Commit Graph

6122 Commits

Author SHA1 Message Date
Marek Olšák 91e533c6aa radeonsi: report correct maximum compute grid sizes
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16901>
2022-06-08 10:23:20 +00:00
Marek Olšák ecda7be628 radeonsi: increase the max compute LDS size to 64KB for gfx7+
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16901>
2022-06-08 10:23:19 +00:00
Pierre-Eric Pelloux-Prayer b81f05e94d radeonsi: set size in si_texture_get_handle
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6507
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6491
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16813>
2022-06-08 09:42:47 +02:00
Marek Olšák ad8f9d5d58 gallium: rename PIPE_CAP_MAX_SHADER_BUFFER_SIZE -> *_UINT
to imply the maximum of 4GB - 1.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16881>
2022-06-07 00:17:58 -04:00
Marek Olšák fd6b8999d7 gallium: rename PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE->MAX_TEXEL_BUFFER_ELEMENTS_UINT
to allow exposing 4G - 1. The "SIZE" was also a misnomer because it meant
elements. This no longer clamps the size to INT_MAX in st/mesa.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16881>
2022-06-07 00:17:58 -04:00
Marek Olšák 406cf871b2 gallium: rename PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE to *_BUFFER0_*
UBOs will use a larger limit.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16881>
2022-06-07 00:17:57 -04:00
Emma Anholt 8c4b88ee48 gallium+glsl: Remove EmitNoSat/PIPE_CAP_VERTEX_SHADER_SATURATE
The drivers not setting it were:

- nv30, which gets lowering using NIR's lower_fsat flag.
- r300, which gets lowering using NIR's lower_fsat flag.
- a2xx, which has was getting it optimized back to fsat anyway.

This drops the check for the cap from gallium nine.  While nine does have
a non-nir path, I think it's safe to assume that if you have SM3
texturing, you can do fsat.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16823>
2022-06-07 02:38:42 +00:00
Qiang Yu 61c500ee9b radeonsi: replace llvm ls/hs interface lds ops with nir lowered ones
Use ac nir lower pass to generate these lds load/store ops explicitly.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16418>
2022-06-07 01:40:14 +00:00
Qiang Yu 87dfff3e6b radeonsi: add tcs_vgpr_only_inputs parameter to si_get_nir_shader
Will be used later.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16418>
2022-06-07 01:40:14 +00:00
Qiang Yu 47dd3525fb radeonsi: implement load_lshs_vertex_stride abi
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16418>
2022-06-07 01:40:14 +00:00
Timothy Arceri 26ff49038c gallium: remove PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT CAP
This is used for the old, buggy and slow GLSL IR loop unrolling
code. All drivers have now switched to the NIR unrolling code so
here we remove the CAP.

Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16366>
2022-06-04 16:11:49 +00:00
SureshGuttula 5d0f922834 Revert "radeon: hardcode uvd/vce encoder not_referenced value to false"
This reverts commit 96b276b327.

This patch enable SVC encoding support on VCE/UVD.

Signed-off-by: Suresh Guttula <suresh.guttula@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16768>
2022-06-03 17:46:28 +00:00
Erik Faye-Lund 69d55f42b6 radeonsi: port amdgcn_glslc build to meson
Seems nice to reduce the number of old-fashioned build systems we have
in-tree.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16789>
2022-06-02 08:54:08 +00:00
Daniel Schürmann bd151a256e nir/opt_vectorize: add callback for max vectorization width
The callback allows to request different vectorization factors
per instruction depending on e.g. bitsize or opcode.

This patch also removes using the vectorize_vec2_16bit option
from nir_opt_vectorize().

Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13080>
2022-06-01 11:41:44 +00:00
Emma Anholt 7472bb4bad glsl,nir: Move i/umulExtended lowering to NIR.
NIR already has the necessary lowering, and the GLSL lowering violates
GLSL IR validation rules.  Once quadop lowering was turned off, the IR
validation at the end of the compile path on DEBUG builds caught the
problem.

In order to move the lowering to NIR, though, we need to make sure that
drivers supporting these functions actually have the lowering flag set.

xfails added for t860, where apparently this tickles a variety of existing
64-bit bugs in the backend.

Fixes: #6461
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Mykhailo Skorokhodov <mykhailo.skorokhodov@globallogic.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16437>
2022-06-01 10:56:35 +00:00
Timothy Arceri abe4536c51 ci: uprev piglit 2022-05-31
Also document additional piglit failures and passes.

Multiple changes, mostly notable:
  - few new tests
  - fixed test for upcoming mesa MR

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16785>
2022-06-01 03:14:29 +00:00
Jason Ekstrand 2a22885a45 st,nir: Use nir_shader::xfb_info in nir_lower_io_passes
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16750>
2022-05-31 23:09:30 +00:00
Pierre-Eric Pelloux-Prayer dad36b5f12 radeonsi: enable use_waterfall_for_divergent_tex_samplers
And run the nir_divergence_analysis pass in si_get_nir_shader to make
sure it's up to date.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2253
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16709>
2022-05-31 13:08:07 +00:00
SureshGuttula f2e3646321 Revert "radeonsi: Set display_remote for non-refernced frames"
This reverts commit ef76b83633.
Reason for revert: This only helps in using I MBs.To further
fix in dpb , reverting this.

Fix added : https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16745

Signed-off-by: SureshGuttula <suresh.guttula@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16744>
2022-05-29 00:07:47 +00:00
SureshGuttula 77a6feff89 radeonsi/vcn : update enc->dpb ref_use for index 0
Currently dpb_enc referneces not updated properly when index 0, as
we are skipping clearing that ref.

This patch will fix this for index 0. So that when ever we set
non_referenced flag, that is not used as ref and not pushed to DPB.
This is helping in SVC encoding.

Signed-off-by: SureshGuttula <suresh.guttula@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16745>
2022-05-28 15:52:53 +00:00
David Heidelberg 0a9461caf5 ci/radeonsi: add RoR and Nheko traces
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16633>
2022-05-27 06:51:38 +00:00
SureshGuttula ef76b83633 radeonsi: Set display_remote for non-refernced frames
When we do SVC temporal encoding, we see output bitsream is not proper. To fix
this , incase of SVC passing session init varaible display_remote as enable.

Signed-off-by: SureshGuttula <suresh.guttula@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16468>
2022-05-26 12:26:53 +00:00
Vlad Zahorodnii e20718e8fa radeonsi: Add support for EGL_IMG_context_priority
This allows creating high priority contexts when using radeonsi. It's
primarily intended for apps whose rendering commands must be processed
as soon as possible, e.g. wayland compositors.

Signed-off-by: Vlad Zahorodnii <vlad.zahorodnii@kde.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16594>
2022-05-25 14:15:30 +00:00
Vlad Zahorodnii f4de4453cf winsys/amdgpu-radeon: Allow specifying context priority
This is needed to implement EGL_IMG_context_priority in radeonsi.

Signed-off-by: Vlad Zahorodnii <vlad.zahorodnii@kde.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16594>
2022-05-25 14:15:30 +00:00
Pierre-Eric Pelloux-Prayer ef950d370a radeonsi: don't use sel->nir in si_check_blend_dst_sampler_noop
We don't want to modify sel->nir so force the use of the serialized
version of the shader.
Waiting on sel->ready guarantees that sel->nir will be NULL and that
si_get_nir_shader will use sel->nir_binary.

Fixes: b78a38bd02 ("radeonsi: use si_nir_is_output_const_if_tex_is_const")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6415
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16587>
2022-05-25 12:03:34 +00:00
Pierre-Eric Pelloux-Prayer e87135c552 radeonsi/tests: use a smaller tests-per-group value
Faster glcts runs (44 -> 34 sec).

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16580>
2022-05-20 09:57:14 +02:00
Pierre-Eric Pelloux-Prayer c2892b811a radeonsi/tests: add a --slow option
Some glcts tests implement tons of tests because they verify
every possible combination of format/swizzle/target/...

They take a long time to execute and aren't possible to run
using multiple processes.

The proper way to fix it would be to split them in vk-gl-cts,
as is already done for some of them (eg es31fTextureGatherTests.cpp).

In the meantime, not running them makes glcts run almost
10 times faster.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16580>
2022-05-20 09:57:05 +02:00
Qiang Yu cc4d5b1666 radeonsi: lower nir_intrinsic_sparse_residency_code_and
This is required by lower_tg4_offsets which split one
sparseTextureGatherOffsetsARB call to four sparseTextureGatherOffsetARB
calls and merge their resisident results into one.

Fixes: ee040a6b63 ("radeonsi: enable ARB_sparse_texture2")

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16599>
2022-05-20 01:45:12 +00:00
Pierre-Eric Pelloux-Prayer cf9ee6d432 radeonsi: wait for PS idle in si_set_framebuffer_state
This is needed to avoid write-after-read hazards in
texture -> render transitions.

This fixes fbo-depth tests that were flaky on GPUs (at
least sienna_cichlid and vega20).

Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16561>
2022-05-19 12:22:11 +00:00
Marek Olšák 2443054932 amd: rename fishes to Navi21, Navi22, Navi23, Navi24, and Rembrandt
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16604>
2022-05-19 11:55:50 +00:00
Indrajit Kumar Das 03bc7503d4 radeonsi: save the fs constant buffer to the util blitter context
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15318>
2022-05-19 11:18:30 +00:00
Pierre-Eric Pelloux-Prayer 74a172a448 radeonsi: fix glTexBuffer max size handling
The spec says the number of texels must be clamped to the value of
GL_MAX_TEXTURE_BUFFER_SIZE.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16480>
2022-05-18 10:36:01 +02:00
Sil Vilerino d2871e40e0 gallium radeon/r600/omx/va: Adds support for multiple reference encoding
gallium: pipe_h264_enc_picture_desc: ref_idx_lx to ref_idx_lx_list[32], add num_ref_idx_lx_active_minus1
gallium radeon/r600: Change usage of ref_idx_lx to ref_idx_lx_list
gallium omx: Fill out ref_idx_lx_list, num_ref_idx_lx_active_minus1
gallium va: Add support for multiple references encoding

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16286>
2022-05-17 21:02:25 +00:00
Sil Vilerino 15540abf22 gallium/va/radeonsi: Using private as a parameter name conflicts with C++ keywords
Reviewed-by: Leo Liu <leo.liu@amd.com>
Acked-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16286>
2022-05-17 21:02:25 +00:00
Marek Olšák ad50daa982 radeonsi: fix resource_copy_region with ETC formats (e.g. for Stoney)
Only Stoney, Vega10, Raven, and Raven2 support ETC.

Fixed tests:
  dEQP-GLES31.functional.copy_image.mixed.viewclass_64_bits_mixed.r11_eac_rgba16i.texture2d_to_texture2d
  dEQP-GLES31.functional.copy_image.mixed.viewclass_64_bits_mixed.r11_eac_rgba16ui.texture2d_to_texture2d
  dEQP-GLES31.functional.copy_image.mixed.viewclass_64_bits_mixed.signed_r11_eac_rgba16i.texture2d_to_texture2d
  dEQP-GLES31.functional.copy_image.mixed.viewclass_64_bits_mixed.signed_r11_eac_rgba16ui.texture2d_to_texture2d

Fixes: cf1e562fdd - radeonsi: remove compressed and subsampled gfx copy from resource_copy_region
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6431

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16491>
2022-05-17 11:26:25 +00:00
Marek Olšák 1fdc3b0fde radeonsi: move CS preamble emission into the winsys
The preamble will be skipped by the kernel if there is no context switch.

Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
2022-05-17 10:27:04 +00:00
Marek Olšák 32c7805ccc radeonsi: merge all preamble states into one
Tess registers are appended. GS registers are appended or overwritten
if they are already set. There are separate TMZ and non-TMZ preambles.

The preamble will be passed to the kernel as an IB to execute on a context
switch only.

Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
2022-05-17 10:27:04 +00:00
Marek Olšák f46cd73e29 radeonsi/gfx11: optimize attribute stores
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
2022-05-17 10:27:04 +00:00
Marek Olšák 9b20120d57 radeonsi/gfx11: fix VM faults due to the attribute ring
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
2022-05-17 10:27:04 +00:00
Marek Olšák c74d854348 Revert "radeonsi/gfx11: limit MSAA color buffers to the RGBA channel order"
This reverts commit 54d85700a1.

It's an LLVM bug. If you disable AMDGPUImageIntrinsicOptimizer in LLVM,
MSAA is fixed. There is no LLVM command line option to disable it from Mesa.

Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
2022-05-17 10:27:04 +00:00
Marek Olšák a529e4f7ad radeonsi/gfx11: fix the value of VGT_GS_OUT_PRIM_TYPE at the beginning of IBs
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
2022-05-17 10:27:04 +00:00
Marek Olšák a8d2ef8bd6 radeonsi/gfx11: don't insert shader code for GS_PIPELINE_STATS_EMU
GS_PIPELINE_STATS_EMU is always false, so the branches were never entered.

Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
2022-05-17 10:27:04 +00:00
Marek Olšák fcaa9f5096 radeonsi/gfx11: fix alpha-to-coverage with stencil or samplemask export
We can't use UINT16_ABGR for the alpha channel. Always use 32_ABGR.

Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
2022-05-17 10:27:04 +00:00
Marek Olšák af880e591e radeonsi: remove GFX9_MERGED_NUM_USER_SGPR definition
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
2022-05-17 10:27:04 +00:00
Dave Airlie 8198900071 ac/radv: drop info pointer from the ac and radv shader structs
This was being used for one bool, just pass the bool.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16521>
2022-05-17 06:15:25 +00:00
Marek Olšák 3382af7f6a radeonsi/gfx11: set BIG_PAGE for the attribute ring
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16466>
2022-05-16 07:03:41 -04:00
Marek Olšák 8a2f151ef8 radeonsi: print an error when failing to create a context
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16466>
2022-05-16 07:03:41 -04:00
Marek Olšák 6515b3b2dc radeonsi: fix a crash when failing to create a context
When shader_query_buffers is NULL, the code treated as as non-empty.

Fixes: 792a638b03 "radeonsi/gfx10: implement streamout-related queries"

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16466>
2022-05-16 07:03:40 -04:00
Marek Olšák 0755d02456 radeonsi: use AMDGPU_VM_PAGE_NOALLOC to disable MALL (infinity cache)
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16466>
2022-05-16 07:03:39 -04:00
Marek Olšák e9e9086b66 radeonsi: use the new flag AMDGPU_GEM_CREATE_DISCARDABLE
It forces the best placement (usually VRAM) and evictions discard the contents
instead of copying.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16466>
2022-05-16 07:03:39 -04:00
Marek Olšák ac0becc648 radeonsi: use PIPE_RESOURCE_FLAG_UNMAPPABLE and DRIVER_INTERNAL more
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16466>
2022-05-16 07:03:38 -04:00
Marek Olšák ceddd7d49a radeonsi: rename RADEON_FLAG_UNCACHED -> RADEON_FLAG_GL2_BYPASS
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16466>
2022-05-16 07:03:36 -04:00
David Heidelberg 875643feeb ci: uprev piglit 2022-05-10
Also document additional piglit failures and crashes with new tests.

Multiple changes, mostly notable:
 - few new tests
 - traces downloader improvements

Reviewed-by: Emma Anholt <emma@anholt.net>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16428>
2022-05-16 06:33:36 +00:00
Marek Olšák 39800f0fa3 amd: change chip_class naming to "enum amd_gfx_level gfx_level"
This aligns the naming with PAL.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pellou-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16469>
2022-05-13 14:56:22 -04:00
Pierre-Eric Pelloux-Prayer d4e4aa997a radeonsi: store shader variants in an array
Instead of storing them in a linked list, put them in an array
in si_shader_selector. The keys are also stored separatly, to
avoid pointer chasing when searching a variant in si_shader_select_with_key.

This main point here is to simplify the code by storing everything
in the selector instead of splitting the list storage between the selector
and the shaders; this shouldn't affect performance in a meaningful way.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16273>
2022-05-13 14:40:56 +00:00
Pierre-Eric Pelloux-Prayer e549b6fe42 radeonsi: scale the number of shader compiler threads
Instead of spawning all the threads on startup.

This speeds up short lived programs (eg: piglit runs duration is reduced by ±25%),
avoid wasting resources and still make use of multi-threaded capabilities.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16273>
2022-05-13 14:40:56 +00:00
Pierre-Eric Pelloux-Prayer b75b9d5cb4 radeonsi: remove unused params from si_shader_select_with_key
thread_index is always -1, optimized_or_none is always false.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16273>
2022-05-13 14:40:56 +00:00
Marek Olšák 29965f356b ac: replace 5 ac_shader_abi::load_* callbacks with 1 intrinsic_load callback
This merges them into si_llvm_load_intrinsic and reuses load_tess_varyings.

RADV only implemented 1 callback.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16467>
2022-05-13 06:45:31 -04:00
Marek Olšák 535d954914 radeonsi: try to group stage-specific code in si_llvm_translate_nir
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16467>
2022-05-13 06:45:31 -04:00
Marek Olšák 2b7906ea74 radeonsi: get rid of the ambiguous "prologue" word
It has nothing to do with our "prolog" shader parts.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16467>
2022-05-13 06:45:31 -04:00
Marek Olšák 4118717cba radeonsi: cleanups getting rid of the ambigous "epilogue" word
It has nothing to do with our "epilog" shader parts.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16467>
2022-05-13 06:44:57 -04:00
Marek Olšák dc81f0ba46 ac/llvm: remove ac_shader_abi::emit_outputs
it's called last in ac_nir_translate, so call it in the caller.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16467>
2022-05-13 06:44:57 -04:00
Marek Olšák 9a8413aaea radeonsi: inline si_nir_build_llvm
it always returns true

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16467>
2022-05-13 06:44:57 -04:00
Marek Olšák 2a1c711052 ac/llvm: skip s_barrier if tess patches don't cross a wave boundary
If tess patches are wholly in one wave, "s_waitcnt lgkm(0)" is sufficient.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16304>
2022-05-13 09:15:20 +00:00
Marek Olšák 59673001c8 radeonsi: add si_get_tcs_epilog_key
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16304>
2022-05-13 09:15:20 +00:00
Marek Olšák 20bb85e2ec ac/llvm: fix the remaining s_barriers for LLVM 15
LLVM 15 doesn't insert s_waitcnt before barriers.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16304>
2022-05-13 09:15:20 +00:00
Marek Olšák b48d183633 ac/llvm: move the gfx6 optimization for TCS barriers into ac_build_s_barrier
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16304>
2022-05-13 09:15:20 +00:00
Marek Olšák e4882d6b7e ac/llvm: add gl_shader_stage parameter into ac_build_s_barrier
this will be used later

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16304>
2022-05-13 09:15:20 +00:00
Marek Olšák fb51a3c4b0 ac/llvm: replace LLVMBuildFence with ac_build_waitcnt(VSTORE)
No change in LLVM IR.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16304>
2022-05-13 09:15:20 +00:00
Marek Olšák 8d4c0197c3 radeonsi: wait before s_barrier in TCS epilog to fix LLVM 15
Only LGKM is needed here.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16304>
2022-05-13 09:15:20 +00:00
Pierre-Eric Pelloux-Prayer 1f31564607 radeonsi: don't use wave32 for GE on gfx10 if culling is used
This is a workaround for issue #6457: it fixes the rendering and
prevent the hang but I can't explain why.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6457
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16427>
2022-05-12 07:46:04 +00:00
Pierre-Eric Pelloux-Prayer f8d205c400 radeonsi: fix gs_invocation query with NGG
When NGG is active, the GS invocation counter is always incremented, even
if there's no explicit GS.

Implementing the counter manually fixes it:
  * in emit_gs_epilogue for the legacy path
  * in gfx10_ngg_gs_emit_prologue for the ngg path

This fixes piglit's arb_query_buffer_object-qbo test.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15861>
2022-05-12 09:16:11 +02:00
Pierre-Eric Pelloux-Prayer 061f64f351 radeonsi/ngg: reuse the pipeline stats buffer when using atomics
To support PIPE_STAT_QUERY_GS_INVOCATIONS and PIPE_STAT_QUERY_GS_PRIMITIVES
being used at the same time we have to reuse the same buffer.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15861>
2022-05-12 09:16:11 +02:00
Pierre-Eric Pelloux-Prayer 0cb6fd0b00 radeonsi/query: use the qbo correct size
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15861>
2022-05-12 09:16:11 +02:00
Pierre-Eric Pelloux-Prayer 58004dfcc9 radeonsi/test: update sienna_cichlid results
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15861>
2022-05-12 09:16:11 +02:00
Pierre-Eric Pelloux-Prayer 38e8a73e14 radeonsi: implement GL_GEOMETRY_SHADER_PRIMITIVES_EMITTED_ARB in shaders
Statistics only work in non-NGG mode. If screen->use_ngg is true, we can't
know if the draw will actually use NGG or not, so this commit switch
to a shader based implementation of this counter.

To avoid modifying si_query, the shader implementation behaves like the hw
one: it uses the same buffer size and offset.

The emulation path activation in the shader is controlled by vs_state_bit[31].

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15861>
2022-05-12 09:16:11 +02:00
Pierre-Eric Pelloux-Prayer bbaf4f1954 radeonsi: store the pipeline stats index
Will be used in later commits.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15861>
2022-05-12 09:16:11 +02:00
Pierre-Eric Pelloux-Prayer 637f09f10e radeonsi: deduplicate query offsets
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15861>
2022-05-12 09:16:11 +02:00
Pierre-Eric Pelloux-Prayer d3a5f411a3 radeonsi: implement pipeline stats workaround
DISABLE_INSTANCE_PACKING needs to be enabled when stats queries are
active to fix incorrect results.

We need to emit this for indexed and non-indexed draws.

Based on PAL's waDisableInstancePacking.

This fixes:
  KHR-GL46.pipeline_statistics_query_tests_ARB.functional_primitives_vertices_submitted_and_clipping_input_output_primitives

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15861>
2022-05-12 09:16:10 +02:00
Pierre-Eric Pelloux-Prayer 283730f368 radeonsi: flush VGT streamout like PAL
Ported from 165b016bbe.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15861>
2022-05-12 09:16:10 +02:00
Marek Olšák 98ea2347a0 radeonsi: report more missing/broken texture formats as unsupported on gfx6-9
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16386>
2022-05-11 06:21:11 +00:00
Marek Olšák e4283708f0 radeonsi: report 10_10_10_2 scaled formats as unsupported on gfx6-9 as well
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16386>
2022-05-11 06:21:11 +00:00
Vinson Lee 997dc0a5e8 radeonsi: Move NULL check before dereference.
Fix defect reported by Coverity Scan.

Dereference before null check (REVERSE_INULL)
check_after_deref: Null-checking desc suggests that it may be
null, but it has already been dereferenced on all paths leading to
the check.

Fixes: 2f83dce059 ("radeonsi: don't report R64_*INT as a sampler format because it doesn't work")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16380>
2022-05-11 04:55:35 +00:00
Dave Airlie 14b1ed1ce1 radeonsi: port tess ring calcs to the common helper.
This uses the common helper code to implement the tess ring sizing.

One question is if radeonsi should be using tess_offchip_ring_offset
in some places it's using tess_factor_ring_size?

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16415>
2022-05-11 02:08:08 +00:00
Jason Ekstrand 3c07c3e16d shader_info: Make images_used a bitset
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15988>
2022-05-10 11:23:11 -05:00
Pierre-Eric Pelloux-Prayer 2b28668d1d radeonsi/tests: reformat with black
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16347>
2022-05-10 09:21:45 +00:00
Pierre-Eric Pelloux-Prayer 9d157755b8 radeonsi/tests: add a heuristic to pick the baseline
When the baseline for the exact GPU tested isn't available,
try to make a reasonnable guess: look for another baseline
from a GPU in the same class.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16347>
2022-05-10 09:21:45 +00:00
Pierre-Eric Pelloux-Prayer 2ca64c1214 radeonsi/tests: allow empty line and comments in csv files
This will help describe why tests are failing.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16347>
2022-05-10 09:21:45 +00:00
Marek Olšák 7203723120 amd: rename RING_* enums to AMD_IP_*
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16360>
2022-05-10 06:59:55 +00:00
Marek Olšák ae7e4d7619 amd: rename ring_type --> amd_ip_type and match the kernel enum values
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16360>
2022-05-10 06:59:55 +00:00
Emma Anholt f3df3d4c80 glsl: Make all drivers take the GLSLOptimizeConservatively path.
Now that all consumers of GLSL use NIR, make the remaining drivers take
the path that relies on NIR to really do optimization.

nouveau steam shader-db runtime -6.69631% +/- 1.29235% (n=12).
No change on shader-db there.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16364>
2022-05-10 05:03:34 +00:00
Marek Olšák d100c07c48 radeonsi: remove tautologies when setting CU_EN
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:55 +00:00
Ruijing Dong 74bd5bbf28 radeonsi/vcn: update av1 decoding to support vcn4
Apply changes of vcn4 on av1 decoding.

Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:55 +00:00
Ruijing Dong 62bb11a5a5 radeonsi/vcn: Add support of array_mode for gfx11
Update array_mode for gfx11 in vcn decoder.

Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:55 +00:00
James Zhu 88075b7ea1 radeonsi/vcn: add jpeg decode support for gfx11
Add jpeg decode support for gfx11.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:55 +00:00
Boyuan Zhang b00ab763a9 radeonsi/vcn: enable vcn 4.0 encode for gfx11 asic
Enable VCN 4.0 encode for supported Asics.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:55 +00:00
Boyuan Zhang efde05c631 radeonsi/vcn: add session init ib for vcn 4.0
Implement session init ib based on new interface for VCN 4.0.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:55 +00:00
Boyuan Zhang dbd75e0d48 radeonsi/vcn: add encode context ib for vcn 4.0
Implement encode context ib based on new reconstructed picture and
interface for VCN 4.0, and modify dpb setup accordingly.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:55 +00:00
Boyuan Zhang 38a95f2109 radeonsi/vcn: add vcn 4.0 encode fw interface version
Add major and minor encode FW interface version for VCN 4.0.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:55 +00:00
Boyuan Zhang ff2b2584fc radeonsi/vcn: add vcn 4.0 encode support
Add new file "radeon_vcn_enc_4_0.c" for VCN 4.0 encode.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:55 +00:00
James Zhu f9de35a731 radeonsi/vcn: add decode software ring support for gfx11
Add decode software ring support for gfx11.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:55 +00:00
James Zhu b8a3bafe94 radeonsi/gfx11: update codec support for gfx11
Update codec support for gfx11.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:55 +00:00
James Zhu 69f02164b3 amd: update headers to support decode software ring
Update headers to support decode software ring.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:55 +00:00
Marek Olšák 2e4e39837a radeonsi/gfx11: add a workaround for CB perf counters
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:55 +00:00
Marek Olšák e3b4e1fe85 radeonsi: inline si_cp_dma_prefetch in si_draw_vbo for lower overhead
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:55 +00:00
Marek Olšák 1bc6d6c933 radeonsi/gfx11: limit CP DMA to max 32KB sizes
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:55 +00:00
Marek Olšák 3bc754a9a6 radeonsi/gfx11: mark streamout as unimplemented for now
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:55 +00:00
Marek Olšák 66d4bafd5b radeonsi/gfx11: resolve MSAA using u_blitter
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:55 +00:00
Marek Olšák 8bfb4657c8 radeonsi/gfx11: don't count the non-existent scratch_byte_offset SGPR
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:55 +00:00
Marek Olšák c65a303f53 radeonsi/gfx11: change LDS allocation granularity for PS
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:55 +00:00
Marek Olšák c749b6f6ae radeonsi/gfx11: update the initialization of SGPR0/1 registers for HS and GS
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:55 +00:00
Marek Olšák 54d85700a1 radeonsi/gfx11: limit MSAA color buffers to the RGBA channel order
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:55 +00:00
Yogesh mohan marimuthu 6531ec8922 ac,radeonsi/gfx11: swizzle MRT0/1 for dual source blending
If dual source blending is enabled, use export targets 21 and 22.
Also we have to swap odd/even lanes between export target 21 and 22.

Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:55 +00:00
Yogesh Mohan Marimuthu 12a606c1bd radeonsi/gfx11: export alpha through mrtz for alpha-to-coverage if mrtz is there
If both mrtz and alpha-to-coverage are enabled, the alpha channel must
be exported through mrtz.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:55 +00:00
Indrajit Kumar Das 167b378377 radeonsi/gfx11: VRS changes
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:55 +00:00
Marek Olšák 6d0e50f226 radeonsi/gfx11: TF_RING_SIZE changed to a per-SE size
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:55 +00:00
Marek Olšák ce950f1d96 radeonsi/gfx11: don't use FLUSH_AND_INV_DB_META
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:55 +00:00
Marek Olšák c33a930cea radeonsi/gfx11: emit SQ_NON_EVENT for tessellation at the end of IBs
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:55 +00:00
Marek Olšák b27b9b0c31 radeonsi/gfx11: don't set non-existent CP_COHER_START_DELAY
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:55 +00:00
Yogesh mohan marimuthu 19a59f05a4 radeonsi/gfx11: program db render control register
Signed-off-by: Yogesh mohan marimuthu <yogesh.mohanmarimuthu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:55 +00:00
Marek Olšák 9fecac091f radeonsi/gfx11: scattered register deltas
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:55 +00:00
Marek Olšák afc110a1f6 radeonsi/gfx11: implement attributes through memory
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:55 +00:00
Marek Olšák 91a7f43f0b radeonsi/gfx11: don't set COMPR for exports, use 0x3 channel mask instead
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:55 +00:00
Yogesh Mohanmarimuthu 6e537680c4 radeonsi/gfx11: use PIXEL_PIPE_STATE_DUMP event instead of ZPASS_DONE
Use PIXEL_PIPE_STATE_CONTROL/DUMP event instead of ZPASS_DONE for gfx11.

Signed-off-by: Yogesh Mohanmarimuthu <yogesh.mohanmarimuthu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:55 +00:00
Marek Olšák 2a1c22e0cd radeonsi/gfx11: don't set non-existent SPI_SHADER_USER_DATA_VS_x
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:54 +00:00
Marek Olšák 61291aff1f ac,radeonsi/gfx11: set SWIZZLE_ENABLE correctly
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:54 +00:00
Marek Olšák a90ff631a5 ac,radeonsi/gfx11: remove FMASK loads
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:54 +00:00
Marek Olšák 529eb739fc radeonsi/gfx11: add CB deltas
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:54 +00:00
Marek Olšák c99b71039a radeonsi/gfx11: buffer descriptor changes
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:54 +00:00
Pierre-Eric Pelloux-Prayer c87da5c80d radeonsi/gfx11: image descriptor changes
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:54 +00:00
Pierre-Eric Pelloux-Prayer 25a66477d0 radeonsi/gfx11: register changes
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:54 +00:00
Pierre-Eric Pelloux-Prayer 3bdb3db5fa radeonsi/gfx11: add assert in legacy vs path
Only ngg should be used.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:54 +00:00
Yogesh mohan marimuthu 1005a2a25f radeonsi/gfx11: program inst_pref_size for compute
For gfx11, program INST_PREF_SIZE value in SPI registers.

v2: move INST_PREF_SIZE reg programming (Marek Olšák)

Signed-off-by: Yogesh mohan marimuthu <yogesh.mohanmarimuthu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:54 +00:00
Marek Olšák 980620ae07 radeonsi/gfx11: program inst_pref_size for graphics
For gfx11, program INST_PREF_SIZE value in SPI registers.

v4: fix mask value, code indendation (Marek Olšák)
v3: improve code for readability (Indrajit Das, Marek Olšák)
v2: ngg is always enabled in gfx11 (Marek Olšák)

Signed-off-by: Yogesh mohan marimuthu <yogesh.mohanmarimuthu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:54 +00:00
Yogesh mohan marimuthu 3b0bfd254f radeonsi/gfx11: make flat_scratch changes for compute
make flat_scratch gen11 changes for compute

v5: optimize the code for size (Pierre-Eric)
v4: remove type cast from 64bit to 32bit (Marek Olšák)
    use radeon_set_sh_reg_seq (Marek Olšák)
    combine RSRC and scratch reg write packets (Marek Olšák)
v3: fix coding guidelines (Marek Olšák)
v2: do not skip si_resource_reference() call (Marek Olšák)

Signed-off-by: Yogesh mohan marimuthu <yogesh.mohanmarimuthu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:54 +00:00
Yogesh mohan marimuthu 02367b29c7 radeonsi/gfx11: make flat_scratch changes for graphics
gfx11 passes scratch base address using
SPI_GFX_SCRATCH_BASE_LO and _HI registers. Make the
code changes to support the same.

v5: remove type cast from 64bit to 32bit (Marek Olšák)
v4: combine scratch_memory and scratch_state atom (Marek Olšák)
v3: skip shader relocs for gfx11
v2: make atom for scratch_memory (Indrajit)

Signed-off-by: Yogesh mohan marimuthu <yogesh.mohanmarimuthu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:54 +00:00
Marek Olšák 27104ff647 radeonsi/gfx11: use the new TCS WaveID SGPR to compute vs_rel_patch_id
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:54 +00:00
Marek Olšák ced20893d4 radeonsi/gfx11: enable arbitrary DCC format reinterpretation
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:54 +00:00
Marek Olšák 7c423a7ad0 radeonsi/gfx11: enable NGG-only draw paths
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:54 +00:00
Marek Olšák 7bd4dd79c8 radeonsi/gfx11: expect packed threadID VGPRs
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:54 +00:00
Marek Olšák 700c2e74fb radeonsi/gfx11: always allow DCC stores
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:54 +00:00
Marek Olšák 0f033ce3a3 radeonsi/gfx11: increase the hw screen offset alignment
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:54 +00:00
Pierre-Eric Pelloux-Prayer 9480ad2b1c amd: update gfx10_format_table.py for gfx11
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:54 +00:00
Marek Olšák 980b7f75e8 amd: enable gfx11 in header generator, fix drivers with renamed gfx6-10 defs
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
2022-05-10 04:29:54 +00:00
Sathishkumar S 324898f5c6 radeon/vcn: engage all available jpeg engines
use multiple contexts and submit in a round robin scheme to make
use of all the available jpeg engines simultaneously. During mjpeg
decode context need not be same across frames as they are discrete
jpeg images.

V2: number of ctx to be equal to number of engines and fix indent (Leo)
V3: decide ctx count in create_decoder, don't add a video param (Boyuan)

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16355>
2022-05-09 19:00:01 +00:00
Georg Lehmann 56070d3322 radeonsi: Use nir_fold_16bit_image_load_store_conversions.
Remove conversions using d16 image_load/image_store.

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16319>
2022-05-08 00:00:41 +00:00
Emma Anholt e9b491f9b5 gallium: Remove now-unused shader caps.
The only interesting ones here were LOWER_IF_THRESHOLD (which previously
had connected to some lowering in GLSL that was broken in the face of side
effects), and FMA (which turned GLSL IR's fma() into TGSI_OPCODE_FMA
instead of MAD).

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8044>
2022-05-05 22:25:03 +00:00
Guilherme Gallo 7a6d85299c ci: Fix tests expectations
For some days, the CI was bypassing LAVA and bare-metal jobs due to an
issue in the init-stage2.sh script. After the fix some tests
crashed/failed. This commit updates the expectations for them.

Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16325>
2022-05-04 23:39:15 +00:00
Samuel Pitoiset 4f9ae10296 ac,radeonsi: add has_sqtt_auto_flush_mode_bug
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16303>
2022-05-04 16:13:49 +00:00
Marek Olšák a0dad2f1db radeonsi: remove si_create_surface_custom
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16215>
2022-05-03 11:11:08 -04:00