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radeonsi/gfx11: program inst_pref_size for compute 

For gfx11, program INST_PREF_SIZE value in SPI registers.

v2: move INST_PREF_SIZE reg programming (Marek Olšák)

Signed-off-by: Yogesh mohan marimuthu <yogesh.mohanmarimuthu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
This commit is contained in:
Yogesh mohan marimuthu 2021-08-24 12:53:06 +05:30 committed by Marge Bot
parent 980620ae07
commit 1005a2a25f
1 changed files with 9 additions and 2 deletions
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11
src/gallium/drivers/radeonsi/si_compute.c
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@ -438,14 +438,16 @@ void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf
}
if (sctx->chip_class >= GFX10) {
radeon_set_sh_reg_seq(R_00B890_COMPUTE_USER_ACCUM_0, 5);
radeon_set_sh_reg_seq(R_00B890_COMPUTE_USER_ACCUM_0, 4);
radeon_emit(0); /* R_00B890_COMPUTE_USER_ACCUM_0 */
radeon_emit(0); /* R_00B894_COMPUTE_USER_ACCUM_1 */
radeon_emit(0); /* R_00B898_COMPUTE_USER_ACCUM_2 */
radeon_emit(0); /* R_00B89C_COMPUTE_USER_ACCUM_3 */
radeon_emit(0); /* R_00B8A0_COMPUTE_PGM_RSRC3 */
radeon_set_sh_reg(R_00B9F4_COMPUTE_DISPATCH_TUNNEL, 0);
if (sctx->chip_class < GFX11)
radeon_set_sh_reg(R_00B8A0_COMPUTE_PGM_RSRC3, 0);
}
radeon_end();
}
@ -551,6 +553,11 @@ static bool si_switch_compute_shader(struct si_context *sctx, struct si_compute
radeon_begin(cs);
radeon_set_sh_reg(R_00B830_COMPUTE_PGM_LO, shader_va >> 8);
if (sctx->chip_class >= GFX11) {
radeon_set_sh_reg(R_00B8A0_COMPUTE_PGM_RSRC3,
S_00B8A0_INST_PREF_SIZE(si_calc_inst_pref_size(shader)));
}
if (sctx->chip_class >= GFX11 && shader->scratch_bo) {
radeon_set_sh_reg_seq(R_00B840_COMPUTE_DISPATCH_SCRATCH_BASE_LO, 4);
radeon_emit(sctx->compute_scratch_buffer->gpu_address >> 8);