gallium: rename PIPE_CAP_MAX_SHADER_BUFFER_SIZE -> *_UINT

to imply the maximum of 4GB - 1.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16881>
This commit is contained in:
Marek Olšák 2022-06-05 20:55:50 -04:00
parent fd6b8999d7
commit ad8f9d5d58
19 changed files with 20 additions and 20 deletions

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@ -520,8 +520,8 @@ The integer capabilities:
```set_sample_locations```.
* ``PIPE_CAP_MAX_GS_INVOCATIONS``: Maximum supported value of
TGSI_PROPERTY_GS_INVOCATIONS.
* ``PIPE_CAP_MAX_SHADER_BUFFER_SIZE``: Maximum supported size for binding
with set_shader_buffers.
* ``PIPE_CAP_MAX_SHADER_BUFFER_SIZE_UINT``: Maximum supported size for binding
with set_shader_buffers. This is unsigned integer with the maximum of 4GB - 1.
* ``PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS``: Maximum total number of shader
buffers. A value of 0 means the sum of all per-shader stage maximums (see
``PIPE_SHADER_CAP_MAX_SHADER_BUFFERS``).

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@ -375,7 +375,7 @@ u_pipe_screen_get_param_defaults(struct pipe_screen *pscreen,
case PIPE_CAP_MAX_GS_INVOCATIONS:
return 32;
case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
case PIPE_CAP_MAX_SHADER_BUFFER_SIZE_UINT:
return 1 << 27;
case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:

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@ -294,7 +294,7 @@ crocus_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
return CROCUS_MAP_BUFFER_ALIGNMENT;
case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
return devinfo->ver >= 7 ? 4 : 0;
case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
case PIPE_CAP_MAX_SHADER_BUFFER_SIZE_UINT:
return devinfo->ver >= 7 ? (1 << 27) : 0;
case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
return 16; // XXX: u_screen says 256 is the minimum value...

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@ -423,7 +423,7 @@ i915_get_param(struct pipe_screen *screen, enum pipe_cap cap)
case PIPE_CAP_MAX_GS_INVOCATIONS:
return 32;
case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
case PIPE_CAP_MAX_SHADER_BUFFER_SIZE_UINT:
return 1 << 27;
case PIPE_CAP_MAX_VIEWPORTS:

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@ -335,7 +335,7 @@ iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
return IRIS_MAP_BUFFER_ALIGNMENT;
case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
return 4;
case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
case PIPE_CAP_MAX_SHADER_BUFFER_SIZE_UINT:
return 1 << 27;
case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
return 16; // XXX: u_screen says 256 is the minimum value...

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@ -339,7 +339,7 @@ llvmpipe_get_param(struct pipe_screen *screen, enum pipe_cap param)
case PIPE_CAP_MAX_GS_INVOCATIONS:
return 32;
case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
case PIPE_CAP_MAX_SHADER_BUFFER_SIZE_UINT:
return LP_MAX_TGSI_SHADER_BUFFER_SIZE;
case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
case PIPE_CAP_TGSI_TG4_COMPONENT_IN_SWIZZLE:

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@ -258,7 +258,7 @@ nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_MAX_GS_INVOCATIONS:
return 32;
case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
case PIPE_CAP_MAX_SHADER_BUFFER_SIZE_UINT:
return 1 << 27;
case PIPE_CAP_VENDOR_ID:
return 0x10de;

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@ -155,7 +155,7 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
return 1;
case PIPE_CAP_MAX_GS_INVOCATIONS:
return 0;
case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
case PIPE_CAP_MAX_SHADER_BUFFER_SIZE_UINT:
return 1 << 27;
case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
return 2048;

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@ -162,7 +162,7 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
return 4;
case PIPE_CAP_MAX_GS_INVOCATIONS:
return 32;
case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
case PIPE_CAP_MAX_SHADER_BUFFER_SIZE_UINT:
return 1 << 27;
case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
return 2048;

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@ -180,7 +180,7 @@ static int r300_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
case PIPE_CAP_MAX_GS_INVOCATIONS:
return 32;
case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
case PIPE_CAP_MAX_SHADER_BUFFER_SIZE_UINT:
return 1 << 27;
/* SWTCL-only features. */

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@ -405,7 +405,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
return 32;
/* shader buffer objects */
case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
case PIPE_CAP_MAX_SHADER_BUFFER_SIZE_UINT:
return 1 << 27;
case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS:
return 8;

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@ -234,7 +234,7 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
return 4096 * 1024;
case PIPE_CAP_MAX_TEXEL_BUFFER_ELEMENTS_UINT:
case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
case PIPE_CAP_MAX_SHADER_BUFFER_SIZE_UINT:
/* Allow max 512 MB to pass CTS with a 32-bit build. */
return MIN2(sscreen->info.max_alloc_size, 512 * 1024 * 1024);
case PIPE_CAP_MAX_TEXTURE_MB:

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@ -304,7 +304,7 @@ softpipe_get_param(struct pipe_screen *screen, enum pipe_cap param)
return 0;
case PIPE_CAP_MAX_GS_INVOCATIONS:
return 32;
case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
case PIPE_CAP_MAX_SHADER_BUFFER_SIZE_UINT:
return 1 << 27;
case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
return 4;

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@ -455,7 +455,7 @@ svga_get_param(struct pipe_screen *screen, enum pipe_cap param)
return 1;
case PIPE_CAP_MAX_GS_INVOCATIONS:
return 32;
case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
case PIPE_CAP_MAX_SHADER_BUFFER_SIZE_UINT:
return 1 << 27;
/* Verify this once protocol is finalized. Setting it to minimum value. */
case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:

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@ -322,7 +322,7 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_CLIP_HALFZ;
case PIPE_CAP_MAX_GS_INVOCATIONS:
return 32;
case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
case PIPE_CAP_MAX_SHADER_BUFFER_SIZE_UINT:
return 1 << 27;
case PIPE_CAP_VENDOR_ID:
return 0x1af4;

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@ -735,7 +735,7 @@ zink_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
/* gallium handles this automatically */
return 0;
case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
case PIPE_CAP_MAX_SHADER_BUFFER_SIZE_UINT:
/* 1<<27 is required by VK spec */
assert(screen->info.props.limits.maxStorageBufferRange >= 1 << 27);
/* but Gallium can't handle values that are too big, so clamp to VK spec minimum */

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@ -260,7 +260,7 @@ lvp_physical_device_init(struct lvp_physical_device *device,
.maxImageArrayLayers = device->pscreen->get_param(device->pscreen, PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS),
.maxTexelBufferElements = device->pscreen->get_param(device->pscreen, PIPE_CAP_MAX_TEXEL_BUFFER_ELEMENTS_UINT),
.maxUniformBufferRange = min_shader_param(device->pscreen, PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE),
.maxStorageBufferRange = device->pscreen->get_param(device->pscreen, PIPE_CAP_MAX_SHADER_BUFFER_SIZE),
.maxStorageBufferRange = device->pscreen->get_param(device->pscreen, PIPE_CAP_MAX_SHADER_BUFFER_SIZE_UINT),
.maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
.maxMemoryAllocationCount = UINT32_MAX,
.maxSamplerAllocationCount = 32 * 1024,

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@ -925,7 +925,7 @@ enum pipe_cap
PIPE_CAP_CONSERVATIVE_RASTER_INNER_COVERAGE,
PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS,
PIPE_CAP_MAX_GS_INVOCATIONS,
PIPE_CAP_MAX_SHADER_BUFFER_SIZE,
PIPE_CAP_MAX_SHADER_BUFFER_SIZE_UINT,
PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE,
PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS,
PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS,

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@ -547,7 +547,7 @@ void st_init_limits(struct pipe_screen *screen,
c->MaxCombinedShaderOutputResources +=
c->MaxCombinedShaderStorageBlocks;
c->MaxShaderStorageBlockSize =
screen->get_param(screen, PIPE_CAP_MAX_SHADER_BUFFER_SIZE);
screen->get_param(screen, PIPE_CAP_MAX_SHADER_BUFFER_SIZE_UINT);
if (c->Program[MESA_SHADER_FRAGMENT].MaxShaderStorageBlocks)
extensions->ARB_shader_storage_buffer_object = GL_TRUE;
}