glsl,nir: Move i/umulExtended lowering to NIR.
NIR already has the necessary lowering, and the GLSL lowering violates GLSL IR validation rules. Once quadop lowering was turned off, the IR validation at the end of the compile path on DEBUG builds caught the problem. In order to move the lowering to NIR, though, we need to make sure that drivers supporting these functions actually have the lowering flag set. xfails added for t860, where apparently this tickles a variety of existing 64-bit bugs in the backend. Fixes: #6461 Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Reviewed-by: Mykhailo Skorokhodov <mykhailo.skorokhodov@globallogic.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16437>
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@ -55,7 +55,6 @@ struct gl_shader_program;
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#define DDIV_TO_MUL_RCP 0x100000
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#define DIV_TO_MUL_RCP (FDIV_TO_MUL_RCP | DDIV_TO_MUL_RCP)
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#define SQRT_TO_ABS_SQRT 0x200000
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#define MUL64_TO_MUL_AND_MUL_HIGH 0x400000
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/* Operations for lower_64bit_integer_instructions() */
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#define DIV64 (1U << 0)
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@ -157,7 +157,6 @@ private:
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void find_msb_to_float_cast(ir_expression *ir);
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void imul_high_to_mul(ir_expression *ir);
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void sqrt_to_abs_sqrt(ir_expression *ir);
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void mul64_to_mul_and_mul_high(ir_expression *ir);
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ir_expression *_carry(operand a, operand b);
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@ -1615,66 +1614,6 @@ lower_instructions_visitor::sqrt_to_abs_sqrt(ir_expression *ir)
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this->progress = true;
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}
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void
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lower_instructions_visitor::mul64_to_mul_and_mul_high(ir_expression *ir)
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{
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/* Lower 32x32-> 64 to
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* msb = imul_high(x_lo, y_lo)
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* lsb = mul(x_lo, y_lo)
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*/
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const unsigned elements = ir->operands[0]->type->vector_elements;
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const ir_expression_operation operation =
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ir->type->base_type == GLSL_TYPE_UINT64 ? ir_unop_pack_uint_2x32
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: ir_unop_pack_int_2x32;
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const glsl_type *var_type = ir->type->base_type == GLSL_TYPE_UINT64
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? glsl_type::uvec(elements)
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: glsl_type::ivec(elements);
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const glsl_type *ret_type = ir->type->base_type == GLSL_TYPE_UINT64
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? glsl_type::uvec2_type
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: glsl_type::ivec2_type;
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ir_instruction &i = *base_ir;
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ir_variable *msb =
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new(ir) ir_variable(var_type, "msb", ir_var_temporary);
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ir_variable *lsb =
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new(ir) ir_variable(var_type, "lsb", ir_var_temporary);
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ir_variable *x =
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new(ir) ir_variable(var_type, "x", ir_var_temporary);
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ir_variable *y =
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new(ir) ir_variable(var_type, "y", ir_var_temporary);
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i.insert_before(x);
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i.insert_before(assign(x, ir->operands[0]));
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i.insert_before(y);
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i.insert_before(assign(y, ir->operands[1]));
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i.insert_before(msb);
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i.insert_before(lsb);
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i.insert_before(assign(msb, imul_high(x, y)));
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i.insert_before(assign(lsb, mul(x, y)));
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ir_rvalue *result[4] = {NULL};
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for (unsigned elem = 0; elem < elements; elem++) {
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ir_rvalue *val = new(ir) ir_expression(ir_quadop_vector, ret_type,
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swizzle(lsb, elem, 1),
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swizzle(msb, elem, 1), NULL, NULL);
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result[elem] = expr(operation, val);
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}
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ir->operation = ir_quadop_vector;
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ir->init_num_operands();
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ir->operands[0] = result[0];
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ir->operands[1] = result[1];
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ir->operands[2] = result[2];
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ir->operands[3] = result[3];
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this->progress = true;
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}
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ir_visitor_status
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lower_instructions_visitor::visit_leave(ir_expression *ir)
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{
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@ -1802,15 +1741,6 @@ lower_instructions_visitor::visit_leave(ir_expression *ir)
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imul_high_to_mul(ir);
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break;
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case ir_binop_mul:
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if (lowering(MUL64_TO_MUL_AND_MUL_HIGH) &&
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(ir->type->base_type == GLSL_TYPE_INT64 ||
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ir->type->base_type == GLSL_TYPE_UINT64) &&
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(ir->operands[0]->type->base_type == GLSL_TYPE_INT ||
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ir->operands[1]->type->base_type == GLSL_TYPE_UINT))
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mul64_to_mul_and_mul_high(ir);
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break;
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case ir_unop_rsq:
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case ir_unop_sqrt:
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if (lowering(SQRT_TO_ABS_SQRT))
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@ -3906,6 +3906,7 @@ static const nir_shader_compiler_options nir_to_tgsi_compiler_options = {
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.lower_rotate = true,
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.lower_uniforms_to_ubo = true,
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.lower_vector_cmp = true,
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.lower_int64_options = nir_lower_imul_2x32_64,
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.use_interpolated_input_intrinsics = true,
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};
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@ -619,6 +619,7 @@ static const struct nir_shader_compiler_options gallivm_nir_options = {
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.lower_usub_borrow = true,
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.lower_mul_2x32_64 = true,
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.lower_ifind_msb = true,
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.lower_int64_options = nir_lower_imul_2x32_64,
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.max_unroll_iterations = 32,
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.use_interpolated_input_intrinsics = true,
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.lower_to_scalar = true,
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@ -3393,7 +3393,7 @@ nvir_nir_shader_compiler_options(int chipset)
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((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_logic64 : 0) |
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((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_minmax64 : 0) |
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((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_shift64 : 0) |
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((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_imul_2x32_64 : 0) |
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nir_lower_imul_2x32_64 |
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((chipset >= NVISA_GM107_CHIPSET) ? nir_lower_extract64 : 0) |
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nir_lower_ufind_msb64
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);
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@ -1081,6 +1081,7 @@ void si_init_screen_get_functions(struct si_screen *sscreen)
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.lower_insert_word = true,
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.lower_rotate = true,
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.lower_to_scalar = true,
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.lower_int64_options = nir_lower_imul_2x32_64,
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.has_sdot_4x8 = sscreen->info.has_accelerated_dot_product,
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.has_udot_4x8 = sscreen->info.has_accelerated_dot_product,
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.has_dot_2x16 = sscreen->info.has_accelerated_dot_product,
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@ -88,6 +88,7 @@ static const nir_shader_compiler_options sp_compiler_options = {
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.lower_rotate = true,
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.lower_uniforms_to_ubo = true,
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.lower_vector_cmp = true,
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.lower_int64_options = nir_lower_imul_2x32_64,
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.max_unroll_iterations = 32,
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.use_interpolated_input_intrinsics = true,
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};
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@ -762,6 +762,7 @@ vgpu10_get_shader_param(struct pipe_screen *screen,
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.lower_extract_word = true, \
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.lower_insert_byte = true, \
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.lower_insert_word = true, \
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.lower_int64_options = nir_lower_imul_2x32_64, \
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.lower_fdph = true, \
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.lower_flrp64 = true, \
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.lower_rotate = true, \
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@ -729,6 +729,7 @@ static const nir_shader_compiler_options v3d_nir_options = {
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.lower_wpos_pntc = true,
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.lower_rotate = true,
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.lower_to_scalar = true,
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.lower_int64_options = nir_lower_imul_2x32_64,
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.has_fsub = true,
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.has_isub = true,
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.divergence_analysis_options =
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@ -106,7 +106,6 @@ link_shader(struct gl_context *ctx, struct gl_shader_program *prog)
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FDIV_TO_MUL_RCP |
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EXP_TO_EXP2 |
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LOG_TO_LOG2 |
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MUL64_TO_MUL_AND_MUL_HIGH |
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(have_ldexp ? 0 : LDEXP_TO_ARITH) |
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(have_dfrexp ? 0 : DFREXP_DLDEXP_TO_ARITH) |
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CARRY_TO_ARITH |
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@ -87,3 +87,8 @@ dEQP-GLES31.functional.texture.multisample.samples_3.use_texture_uint_2d,Fail
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dEQP-GLES31.functional.texture.multisample.samples_3.use_texture_uint_2d_array,Fail
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dEQP-GLES31.functional.texture.multisample.samples_4.use_texture_int_2d,Fail
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dEQP-GLES31.functional.texture.multisample.samples_4.use_texture_int_2d_array,Fail
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dEQP-GLES31.functional.shaders.builtin_functions.integer.imulextended.ivec3_highp_compute,Fail
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dEQP-GLES31.functional.shaders.builtin_functions.integer.umulextended.uvec3_highp_compute,Fail
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dEQP-GLES31.functional.shaders.builtin_functions.integer.imulextended.ivec4_highp_vertex,Fail
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dEQP-GLES31.functional.shaders.builtin_functions.integer.umulextended.uvec4_highp_vertex,Fail
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@ -83,6 +83,9 @@ static const nir_shader_compiler_options midgard_nir_options = {
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.lower_unpack_unorm_4x8 = true,
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.lower_unpack_snorm_4x8 = true,
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.lower_pack_split = true,
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.lower_pack_64_2x32_split = true,
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.lower_unpack_64_2x32_split = true,
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.lower_int64_options = nir_lower_imul_2x32_64,
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.lower_doubles_options = nir_lower_dmod,
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