Commit Graph

6122 Commits

Author SHA1 Message Date
Eric Engestrom 2c67457e5e util/list: rename LIST_ENTRY() to list_entry()
This follows the Linux kernel convention, and avoids collision with
macOS header macro.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6751
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6840
Cc: mesa-stable
Signed-off-by: Eric Engestrom <eric@igalia.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17772>
2022-07-28 10:10:44 +00:00
Georg Lehmann df4b5914cd nir/fold_16bit_tex_image: Default to only_fold_all.
No driver doesn't use this option.

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17757>
2022-07-27 18:57:12 +00:00
Georg Lehmann dd3e9be413 radeonsi: Stop using nir_legalize_16bit_sampler_srcs.
This pass is problematic because it truncates sources when there are type
mismatches. With the right nir_fold_16bit_tex_image options we can ensure
that there is never a mismatch.

Other changes: bias is affected by A16 https://reviews.llvm.org/D111754
And enable G16 as we recently confirmed that it's fully independent from A16.

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17757>
2022-07-27 18:57:12 +00:00
Marek Olšák bc85e79bba ac/gpu_info: require amdgpu DRM 3.15.0 (kernel 4.12) from July 2017
to match the radeon requirement

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17411>
2022-07-27 05:01:38 +00:00
Marek Olšák 9f6a64b1c3 gallium/radeon: require radeon DRM 2.50.0 (kernel 4.12) from July 2017
This is the latest radeon DRM version.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17411>
2022-07-27 05:01:38 +00:00
Marek Olšák abd188ec1c radeonsi: remove workarounds for radeon DRM < 2.45.0
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17411>
2022-07-27 05:01:38 +00:00
Marek Olšák b2455e1ccb gallium/radeon: require radeon DRM 2.45.0 from April 2016
This removes most non-radeonsi workarounds.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17411>
2022-07-27 05:01:38 +00:00
Marek Olšák 3657cdafd6 amd: require amdgpu DRM 3.2.0 from April 2016
This removes an early bug workaround.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17411>
2022-07-27 05:01:38 +00:00
Marek Olšák ff19666a0d ac/gpu_info: remove redundant vcn_encode
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17411>
2022-07-27 05:01:38 +00:00
Marek Olšák 89113c0338 ac/gpu_info: remove redundant vce_encode
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17411>
2022-07-27 05:01:38 +00:00
Marek Olšák 9cbbdc6583 ac/gpu_info: remove redundant uvd_encode
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17411>
2022-07-27 05:01:38 +00:00
Marek Olšák 2972ceccfd ac/gpu_info: remove redundant jpeg_decode
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17411>
2022-07-27 05:01:38 +00:00
Marek Olšák a0d2e16c91 ac/gpu_info: remove redundant uvd_decode
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17411>
2022-07-27 05:01:38 +00:00
Marek Olšák 12c5d64fae ac/gpu_info: remove vram_size and gtt_size in favor of *_kb variants
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17411>
2022-07-27 05:01:38 +00:00
Marek Olšák 9552da66cc ac/gpu_info: rework and extend device info to be more informative
This is the result with AMD_DEBUG=info:

Device info:
    name = NAVI23
    marketing_name = AMD Radeon RX 6600
    num_se = 2
    num_rb = 8
    num_cu = 28
    max_gpu_freq = 2750 MHz
    max_gflops = 9856 GFLOPS
    l0_cache_size = 16 KB
    l1_cache_size = 128 KB
    l2_cache_size = 2048 KB
    l3_cache_size = 32 MB
    memory_channels = 8 (TCC blocks)
    memory_size = 8 GB (8192 MB)
    memory_freq = 14 GHz
    memory_bus_width = 128 bits
    memory_bandwidth = 224 GB/s
    clock_crystal_freq = 100000 KHz
    IP GFX     10.3 	queues:1
    IP COMP    10.3 	queues:4
    IP SDMA     5.2 	queues:2
    IP VCN_DEC  3.0 	queues:1
    IP VCN_ENC  3.0 	queues:1
    IP VCN_JPG  3.0 	queues:1

It might not be 100% correct with other chips.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17411>
2022-07-27 05:01:38 +00:00
Marek Olšák f218c3d795 ac/gpu_info: rename info fields to num_cu, memory_bus_width, memory_freq_mhz
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17411>
2022-07-27 05:01:38 +00:00
Boyuan Zhang fef2004b11 radeonsi/vcn/enc: enable cabac entropy mode
Set cabac entropy mode if enabled.

v2: add extra check on radeon driver side, disable cabac if profile is
baseline or extended.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16113>
2022-07-25 13:17:18 +00:00
Marek Olšák 3e94d498b3 gallium: add pipe_blit_info::dst_sample, update u_blitter to write that sample
A new radeonsi blit test will use it to upload different sample values
into MSAA textures.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17694>
2022-07-23 18:21:31 +00:00
Pierre-Eric Pelloux-Prayer af7c2ff842 radeonsi: check last_dirty_buf_counter and dirty_tex_counter
Check both counters in draw and compute, otherwise compute dispatches may
miss buffers invalidation.
This fixes the test case from https://gitlab.freedesktop.org/mesa/piglit/-/merge_requests/702
(both with and without GALLIUM_THREAD=0).

cc: mesa-stable

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17394>
2022-07-23 18:03:22 +00:00
Georg Lehmann 87e3277b82 nir: Rewrite and merge 16bit tex folding pass with 16bit image folding pass.
Allow folding constants/undef sources by sharing more code with the image_store
16bit folding pass.

Allow more than one set of sources because RADV wants two, one for
G16 (ddx/ddy) and one for A16 (all other sources).

Allow folding cube sampling destination conversions on radeonsi/radv because
I think the limitation only applies to sources.

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16978>
2022-07-21 19:15:03 +00:00
Konstantin Seurer 435cb21e11 radeonsi: Remove format desc null checks
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17490>
2022-07-21 12:48:01 +00:00
Konstantin Seurer eb19640d61 radeonsi: Set vertex_id_zero_based
Let NIR lower load_vertex_id instead of LLVM.

Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17539>
2022-07-19 13:26:09 +00:00
Arvind Yadav 1fbc7337a1 radeonsi: Enable nir_lower_point_smooth lowering pass for point smoothing
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15117>
2022-07-16 07:08:33 -04:00
Arvind Yadav 25204d89a6 radeonsi: Add nir_lower_poly_line_smooth pass for polygon and line smoothing
Added a new NIR pass for handling polygon and line smoothing and
Removed previous smoothing changes.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16245>
2022-07-16 10:15:22 +00:00
Boyuan Zhang 3962555db8 radeonsi/vcn: use calculated max hierarchy depth for hevc enc
Certain player has hard coded max_transform_hierarchy_depth_inter and
max_transform_hierarchy_depth_intra values set through VA-API, which
doesn't work on radeon HW. Until properly fixing it on player side,
temporarily adding this workaround to use calculated values instead.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17489>
2022-07-14 14:23:02 +00:00
Yogesh Mohan Marimuthu 1c2ca3cfb7 radeonsi: no need to call si_pm4_clear_state() in si_pm4_free_state()
the si_pm4_clear_state() initializes the variable in struct si_pm4_state which
anyway gets freed in si_pm4_free_state(). Hence no need to call
si_pm4_clear_state() in si_pm4_free_state().

Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17504>
2022-07-14 10:30:09 +00:00
Yogesh Mohan Marimuthu 2330c71751 radeonsi: remove tabs from code
v2: fix indentation after if (Marek Olšák)

Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17504>
2022-07-14 10:30:09 +00:00
Adam Jackson 768238fdc0 glx: Fix drawable refcounting for naked Windows
driFetchDrawable is only ever called from the MakeCurrent path, which
means it has to handle the case of pre-GLX-1.3 Windows being named as
the drawable. When it finds the drawable in the hash, it increments its
refcount before returning it, so for a GLXWindow it would be 2 on first
return, one from glXCreateWindow and one from glXMakeCurrent. But when
it does not find the drawable and creates one for the naked Window, the
reference count on first return would only be 1. As a result, if this
context was then ever bound to a different drawable, the old Window's
DRI drawable state (like the back buffer) would be destroyed.

Fixes piglit's glx-multi-window-single-context and glx-make-current for
a variety of drivers.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6713
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17479>
2022-07-13 12:25:30 -04:00
Mike Blumenkrantz 21b3a23404 mesa: fix SignalSemaphoreEXT behavior
the EXT_external_object spec originally was underspecified with regards
to this function, leaving room for synchronization errors where:
* app calls SignalSemaphoreEXT to signal a semaphore
* mesa defers pipe_context::fence_server_signal with threaded context
* driver defers gpu submission
* SignalSemaphoreEXT has long since returned, app submits vk cmdbuf waiting on semaphore
* spec violation / device lost

to prevent this, the spec is being changed to:
1) require an implicit flush when calling SignalSemaphoreEXT
2) require that this implicit flush also forces GPU submission before SignalSemaphoreEXT returns

all affected drivers have been updated

fixes #6568

cc: mesa-stable

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17376>
2022-07-10 16:15:17 +00:00
Marek Olšák 3b36700162 radeonsi: fix random PS wave size
Fixes: b3b2f97f2e "radeonsi: add Wave32 heuristics and shader profiles"

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17410>
2022-07-09 21:00:51 +00:00
Pierre-Eric Pelloux-Prayer 01314d0880 radeonsi: use LLVMBuildLoad2 for inter-stage outputs loads
The PS case was covered by the previous commit, so we can use f32
everywhere.

Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17361>
2022-07-08 08:41:26 +00:00
Pierre-Eric Pelloux-Prayer 248781dea1 radeonsi: use LLVMBuildLoad2 in llvm PS
PS is the only shader type where unpacked 16-bit outputs can be used,
so use ac_shader_abi::is_16bit to pass the proper type to LLVMBuildLoad2.

Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17361>
2022-07-08 08:41:26 +00:00
Pierre-Eric Pelloux-Prayer 196c4ebe1a ac: add per output is_16bit flag to ac_shader_abi
Outputs are always f32 except for FS that may use unpacked f16.
Store this information here to make it available to later processing.

Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17361>
2022-07-08 08:41:25 +00:00
Pierre-Eric Pelloux-Prayer c275e69cee radeonsi: use LLVMBuildLoad2 where possible
This commit replaces LLVMBuildLoad usage by LLVMBuildLoad2
where possible (= where the pointee type is known).

Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17361>
2022-07-08 08:41:25 +00:00
Pierre-Eric Pelloux-Prayer 8856379a03 mesa/st: don't guess the internal format if it's known
This fixes tests using imageLoad/imageStore on texture
created using glEGLImageTargetTexture2DOES.

Before this change, the format was guessed as GL_RGBA,
which would be rejected by _mesa_get_shader_image_format.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16662>
2022-07-07 12:25:05 +00:00
David Heidelberg 6c4cc0abc6 ci: traces: switch to brotli compressed traces
virgl: Also drop old pre-trim glxgears trace (cached).

Acked-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Emma Anholt <emma@anholt.net>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17280>
2022-06-29 00:58:28 +00:00
Qiang Yu 04b15f88e7 radeonsi: replace llvm gs input handle with nir lowering
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
2022-06-27 11:32:50 +08:00
Qiang Yu f8ddee90ca radeonsi: replace llvm es output with nir lowering
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
2022-06-27 11:32:38 +08:00
Qiang Yu c66eba2072 radeonsi: set lds for gs/es to handle nir shared memory load/store
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
2022-06-27 11:32:26 +08:00
Qiang Yu 06d493dde2 radeonsi: implement two esgs ring nir intrinsic
nir_intrinsic_load_ring_esgs_amd
nir_intrinsic_load_ring_es2gs_offset_amd

Will be used by esgs lowering.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
2022-06-27 11:32:15 +08:00
Qiang Yu 7847114343 radeonsi: replace llvm tes input load with nir lowering
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu 6b6aeeecbb radeonsi: set uses_vmem_load_other for nir_intrinsic_load_buffer_amd
Before lower TES load input to load buffer, mark this flag for this
intrinsic, otherwise we get corruption with GFX10 after the lowering.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu 2b7e167bbd radeonsi: enable PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS
This can remove special handling of tessfactors which also benifit
the nir lower pass which does not handle these as system value.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu 7598bfd768 radeonsi: replace llvm tcs output with nir lower pass
Remove the store_tcs_outputs abi, we can use common output abi
to handle the tessfactor pass as vgpr.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu baaeca7d1a radeonsi: implement nir_intrinsic_load_tess_rel_patch_id_amd for both tcs and tes
radv will lower this intrinsic before gets to llvm, so we just need to
implement it in radeonsi.

The tes version will be used in tess lower too.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu 3853dfcd44 radeonsi: implement nir_intrinsic_load_ring_tess_offchip(_offset)_amd
Used by tess lower latter.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu 4ec864c057 radeonsi: preload tess offchip ring for tcs
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Sigend-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu fdf589321c ac/nir: add nir_intrinsic_load_hs_out_patch_data_offset_amd
Also add radv and radeonsi implementation. Will be used in tess lowering.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu 07e025a390 radeonsi: implement nir_intrinsic_load_tcs_num_patches_amd
Used by ac_nir_lower_tess_io_to_mem.c.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu a1763ad4b3 radeonsi: replace llvm based fixed tcs with nir
Create nir passthrough shader with explicit input/output and vertex
output count so that it can be handled by compiler same as user tcs.

The drawback is we create more si_shader_selector with different
input/output and vertex output count which was handled by compiler
backend before.

As fixed function tcs can be handled like user tcs, we don't need
the dedicated fixed_func_tcs_shader state either.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00