radeonsi/gfx11: fix alpha-to-coverage with stencil or samplemask export
We can't use UINT16_ABGR for the alpha channel. Always use 32_ABGR. Reviewed-by: Mihai Preda <mhpreda@gmail.com> Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
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@ -31,11 +31,15 @@
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#include <stdlib.h>
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#include <string.h>
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unsigned ac_get_spi_shader_z_format(bool writes_z, bool writes_stencil, bool writes_samplemask)
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unsigned ac_get_spi_shader_z_format(bool writes_z, bool writes_stencil, bool writes_samplemask,
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bool writes_mrt0_alpha)
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{
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if (writes_z) {
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/* If writes_mrt0_alpha is true, one other flag must be true too. */
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assert(!writes_mrt0_alpha || writes_z || writes_stencil || writes_samplemask);
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if (writes_z || writes_mrt0_alpha) {
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/* Z needs 32 bits. */
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if (writes_samplemask)
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if (writes_samplemask || writes_mrt0_alpha)
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return V_028710_SPI_SHADER_32_ABGR;
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else if (writes_stencil)
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return V_028710_SPI_SHADER_32_GR;
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@ -90,7 +90,8 @@ enum ac_descriptor_type
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AC_DESC_PLANE_2,
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};
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unsigned ac_get_spi_shader_z_format(bool writes_z, bool writes_stencil, bool writes_samplemask);
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unsigned ac_get_spi_shader_z_format(bool writes_z, bool writes_stencil, bool writes_samplemask,
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bool writes_mrt0_alpha);
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unsigned ac_get_cb_shader_mask(unsigned spi_shader_col_format);
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@ -4290,11 +4290,12 @@ LLVMValueRef ac_build_call(struct ac_llvm_context *ctx, LLVMValueRef func, LLVMV
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}
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void ac_export_mrt_z(struct ac_llvm_context *ctx, LLVMValueRef depth, LLVMValueRef stencil,
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LLVMValueRef samplemask, LLVMValueRef mrtz_alpha, bool is_last,
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LLVMValueRef samplemask, LLVMValueRef mrt0_alpha, bool is_last,
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struct ac_export_args *args)
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{
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unsigned mask = 0;
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unsigned format = ac_get_spi_shader_z_format(depth != NULL, stencil != NULL, samplemask != NULL);
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unsigned format = ac_get_spi_shader_z_format(depth != NULL, stencil != NULL, samplemask != NULL,
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mrt0_alpha != NULL);
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assert(depth || stencil || samplemask);
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@ -4330,17 +4331,6 @@ void ac_export_mrt_z(struct ac_llvm_context *ctx, LLVMValueRef depth, LLVMValueR
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args->out[1] = samplemask;
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mask |= ctx->gfx_level >= GFX11 ? 0x2 : 0xc;
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}
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if (mrtz_alpha) {
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/* MRT0 alpha should be in Y[31:16] if alpha-to-coverage is enabled and MRTZ is present. */
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assert(ctx->gfx_level >= GFX11);
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mrtz_alpha = LLVMBuildFPTrunc(ctx->builder, mrtz_alpha, ctx->f16, "");
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mrtz_alpha = ac_to_integer(ctx, mrtz_alpha);
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mrtz_alpha = LLVMBuildZExt(ctx->builder, mrtz_alpha, ctx->i32, "");
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mrtz_alpha = LLVMBuildShl(ctx->builder, mrtz_alpha, LLVMConstInt(ctx->i32, 16, 0), "");
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args->out[1] = LLVMBuildOr(ctx->builder, ac_to_integer(ctx, args->out[1]), mrtz_alpha, "");
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args->out[1] = ac_to_float(ctx, args->out[1]);
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mask |= 0x2;
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}
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} else {
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if (depth) {
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args->out[0] = depth;
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@ -4354,8 +4344,8 @@ void ac_export_mrt_z(struct ac_llvm_context *ctx, LLVMValueRef depth, LLVMValueR
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args->out[2] = samplemask;
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mask |= 0x4;
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}
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if (mrtz_alpha) {
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args->out[3] = mrtz_alpha;
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if (mrt0_alpha) {
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args->out[3] = mrt0_alpha;
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mask |= 0x8;
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}
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}
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@ -556,7 +556,7 @@ LLVMValueRef ac_build_atomic_cmp_xchg(struct ac_llvm_context *ctx, LLVMValueRef
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LLVMValueRef cmp, LLVMValueRef val, const char *sync_scope);
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void ac_export_mrt_z(struct ac_llvm_context *ctx, LLVMValueRef depth, LLVMValueRef stencil,
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LLVMValueRef samplemask, LLVMValueRef mrtz_alpha, bool is_last,
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LLVMValueRef samplemask, LLVMValueRef mrt0_alpha, bool is_last,
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struct ac_export_args *args);
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void ac_build_sendmsg_gs_alloc_req(struct ac_llvm_context *ctx, LLVMValueRef wave_id,
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@ -6208,7 +6208,7 @@ radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf *ctx_cs, struct rade
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radeon_set_context_reg(
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ctx_cs, R_028710_SPI_SHADER_Z_FORMAT,
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ac_get_spi_shader_z_format(ps->info.ps.writes_z, ps->info.ps.writes_stencil,
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ps->info.ps.writes_sample_mask));
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ps->info.ps.writes_sample_mask, false));
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}
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static void
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@ -1943,7 +1943,8 @@ static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader)
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shader->ctx_reg.ps.spi_baryc_cntl = spi_baryc_cntl;
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shader->ctx_reg.ps.spi_ps_in_control = spi_ps_in_control;
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shader->ctx_reg.ps.spi_shader_z_format =
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ac_get_spi_shader_z_format(info->writes_z, info->writes_stencil, info->writes_samplemask);
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ac_get_spi_shader_z_format(info->writes_z, info->writes_stencil, info->writes_samplemask,
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shader->key.ps.part.epilog.alpha_to_coverage_via_mrtz);
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shader->ctx_reg.ps.spi_shader_col_format = spi_shader_col_format;
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shader->ctx_reg.ps.cb_shader_mask = cb_shader_mask;
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