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radeonsi/gfx11: update the initialization of SGPR0/1 registers for HS and GS 

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
This commit is contained in:
Marek Olšák 2022-04-02 01:51:44 -04:00 committed by Marge Bot
parent 54d85700a1
commit c749b6f6ae
3 changed files with 21 additions and 10 deletions
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21
src/gallium/drivers/radeonsi/si_descriptors.c
View File

@ -2698,6 +2698,15 @@ void si_init_all_descriptors(struct si_context *sctx)
{
int i;
unsigned first_shader = sctx->has_graphics ? 0 : PIPE_SHADER_COMPUTE;
unsigned hs_sgpr0, gs_sgpr0;
if (sctx->chip_class >= GFX11) {
hs_sgpr0 = R_00B420_SPI_SHADER_PGM_LO_HS;
gs_sgpr0 = R_00B220_SPI_SHADER_PGM_LO_GS;
} else {
hs_sgpr0 = R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS;
gs_sgpr0 = R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS;
}
for (i = first_shader; i < SI_NUM_SHADERS; i++) {
bool is_2nd =
@ -2710,13 +2719,13 @@ void si_init_all_descriptors(struct si_context *sctx)
if (is_2nd) {
if (i == PIPE_SHADER_TESS_CTRL) {
rel_dw_offset =
(R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS - R_00B430_SPI_SHADER_USER_DATA_LS_0) / 4;
(hs_sgpr0 - R_00B430_SPI_SHADER_USER_DATA_LS_0) / 4;
} else if (sctx->chip_class >= GFX10) { /* PIPE_SHADER_GEOMETRY */
rel_dw_offset =
(R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS - R_00B230_SPI_SHADER_USER_DATA_GS_0) / 4;
(gs_sgpr0 - R_00B230_SPI_SHADER_USER_DATA_GS_0) / 4;
} else {
rel_dw_offset =
(R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS - R_00B330_SPI_SHADER_USER_DATA_ES_0) / 4;
(gs_sgpr0 - R_00B330_SPI_SHADER_USER_DATA_ES_0) / 4;
}
} else {
rel_dw_offset = SI_SGPR_CONST_AND_SHADER_BUFFERS;
@ -2730,13 +2739,13 @@ void si_init_all_descriptors(struct si_context *sctx)
if (is_2nd) {
if (i == PIPE_SHADER_TESS_CTRL) {
rel_dw_offset =
(R_00B40C_SPI_SHADER_USER_DATA_ADDR_HI_HS - R_00B430_SPI_SHADER_USER_DATA_LS_0) / 4;
(hs_sgpr0 + 4 - R_00B430_SPI_SHADER_USER_DATA_LS_0) / 4;
} else if (sctx->chip_class >= GFX10) { /* PIPE_SHADER_GEOMETRY */
rel_dw_offset =
(R_00B20C_SPI_SHADER_USER_DATA_ADDR_HI_GS - R_00B230_SPI_SHADER_USER_DATA_GS_0) / 4;
(gs_sgpr0 + 4 - R_00B230_SPI_SHADER_USER_DATA_GS_0) / 4;
} else {
rel_dw_offset =
(R_00B20C_SPI_SHADER_USER_DATA_ADDR_HI_GS - R_00B330_SPI_SHADER_USER_DATA_ES_0) / 4;
(gs_sgpr0 + 4 - R_00B330_SPI_SHADER_USER_DATA_ES_0) / 4;
}
} else {
rel_dw_offset = SI_SGPR_SAMPLERS_AND_IMAGES;

6
src/gallium/drivers/radeonsi/si_shader.c
View File

@ -465,7 +465,8 @@ void si_init_shader_args(struct si_shader_context *ctx, bool ngg_cull_shader)
case SI_SHADER_MERGED_VERTEX_TESSCTRL:
/* Merged stages have 8 system SGPRs at the beginning. */
/* SPI_SHADER_USER_DATA_ADDR_LO/HI_HS */
/* Gfx9-10: SPI_SHADER_USER_DATA_ADDR_LO/HI_HS */
/* Gfx11+: SPI_SHADER_PGM_LO/HI_HS */
declare_per_stage_desc_pointers(ctx, ctx->stage == MESA_SHADER_TESS_CTRL);
ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.tess_offchip_offset);
ac_add_arg(&ctx->args, AC_ARG_SGPR, 1, AC_ARG_INT, &ctx->args.merged_wave_info);
@ -532,7 +533,8 @@ void si_init_shader_args(struct si_shader_context *ctx, bool ngg_cull_shader)
case SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY:
/* Merged stages have 8 system SGPRs at the beginning. */
/* SPI_SHADER_USER_DATA_ADDR_LO/HI_GS */
/* Gfx9-10: SPI_SHADER_USER_DATA_ADDR_LO/HI_GS */
/* Gfx11+: SPI_SHADER_PGM_LO/HI_GS */
declare_per_stage_desc_pointers(ctx, ctx->stage == MESA_SHADER_GEOMETRY);
if (ctx->shader->key.ge.as_ngg)

4
src/gallium/drivers/radeonsi/si_shader.h
View File

@ -200,8 +200,8 @@ enum
GFX6_TCS_NUM_USER_SGPR,
/* GFX9: Merged shaders. */
/* 2ND_CONST_AND_SHADER_BUFFERS is set in USER_DATA_ADDR_LO (SGPR0). */
/* 2ND_SAMPLERS_AND_IMAGES is set in USER_DATA_ADDR_HI (SGPR1). */
/* 2ND_CONST_AND_SHADER_BUFFERS is set in USER_DATA_ADDR_LO/PGM_LO (SGPR0). */
/* 2ND_SAMPLERS_AND_IMAGES is set in USER_DATA_ADDR_HI/PGM_HI (SGPR1). */
GFX9_MERGED_NUM_USER_SGPR = SI_VS_NUM_USER_SGPR,
/* GFX9: Merged LS-HS (VS-TCS) only. */