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amd: rename fishes to Navi21, Navi22, Navi23, Navi24, and Rembrandt 

Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16604>
This commit is contained in:
Marek Olšák 2022-05-19 05:37:09 -04:00 committed by Marge Bot
parent c6bb8961a8
commit 2443054932
27 changed files with 98 additions and 98 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
src/amd/addrlib/src/amdgpu_asic_addr.h
View File

@ -46,7 +46,7 @@
#define FAMILY_VGH 0x90
#define FAMILY_GFX1100 0x91
#define FAMILY_GFX1103 0x94
#define FAMILY_YC 0x92
#define FAMILY_RMB 0x92
#define FAMILY_GC_10_3_6 0x95
#define FAMILY_GC_10_3_7 0x97
@ -62,7 +62,7 @@
#define FAMILY_IS_AI(f) FAMILY_IS(f, AI)
#define FAMILY_IS_RV(f) FAMILY_IS(f, RV)
#define FAMILY_IS_NV(f) FAMILY_IS(f, NV)
#define FAMILY_IS_YC(f) FAMILY_IS(f, YC)
#define FAMILY_IS_RMB(f) FAMILY_IS(f, RMB)
#define FAMILY_IS_GFX1100(f) FAMILY_IS(f, GFX1100)
#define FAMILY_IS_GFX1103(f) FAMILY_IS(f, GFX1103)
@ -107,10 +107,10 @@
#define AMDGPU_NAVI10_RANGE 0x01, 0x0A
#define AMDGPU_NAVI12_RANGE 0x0A, 0x14
#define AMDGPU_NAVI14_RANGE 0x14, 0x28
#define AMDGPU_SIENNA_CICHLID_RANGE 0x28, 0x32
#define AMDGPU_NAVY_FLOUNDER_RANGE 0x32, 0x3C
#define AMDGPU_DIMGREY_CAVEFISH_RANGE 0x3C, 0x46
#define AMDGPU_BEIGE_GOBY_RANGE 0x46, 0x50
#define AMDGPU_NAVI21_RANGE 0x28, 0x32
#define AMDGPU_NAVI22_RANGE 0x32, 0x3C
#define AMDGPU_NAVI23_RANGE 0x3C, 0x46
#define AMDGPU_NAVI24_RANGE 0x46, 0x50
#define AMDGPU_VANGOGH_RANGE 0x01, 0xFF
@ -120,7 +120,7 @@
#define AMDGPU_GFX1103_RANGE 0x01, 0xFF
#define AMDGPU_YELLOW_CARP_RANGE 0x01, 0xFF
#define AMDGPU_REMBRANDT_RANGE 0x01, 0xFF
#define AMDGPU_GFX1036_RANGE 0x01, 0xFF
@ -177,13 +177,13 @@
#define ASICREV_IS_NAVI14_M(r) ASICREV_IS(r, NAVI14)
#define ASICREV_IS_SIENNA_CICHLID(r) ASICREV_IS(r, SIENNA_CICHLID)
#define ASICREV_IS_NAVI21_M(r) ASICREV_IS(r, NAVI21)
#define ASICREV_IS_NAVY_FLOUNDER(r) ASICREV_IS(r, NAVY_FLOUNDER)
#define ASICREV_IS_NAVI22_P(r) ASICREV_IS(r, NAVI22)
#define ASICREV_IS_DIMGREY_CAVEFISH(r) ASICREV_IS(r, DIMGREY_CAVEFISH)
#define ASICREV_IS_NAVI23_P(r) ASICREV_IS(r, NAVI23)
#define ASICREV_IS_BEIGE_GOBY(r) ASICREV_IS(r, BEIGE_GOBY)
#define ASICREV_IS_NAVI24_P(r) ASICREV_IS(r, NAVI24)
#define ASICREV_IS_VANGOGH(r) ASICREV_IS(r, VANGOGH)
@ -192,7 +192,7 @@
#define ASICREV_IS_GFX1102(r) ASICREV_IS(r, GFX1102)
#define ASICREV_IS_GFX1103(r) ASICREV_IS(r, GFX1103)
#define ASICREV_IS_YELLOW_CARP(r) ASICREV_IS(r, YELLOW_CARP)
#define ASICREV_IS_REMBRANDT(r) ASICREV_IS(r, REMBRANDT)
#define ASICREV_IS_GFX1036(r) ASICREV_IS(r, GFX1036)

2
src/amd/addrlib/src/core/addrlib.cpp
View File

@ -227,7 +227,7 @@ ADDR_E_RETURNCODE Lib::Create(
break;
case FAMILY_NV:
case FAMILY_VGH:
case FAMILY_YC:
case FAMILY_RMB:
case FAMILY_GC_10_3_6:
case FAMILY_GC_10_3_7:
pLib = Gfx10HwlInit(&client);

12
src/amd/addrlib/src/gfx10/gfx10addrlib.cpp
View File

@ -1035,25 +1035,25 @@ ChipFamily Gfx10Lib::HwlConvertChipFamily(
m_settings.isDcn20 = 1;
}
if (ASICREV_IS_SIENNA_CICHLID(chipRevision))
if (ASICREV_IS_NAVI21_M(chipRevision))
{
m_settings.supportRbPlus = 1;
m_settings.dccUnsup3DSwDis = 0;
}
if (ASICREV_IS_NAVY_FLOUNDER(chipRevision))
if (ASICREV_IS_NAVI22_P(chipRevision))
{
m_settings.supportRbPlus = 1;
m_settings.dccUnsup3DSwDis = 0;
}
if (ASICREV_IS_DIMGREY_CAVEFISH(chipRevision))
if (ASICREV_IS_NAVI23_P(chipRevision))
{
m_settings.supportRbPlus = 1;
m_settings.dccUnsup3DSwDis = 0;
}
if (ASICREV_IS_BEIGE_GOBY(chipRevision))
if (ASICREV_IS_NAVI24_P(chipRevision))
{
m_settings.supportRbPlus = 1;
m_settings.dccUnsup3DSwDis = 0;
@ -1072,8 +1072,8 @@ ChipFamily Gfx10Lib::HwlConvertChipFamily(
}
break;
case FAMILY_YC:
if (ASICREV_IS_YELLOW_CARP(chipRevision))
case FAMILY_RMB:
if (ASICREV_IS_REMBRANDT(chipRevision))
{
m_settings.supportRbPlus = 1;
m_settings.dccUnsup3DSwDis = 0;

6
src/amd/ci/gitlab-ci.yml
View File

@ -147,7 +147,7 @@ deqp-navi21-valve:
extends:
- .deqp-test-valve
variables:
GPU_VERSION: radv-sienna_cichlid-aco
GPU_VERSION: radv-navi21-aco
FDO_CI_CONCURRENT: 16
B2C_KERNEL_CMDLINE_EXTRAS: 'b2c.swap=16g'
tags:
@ -188,6 +188,6 @@ radv-fossils:
# Navi10 (GFX10)
- export RADV_FORCE_FAMILY="NAVI10"
- ./install/fossilize-runner.sh
# Sienna Cichlid (GFX10)
- export RADV_FORCE_FAMILY="SIENNA_CICHLID"
# Navi21 (GFX10_3)
- export RADV_FORCE_FAMILY="NAVI21"
- ./install/fossilize-runner.sh

0
src/amd/ci/radv-sienna_cichlid-aco-fails.txt → src/amd/ci/radv-navi21-aco-fails.txt
View File

0
src/amd/ci/radv-sienna_cichlid-aco-flakes.txt → src/amd/ci/radv-navi21-aco-flakes.txt
View File

2
src/amd/ci/radv-skips.txt
View File

@ -12,5 +12,5 @@ dEQP-VK.memory.pipeline_barrier.transfer_src_transfer_dst.1048576
dEQP-VK.api.driver_properties.conformance_version
# Exclude these tests because they randomly hang on Navi10 and randomly fail on
# Sienna Cichlid.
# Navi21
dEQP-VK.renderpass2.depth_stencil_resolve.*_samplemask

40
src/amd/common/ac_gpu_info.c
View File

@ -722,16 +722,16 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
identify_chip(NAVI10);
identify_chip(NAVI12);
identify_chip(NAVI14);
identify_chip(SIENNA_CICHLID);
identify_chip(NAVY_FLOUNDER);
identify_chip(DIMGREY_CAVEFISH);
identify_chip(BEIGE_GOBY);
identify_chip(NAVI21);
identify_chip(NAVI22);
identify_chip(NAVI23);
identify_chip(NAVI24);
break;
case FAMILY_VGH:
identify_chip(VANGOGH);
break;
case FAMILY_YC:
identify_chip(YELLOW_CARP);
case FAMILY_RMB:
identify_chip(REMBRANDT);
break;
case FAMILY_GC_10_3_6:
identify_chip(GFX1036);
@ -761,7 +761,7 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
if (info->family >= CHIP_GFX1100)
info->gfx_level = GFX11;
else if (info->family >= CHIP_SIENNA_CICHLID)
else if (info->family >= CHIP_NAVI21)
info->gfx_level = GFX10_3;
else if (info->family >= CHIP_NAVI10)
info->gfx_level = GFX10;
@ -915,7 +915,7 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
default:
info->l2_cache_size = info->num_tcc_blocks * 256 * 1024;
break;
case CHIP_YELLOW_CARP:
case CHIP_REMBRANDT:
info->l2_cache_size = info->num_tcc_blocks * 512 * 1024;
break;
}
@ -1013,18 +1013,18 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
/* Whether chips are affected by the image load/sample/gather hw bug when
* DCC is enabled (ie. WRITE_COMPRESS_ENABLE should be 0).
*/
info->has_image_load_dcc_bug = info->family == CHIP_DIMGREY_CAVEFISH ||
info->has_image_load_dcc_bug = info->family == CHIP_NAVI23 ||
info->family == CHIP_VANGOGH ||
info->family == CHIP_YELLOW_CARP;
info->family == CHIP_REMBRANDT;
/* DB has a bug when ITERATE_256 is set to 1 that can cause a hang. The
* workaround is to set DECOMPRESS_ON_Z_PLANES to 2 for 4X MSAA D/S images.
*/
info->has_two_planes_iterate256_bug = info->gfx_level == GFX10;
/* GFX10+Sienna: NGG->legacy transitions require VGT_FLUSH. */
/* GFX10+Navi21: NGG->legacy transitions require VGT_FLUSH. */
info->has_vgt_flush_ngg_legacy_bug = info->gfx_level == GFX10 ||
info->family == CHIP_SIENNA_CICHLID;
info->family == CHIP_NAVI21;
/* HW bug workaround when CS threadgroups > 256 threads and async compute
* isn't used, i.e. only one compute job can run at a time. If async
@ -1145,17 +1145,17 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
case CHIP_RENOIR:
case CHIP_NAVI10:
case CHIP_NAVI12:
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
case CHIP_DIMGREY_CAVEFISH:
case CHIP_NAVI21:
case CHIP_NAVI22:
case CHIP_NAVI23:
pc_lines = 1024;
break;
case CHIP_NAVI14:
case CHIP_BEIGE_GOBY:
case CHIP_NAVI24:
pc_lines = 512;
break;
case CHIP_VANGOGH:
case CHIP_YELLOW_CARP:
case CHIP_REMBRANDT:
case CHIP_GFX1036:
pc_lines = 256;
break;
@ -1199,9 +1199,9 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
info->never_stop_sq_perf_counters = info->gfx_level == GFX10 ||
info->gfx_level == GFX10_3;
info->never_send_perfcounter_stop = info->gfx_level == GFX11;
info->has_sqtt_rb_harvest_bug = (info->family == CHIP_DIMGREY_CAVEFISH ||
info->family == CHIP_BEIGE_GOBY ||
info->family == CHIP_YELLOW_CARP ||
info->has_sqtt_rb_harvest_bug = (info->family == CHIP_NAVI23 ||
info->family == CHIP_NAVI24 ||
info->family == CHIP_REMBRANDT ||
info->family == CHIP_VANGOGH) &&
util_bitcount(info->enabled_rb_mask) !=
info->max_render_backends;

4
src/amd/common/ac_surface.c
View File

@ -2276,12 +2276,12 @@ static int gfx9_compute_surface(struct ac_addrlib *addrlib, const struct radeon_
surf->u.gfx9.color.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
}
if ((info->gfx_level >= GFX10_3 && info->family <= CHIP_YELLOW_CARP) ||
if ((info->gfx_level >= GFX10_3 && info->family <= CHIP_REMBRANDT) ||
/* Newer chips will skip this when possible to get better performance.
* This is also possible for other gfx10.3 chips, but is disabled for
* interoperability between different Mesa versions.
*/
(info->family > CHIP_YELLOW_CARP &&
(info->family > CHIP_REMBRANDT &&
gfx10_DCN_requires_independent_64B_blocks(info, config))) {
surf->u.gfx9.color.dcc.independent_64B_blocks = 1;
surf->u.gfx9.color.dcc.independent_128B_blocks = 1;

2
src/amd/common/ac_surface_test_common.h
View File

@ -123,7 +123,7 @@ static void init_navi14(struct radeon_info *info)
static void init_gfx103(struct radeon_info *info)
{
info->family = CHIP_SIENNA_CICHLID; /* This doesn't affect tests. */
info->family = CHIP_NAVI21; /* This doesn't affect tests. */
info->gfx_level = GFX10_3;
info->family_id = AMDGPU_FAMILY_NV;
info->chip_external_rev = 0x28;

20
src/amd/common/amd_family.c
View File

@ -88,18 +88,18 @@ const char *ac_get_family_name(enum radeon_family family)
return "NAVI12";
case CHIP_NAVI14:
return "NAVI14";
case CHIP_SIENNA_CICHLID:
return "SIENNA_CICHLID";
case CHIP_NAVY_FLOUNDER:
return "NAVY_FLOUNDER";
case CHIP_DIMGREY_CAVEFISH:
return "DIMGREY_CAVEFISH";
case CHIP_NAVI21:
return "NAVI21";
case CHIP_NAVI22:
return "NAVI22";
case CHIP_NAVI23:
return "NAVI23";
case CHIP_VANGOGH:
return "VANGOGH";
case CHIP_BEIGE_GOBY:
return "BEIGE_GOBY";
case CHIP_YELLOW_CARP:
return "YELLOW_CARP";
case CHIP_NAVI24:
return "NAVI24";
case CHIP_REMBRANDT:
return "REMBRANDT";
case CHIP_GFX1036:
return "GFX1036";
case CHIP_GFX1100:

10
src/amd/common/amd_family.h
View File

@ -121,12 +121,12 @@ enum radeon_family
CHIP_NAVI12, /* Radeon Pro 5600M */
CHIP_NAVI14, /* Radeon 5300, 5500 */
/* GFX10.3 (RDNA 2) */
CHIP_SIENNA_CICHLID, /* Radeon 6800, 6900 */
CHIP_NAVY_FLOUNDER, /* Radeon 6700 */
CHIP_NAVI21, /* Radeon 6800, 6900 (formerly "Sienna Cichlid") */
CHIP_NAVI22, /* Radeon 6700 (formerly "Navy Flounder") */
CHIP_VANGOGH, /* Steam Deck */
CHIP_DIMGREY_CAVEFISH, /* Radeon 6600 */
CHIP_BEIGE_GOBY, /* Radeon 6400, 6500 */
CHIP_YELLOW_CARP, /* Ryzen 6000 */
CHIP_NAVI23, /* Radeon 6600 (formerly "Dimgrey Cavefish") */
CHIP_NAVI24, /* Radeon 6400, 6500 (formerly "Beige Goby") */
CHIP_REMBRANDT, /* Ryzen 6000 (formerly "Yellow Carp") */
CHIP_GFX1036,
CHIP_GFX1100,
CHIP_GFX1101,

2
src/amd/compiler/tests/helpers.cpp
View File

@ -370,7 +370,7 @@ VkDevice get_vk_device(enum amd_gfx_level gfx_level)
family = CHIP_NAVI10;
break;
case GFX10_3:
family = CHIP_SIENNA_CICHLID;
family = CHIP_NAVI21;
break;
case GFX11:
family = CHIP_GFX1100;

10
src/amd/llvm/ac_llvm_util.c
View File

@ -161,17 +161,17 @@ const char *ac_get_llvm_processor_name(enum radeon_family family)
return "gfx1011";
case CHIP_NAVI14:
return "gfx1012";
case CHIP_SIENNA_CICHLID:
case CHIP_NAVI21:
return "gfx1030";
case CHIP_NAVY_FLOUNDER:
case CHIP_NAVI22:
return LLVM_VERSION_MAJOR >= 12 ? "gfx1031" : "gfx1030";
case CHIP_DIMGREY_CAVEFISH:
case CHIP_NAVI23:
return LLVM_VERSION_MAJOR >= 12 ? "gfx1032" : "gfx1030";
case CHIP_VANGOGH:
return LLVM_VERSION_MAJOR >= 12 ? "gfx1033" : "gfx1030";
case CHIP_BEIGE_GOBY:
case CHIP_NAVI24:
return LLVM_VERSION_MAJOR >= 13 ? "gfx1034" : "gfx1030";
case CHIP_YELLOW_CARP:
case CHIP_REMBRANDT:
return LLVM_VERSION_MAJOR >= 13 ? "gfx1035" : "gfx1030";
case CHIP_GFX1036: /* TODO: LLVM 15 doesn't support this yet */
return "gfx1030";

2
src/amd/vulkan/radv_cmd_buffer.c
View File

@ -5207,7 +5207,7 @@ radv_CmdBindPipeline(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipeline
cmd_buffer->state.emitted_pipeline->graphics.is_ngg &&
!cmd_buffer->state.pipeline->graphics.is_ngg) {
/* Transitioning from NGG to legacy GS requires
* VGT_FLUSH on GFX10 and Sienna Cichlid. VGT_FLUSH
* VGT_FLUSH on GFX10 and Navi21. VGT_FLUSH
* is also emitted at the beginning of IBs when legacy
* GS ring pointers are set.
*/

10
src/amd/vulkan/radv_device.c
View File

@ -3353,13 +3353,13 @@ radv_CreateDevice(VkPhysicalDevice physicalDevice, const VkDeviceCreateInfo *pCr
*/
switch (device->physical_device->rad_info.family) {
case CHIP_VANGOGH:
case CHIP_BEIGE_GOBY:
case CHIP_YELLOW_CARP:
case CHIP_NAVI24:
case CHIP_REMBRANDT:
device->task_num_entries = 256;
break;
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
case CHIP_DIMGREY_CAVEFISH:
case CHIP_NAVI21:
case CHIP_NAVI22:
case CHIP_NAVI23:
default:
device->task_num_entries = 1024;
break;

4
src/amd/vulkan/radv_pipeline.c
View File

@ -3200,8 +3200,8 @@ radv_generate_graphics_pipeline_key(const struct radv_pipeline *pipeline,
key.use_ngg = pipeline->device->physical_device->use_ngg;
if ((radv_is_vrs_enabled(pipeline, pCreateInfo) || device->force_vrs_enabled) &&
(device->physical_device->rad_info.family == CHIP_SIENNA_CICHLID ||
device->physical_device->rad_info.family == CHIP_NAVY_FLOUNDER ||
(device->physical_device->rad_info.family == CHIP_NAVI21 ||
device->physical_device->rad_info.family == CHIP_NAVI22 ||
device->physical_device->rad_info.family == CHIP_VANGOGH))
key.adjust_frag_coord_z = true;

2
src/amd/vulkan/radv_shader.c
View File

@ -1090,7 +1090,7 @@ radv_consider_culling(struct radv_device *device, struct nir_shader *nir, uint64
unsigned max_se = device->physical_device->rad_info.max_se;
if (max_render_backends / max_se == 4)
max_ps_params = 6; /* Sienna Cichlid and other GFX10.3 dGPUs. */
max_ps_params = 6; /* Navi21 and other GFX10.3 dGPUs. */
else
max_ps_params = 4; /* Navi 1x. */

10
src/amd/vulkan/winsys/null/radv_null_winsys.c
View File

@ -64,10 +64,10 @@ static const struct {
[CHIP_NAVI10] = {0x7310, 16, true},
[CHIP_NAVI12] = {0x7360, 8, true},
[CHIP_NAVI14] = {0x7340, 8, true},
[CHIP_SIENNA_CICHLID] = {0x73A0, 16, true},
[CHIP_NAVI21] = {0x73A0, 16, true},
[CHIP_VANGOGH] = {0x163F, 8, false},
[CHIP_NAVY_FLOUNDER] = {0x73C0, 8, true},
[CHIP_DIMGREY_CAVEFISH] = {0x73E0, 8, true},
[CHIP_NAVI22] = {0x73C0, 8, true},
[CHIP_NAVI23] = {0x73E0, 8, true},
[CHIP_GFX1100] = {0xdead, 8, true}, /* TODO: fill with real info. */
};
@ -88,7 +88,7 @@ radv_null_winsys_query_info(struct radeon_winsys *rws, struct radeon_info *info)
if (info->family >= CHIP_GFX1100)
info->gfx_level = GFX11;
else if (i >= CHIP_SIENNA_CICHLID)
else if (i >= CHIP_NAVI21)
info->gfx_level = GFX10_3;
else if (i >= CHIP_NAVI10)
info->gfx_level = GFX10;
@ -139,7 +139,7 @@ radv_null_winsys_query_info(struct radeon_winsys *rws, struct radeon_info *info)
info->has_packed_math_16bit = info->gfx_level >= GFX9;
info->has_image_load_dcc_bug =
info->family == CHIP_DIMGREY_CAVEFISH || info->family == CHIP_VANGOGH;
info->family == CHIP_NAVI23 || info->family == CHIP_VANGOGH;
info->has_accelerated_dot_product =
info->family == CHIP_ARCTURUS || info->family == CHIP_ALDEBARAN ||

0
src/gallium/drivers/radeonsi/ci/gfx10_3-sienna_cichlid-fail.csv → src/gallium/drivers/radeonsi/ci/gfx10_3-navi21-fail.csv
View File

2
src/gallium/drivers/radeonsi/gfx10_shader_ngg.c
View File

@ -137,7 +137,7 @@ void gfx10_ngg_build_sendmsg_gs_alloc_req(struct si_shader_context *ctx)
{
/* Newer chips can use PRIMGEN_PASSTHRU_NO_MSG to skip gs_alloc_req for NGG passthrough. */
if (gfx10_is_ngg_passthrough(ctx->shader) &&
ctx->screen->info.family >= CHIP_DIMGREY_CAVEFISH)
ctx->screen->info.family >= CHIP_NAVI23)
return;
ac_build_sendmsg_gs_alloc_req(&ctx->ac, get_wave_id_in_tg(ctx), ngg_get_vtx_cnt(ctx),

16
src/gallium/drivers/radeonsi/radeon_vcn_dec.c
View File

@ -1914,7 +1914,7 @@ static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec,
decode->sw_ctxt_size = RDECODE_SESSION_CONTEXT_SIZE;
decode->db_pitch = align(dec->base.width, dec->db_alignment);
if (((struct si_screen*)dec->screen)->info.family >= CHIP_SIENNA_CICHLID &&
if (((struct si_screen*)dec->screen)->info.family >= CHIP_NAVI21 &&
(dec->stream_type == RDECODE_CODEC_VP9 || dec->stream_type == RDECODE_CODEC_AV1 ||
dec->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10))
decode->db_aligned_height = align(dec->base.height, 64);
@ -2807,7 +2807,7 @@ struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
for (i = 0; i < ARRAY_SIZE(dec->render_pic_list); i++)
dec->render_pic_list[i] = NULL;
if (sctx->family >= CHIP_SIENNA_CICHLID && (stream_type == RDECODE_CODEC_H264_PERF)) {
if (sctx->family >= CHIP_NAVI21 && (stream_type == RDECODE_CODEC_H264_PERF)) {
for (i = 0; i < ARRAY_SIZE(dec->h264_valid_ref_num); i++)
dec->h264_valid_ref_num[i] = (unsigned) -1;
for (i = 0; i < ARRAY_SIZE(dec->h264_valid_poc_num); i++)
@ -2853,7 +2853,7 @@ struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
}
}
if (sctx->family >= CHIP_SIENNA_CICHLID &&
if (sctx->family >= CHIP_NAVI21 &&
(stream_type == RDECODE_CODEC_VP9 ||
stream_type == RDECODE_CODEC_AV1 ||
((stream_type == RDECODE_CODEC_H265) && templ->expect_chunked_decode) ||
@ -2902,12 +2902,12 @@ struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
break;
case CHIP_ARCTURUS:
case CHIP_ALDEBARAN:
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
case CHIP_DIMGREY_CAVEFISH:
case CHIP_BEIGE_GOBY:
case CHIP_NAVI21:
case CHIP_NAVI22:
case CHIP_NAVI23:
case CHIP_NAVI24:
case CHIP_VANGOGH:
case CHIP_YELLOW_CARP:
case CHIP_REMBRANDT:
case CHIP_GFX1036:
dec->reg.data0 = RDECODE_VCN2_5_GPCOM_VCPU_DATA0;
dec->reg.data1 = RDECODE_VCN2_5_GPCOM_VCPU_DATA1;

2
src/gallium/drivers/radeonsi/radeon_vcn_enc.c
View File

@ -591,7 +591,7 @@ struct pipe_video_codec *radeon_create_encoder(struct pipe_context *context,
if (sscreen->info.gfx_level >= GFX11)
radeon_enc_4_0_init(enc);
else if (sscreen->info.family >= CHIP_SIENNA_CICHLID)
else if (sscreen->info.family >= CHIP_NAVI21)
radeon_enc_3_0_init(enc);
else if (sscreen->info.family >= CHIP_RENOIR)
radeon_enc_2_0_init(enc);

6
src/gallium/drivers/radeonsi/si_get.c
View File

@ -593,7 +593,7 @@ static int si_get_video_param(struct pipe_screen *screen, enum pipe_video_profil
return 0;
case PIPE_VIDEO_CAP_EFC_SUPPORTED:
return ((sscreen->info.family >= CHIP_RENOIR) &&
(sscreen->info.family < CHIP_SIENNA_CICHLID) &&
(sscreen->info.family < CHIP_NAVI21) &&
!(sscreen->debug_flags & DBG(NO_EFC)));
default:
return 0;
@ -603,7 +603,7 @@ static int si_get_video_param(struct pipe_screen *screen, enum pipe_video_profil
switch (param) {
case PIPE_VIDEO_CAP_SUPPORTED:
if (codec < PIPE_VIDEO_FORMAT_MPEG4_AVC &&
sscreen->info.family >= CHIP_BEIGE_GOBY)
sscreen->info.family >= CHIP_NAVI24)
return false;
if (codec != PIPE_VIDEO_FORMAT_JPEG &&
!(sscreen->info.has_video_hw.uvd_decode ||
@ -660,7 +660,7 @@ static int si_get_video_param(struct pipe_screen *screen, enum pipe_video_profil
return false;
return true;
case PIPE_VIDEO_FORMAT_AV1:
if (sscreen->info.family < CHIP_SIENNA_CICHLID)
if (sscreen->info.family < CHIP_NAVI21)
return false;
return true;
default:

4
src/gallium/drivers/radeonsi/si_state_shaders.cpp
View File

@ -1171,7 +1171,7 @@ bool gfx10_is_ngg_passthrough(struct si_shader *shader)
* - user GS is turned off (no amplification, no GS instancing, and no culling)
* - VGT_ESGS_RING_ITEMSIZE is ignored (behaving as if it was equal to 1)
* - vertex indices are packed into 1 VGPR
* - Dimgrey and later chips can optionally skip the gs_alloc_req message
* - Navi23 and later chips can optionally skip the gs_alloc_req message
*
* NGG passthrough still allows the use of LDS.
*/
@ -4158,7 +4158,7 @@ struct si_pm4_state *si_build_vgt_shader_config(struct si_screen *screen, union
S_028B54_NGG_WAVE_ID_EN(key.u.streamout) |
S_028B54_PRIMGEN_PASSTHRU_EN(key.u.ngg_passthrough) |
S_028B54_PRIMGEN_PASSTHRU_NO_MSG(key.u.ngg_passthrough &&
screen->info.family >= CHIP_DIMGREY_CAVEFISH);
screen->info.family >= CHIP_NAVI23);
} else if (key.u.gs)
stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);

2
src/gallium/drivers/zink/ci/zink-radv-skips.txt
View File

@ -9,7 +9,7 @@ spec@arb_shader_image_load_store.max-size
spec@arb_gpu_shader_fp64@execution@glsl-fs-loop-unroll-mul-fp64
.*@execution@vs_in.*
# Only hangs on Navi10 if run in parallel (no hangs so far on Sienna).
# Only hangs on Navi10 if run in parallel (no hangs so far on Navi21).
dEQP-GLES31.functional.geometry_shading.*
# Kopper regression

2
src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
View File

@ -67,7 +67,7 @@ static void handle_env_var_force_family(struct amdgpu_winsys *ws)
if (i >= CHIP_GFX1100)
ws->info.gfx_level = GFX11;
else if (i >= CHIP_SIENNA_CICHLID)
else if (i >= CHIP_NAVI21)
ws->info.gfx_level = GFX10_3;
else if (i >= CHIP_NAVI10)
ws->info.gfx_level = GFX10;