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gallium: remove PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT CAP 

This is used for the old, buggy and slow GLSL IR loop unrolling
code. All drivers have now switched to the NIR unrolling code so
here we remove the CAP.

Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16366>
This commit is contained in:
Timothy Arceri 2022-05-06 12:13:44 +10:00 committed by Marge Bot
parent 8c79616984
commit 26ff49038c
24 changed files with 0 additions and 42 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
docs/gallium/screen.rst
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@ -735,10 +735,6 @@ MOV OUT[0], CONST[0][3] # copy vector 3 of constbuf 0
* ``PIPE_SHADER_CAP_LDEXP_SUPPORTED``: Whether LDEXP is supported.
* ``PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE``: Whether the driver doesn't
ignore tgsi_declaration_range::Last for shader inputs and outputs.
* ``PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT``: This is the maximum number
of iterations that loops are allowed to have to be unrolled. It is only
a hint to gallium frontends. Whether any loops will be unrolled is not
guaranteed.
* ``PIPE_SHADER_CAP_MAX_SHADER_BUFFERS``: Maximum number of memory buffers
(also used to implement atomic counters). Having this be non-0 also
implies support for the ``LOAD``, ``STORE``, and ``ATOM*`` TGSI

1
src/gallium/auxiliary/gallivm/lp_bld_limits.h
View File

@ -157,7 +157,6 @@ gallivm_get_shader_param(enum pipe_shader_cap param)
case PIPE_SHADER_CAP_LDEXP_SUPPORTED:
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
return 0;
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
return LP_MAX_TGSI_SHADER_BUFFERS;

1
src/gallium/auxiliary/tgsi/tgsi_exec.h
View File

@ -469,7 +469,6 @@ tgsi_exec_get_shader_param(enum pipe_shader_cap param)
case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
case PIPE_SHADER_CAP_INT16:
case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
return 0;
case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
return PIPE_MAX_SAMPLERS;

1
src/gallium/drivers/asahi/agx_pipe.c
View File

@ -981,7 +981,6 @@ agx_get_shader_param(struct pipe_screen* pscreen,
case PIPE_SHADER_CAP_SUPPORTED_IRS:
return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_NIR_SERIALIZED);
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:

1
src/gallium/drivers/crocus/crocus_screen.c
View File

@ -526,7 +526,6 @@ crocus_get_shader_param(struct pipe_screen *pscreen,
case PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
case PIPE_SHADER_CAP_FP16_DERIVATIVES:
case PIPE_SHADER_CAP_INT16:
case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:

1
src/gallium/drivers/d3d12/d3d12_screen.cpp
View File

@ -483,7 +483,6 @@ d3d12_get_shader_param(struct pipe_screen *pscreen,
screen->opts.ResourceBindingTier >= D3D12_RESOURCE_BINDING_TIER_3) ?
PIPE_MAX_SHADER_IMAGES : D3D12_PS_CS_UAV_REGISTER_COUNT;
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
case PIPE_SHADER_CAP_LDEXP_SUPPORTED:
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:

1
src/gallium/drivers/etnaviv/etnaviv_screen.c
View File

@ -414,7 +414,6 @@ etna_screen_get_shader_param(struct pipe_screen *pscreen,
case PIPE_SHADER_CAP_SUPPORTED_IRS:
return (1 << PIPE_SHADER_IR_TGSI) |
(1 << PIPE_SHADER_IR_NIR);
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:

1
src/gallium/drivers/freedreno/freedreno_screen.c
View File

@ -649,7 +649,6 @@ fd_screen_get_shader_param(struct pipe_screen *pscreen,
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
return 0;
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
return 1;

1
src/gallium/drivers/i915/i915_screen.c
View File

@ -370,7 +370,6 @@ i915_get_shader_param(struct pipe_screen *screen, enum pipe_shader_type shader,
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
return 0;
default:

1
src/gallium/drivers/iris/iris_screen.c
View File

@ -524,7 +524,6 @@ iris_get_shader_param(struct pipe_screen *pscreen,
case PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
return 0;
default:
unreachable("unknown shader param");

4
src/gallium/drivers/lima/lima_screen.c
View File

@ -238,9 +238,6 @@ get_vertex_shader_param(struct lima_screen *screen,
case PIPE_SHADER_CAP_MAX_TEMPS:
return 256; /* need investigate */
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
return 0;
default:
return 0;
}
@ -289,7 +286,6 @@ get_fragment_shader_param(struct lima_screen *screen,
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
return 0;
default:

2
src/gallium/drivers/nouveau/nv30/nv30_screen.c
View File

@ -347,7 +347,6 @@ nv30_screen_get_shader_param(struct pipe_screen *pscreen,
return (eng3d->oclass >= NV40_3D_CLASS) ? 32 : 13;
case PIPE_SHADER_CAP_PREFERRED_IR:
return (NOUVEAU_DEBUG & NOUVEAU_DEBUG_USE_TGSI) ? PIPE_SHADER_IR_TGSI : PIPE_SHADER_IR_NIR;
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
return 0;
@ -405,7 +404,6 @@ nv30_screen_get_shader_param(struct pipe_screen *pscreen,
return 16;
case PIPE_SHADER_CAP_PREFERRED_IR:
return (NOUVEAU_DEBUG & NOUVEAU_DEBUG_USE_TGSI) ? PIPE_SHADER_IR_TGSI : PIPE_SHADER_IR_NIR;
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
case PIPE_SHADER_CAP_CONT_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:

1
src/gallium/drivers/nouveau/nv50/nv50_screen.c
View File

@ -517,7 +517,6 @@ nv50_screen_get_shader_param(struct pipe_screen *pscreen,
return screen->prefer_nir ? PIPE_SHADER_IR_NIR : PIPE_SHADER_IR_TGSI;
case PIPE_SHADER_CAP_SUPPORTED_IRS:
return (1 << PIPE_SHADER_IR_TGSI) | (1 << PIPE_SHADER_IR_NIR);
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
case PIPE_SHADER_CAP_DROUND_SUPPORTED:
case PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED:
case PIPE_SHADER_CAP_LDEXP_SUPPORTED:

1
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
View File

@ -552,7 +552,6 @@ nvc0_screen_get_shader_param(struct pipe_screen *pscreen,
case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
return 0;
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
return NVC0_MAX_BUFFERS;

1
src/gallium/drivers/panfrost/pan_screen.c
View File

@ -457,7 +457,6 @@ panfrost_get_shader_param(struct pipe_screen *screen,
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
return allow_side_effects ? PIPE_MAX_SHADER_IMAGES : 0;
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
return 0;

2
src/gallium/drivers/r300/r300_screen.c
View File

@ -316,7 +316,6 @@ static int r300_get_shader_param(struct pipe_screen *pscreen,
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
return 0;
default:
break;
@ -408,7 +407,6 @@ static int r300_get_shader_param(struct pipe_screen *pscreen,
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
return 0;
default:
break;

1
src/gallium/drivers/r600/r600_pipe.c
View File

@ -642,7 +642,6 @@ static int r600_get_shader_param(struct pipe_screen* pscreen,
}
return ir;
}
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
case PIPE_SHADER_CAP_DROUND_SUPPORTED:
case PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED:
case PIPE_SHADER_CAP_LDEXP_SUPPORTED:

2
src/gallium/drivers/radeonsi/si_get.c
View File

@ -441,8 +441,6 @@ static int si_get_shader_param(struct pipe_screen *pscreen, enum pipe_shader_typ
return SI_NUM_SHADER_BUFFERS;
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
return SI_NUM_IMAGES;
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
return 0;
case PIPE_SHADER_CAP_PREFERRED_IR:
return PIPE_SHADER_IR_NIR;

3
src/gallium/drivers/svga/svga_screen.c
View File

@ -554,7 +554,6 @@ vgpu9_get_shader_param(struct pipe_screen *screen,
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
return 0;
}
/* If we get here, we failed to handle a cap above */
@ -621,7 +620,6 @@ vgpu9_get_shader_param(struct pipe_screen *screen,
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
return 0;
}
/* If we get here, we failed to handle a cap above */
@ -743,7 +741,6 @@ vgpu10_get_shader_param(struct pipe_screen *screen,
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
return sws->have_gl43 ? SVGA_MAX_ATOMIC_BUFFERS : 0;
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
case PIPE_SHADER_CAP_INT64_ATOMICS:
return 0;

3
src/gallium/drivers/v3d/v3d_screen.c
View File

@ -466,9 +466,6 @@ v3d_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
return PIPE_SHADER_IR_NIR;
case PIPE_SHADER_CAP_SUPPORTED_IRS:
return 1 << PIPE_SHADER_IR_NIR;
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
/* We use NIR's loop unrolling */
return 0;
default:
fprintf(stderr, "unknown shader param %d\n", param);
return 0;

1
src/gallium/drivers/vc4/vc4_screen.c
View File

@ -311,7 +311,6 @@ vc4_screen_get_shader_param(struct pipe_screen *pscreen,
return PIPE_SHADER_IR_NIR;
case PIPE_SHADER_CAP_SUPPORTED_IRS:
return 1 << PIPE_SHADER_IR_NIR;
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:

3
src/gallium/drivers/zink/zink_screen.c
View File

@ -1012,9 +1012,6 @@ zink_get_shader_param(struct pipe_screen *pscreen,
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
return 0; /* no idea */
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
return 0;
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
switch (shader) {
case PIPE_SHADER_VERTEX:

1
src/gallium/include/pipe/p_defines.h
View File

@ -1101,7 +1101,6 @@ enum pipe_shader_cap
PIPE_SHADER_CAP_DROUND_SUPPORTED, /* all rounding modes */
PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED,
PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE,
PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT,
PIPE_SHADER_CAP_MAX_SHADER_BUFFERS,
PIPE_SHADER_CAP_SUPPORTED_IRS,
PIPE_SHADER_CAP_MAX_SHADER_IMAGES,

4
src/mesa/state_tracker/st_extensions.c
View File

@ -351,10 +351,6 @@ void st_init_limits(struct pipe_screen *screen,
can_ubo = false;
}
options->MaxUnrollIterations =
screen->get_shader_param(screen, sh,
PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT);
if (!screen->get_param(screen, PIPE_CAP_NIR_COMPACT_ARRAYS))
options->LowerCombinedClipCullDistance = true;