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radv: use flush vgt streamout like PAL does. 

This uses WRITE_DATA on the ME engine to reset the register, to match what
PAL does on GFX9+.

This fixes
KHR-GL45.transform_feedback_overflow_query_ARB.multiple-streams-one-buffer-per-stream
on zink/radv.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15812>
This commit is contained in:
Dave Airlie 2022-04-08 11:45:11 +10:00 committed by Marge Bot
parent 1407a4db69
commit 165b016bbe
1 changed files with 8 additions and 1 deletions
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9
src/amd/vulkan/radv_cmd_buffer.c
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@ -8779,7 +8779,14 @@ radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
unsigned reg_strmout_cntl;
/* The register is at different places on different ASICs. */
if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
radeon_emit(cs, S_370_DST_SEL(V_370_MEM_MAPPED_REGISTER) | S_370_ENGINE_SEL(V_370_ME));
radeon_emit(cs, R_0300FC_CP_STRMOUT_CNTL >> 2);
radeon_emit(cs, 0);
radeon_emit(cs, 0);
} else if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
} else {