radeonsi/gfx11: use PIXEL_PIPE_STATE_DUMP event instead of ZPASS_DONE

Use PIXEL_PIPE_STATE_CONTROL/DUMP event instead of ZPASS_DONE for gfx11.

Signed-off-by: Yogesh Mohanmarimuthu <yogesh.mohanmarimuthu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
This commit is contained in:
Yogesh Mohanmarimuthu 2021-10-06 00:44:42 +05:30 committed by Marge Bot
parent 2a1c22e0cd
commit 6e537680c4
2 changed files with 28 additions and 2 deletions

View File

@ -66,6 +66,15 @@
* 4 - *S_PARTIAL_FLUSH
* 5 - TS events
*/
#define PIXEL_PIPE_STATE_CNTL_COUNTER_ID(x) ((x) << 3)
#define PIXEL_PIPE_STATE_CNTL_STRIDE(x) ((x) << 9)
/* 0 - 32 bits
* 1 - 64 bits
* 2 - 128 bits
* 3 - 256 bits
*/
#define PIXEL_PIPE_STATE_CNTL_INSTANCE_EN_LO(x) ((x) << 11)
#define PIXEL_PIPE_STATE_CNTL_INSTANCE_EN_HI(x) ((x) >> 21)
/* EVENT_WRITE_EOP (SI-VI) & RELEASE_MEM (GFX9) */
#define EVENT_TCL1_VOL_ACTION_ENA (1 << 12)

View File

@ -776,8 +776,22 @@ static void si_query_hw_do_emit_start(struct si_context *sctx, struct si_query_h
case PIPE_QUERY_OCCLUSION_PREDICATE:
case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE: {
radeon_begin(cs);
if (sctx->chip_class >= GFX11) {
uint64_t rb_mask = BITFIELD64_MASK(sctx->screen->info.max_render_backends);
radeon_emit(PKT3(PKT3_EVENT_WRITE, 2, 0));
radeon_emit(EVENT_TYPE(V_028A90_PIXEL_PIPE_STAT_CONTROL) | EVENT_INDEX(1));
radeon_emit(PIXEL_PIPE_STATE_CNTL_COUNTER_ID(0) |
PIXEL_PIPE_STATE_CNTL_STRIDE(2) |
PIXEL_PIPE_STATE_CNTL_INSTANCE_EN_LO(rb_mask));
radeon_emit(PIXEL_PIPE_STATE_CNTL_INSTANCE_EN_HI(rb_mask));
}
radeon_emit(PKT3(PKT3_EVENT_WRITE, 2, 0));
radeon_emit(EVENT_TYPE(V_028A90_ZPASS_DONE) | EVENT_INDEX(1));
if (sctx->chip_class >= GFX11)
radeon_emit(EVENT_TYPE(V_028A90_PIXEL_PIPE_STAT_DUMP) | EVENT_INDEX(1));
else
radeon_emit(EVENT_TYPE(V_028A90_ZPASS_DONE) | EVENT_INDEX(1));
radeon_emit(va);
radeon_emit(va >> 32);
radeon_end();
@ -845,7 +859,10 @@ static void si_query_hw_do_emit_stop(struct si_context *sctx, struct si_query_hw
va += 8;
radeon_begin(cs);
radeon_emit(PKT3(PKT3_EVENT_WRITE, 2, 0));
radeon_emit(EVENT_TYPE(V_028A90_ZPASS_DONE) | EVENT_INDEX(1));
if (sctx->chip_class >= GFX11)
radeon_emit(EVENT_TYPE(V_028A90_PIXEL_PIPE_STAT_DUMP) | EVENT_INDEX(1));
else
radeon_emit(EVENT_TYPE(V_028A90_ZPASS_DONE) | EVENT_INDEX(1));
radeon_emit(va);
radeon_emit(va >> 32);
radeon_end();