2014-12-07 16:53:56 +00:00
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/*
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* Copyright 2012 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* on the rights to use, copy, modify, merge, publish, distribute, sub
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* license, and/or sell copies of the Software, and to permit persons to whom
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* the Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Christian König <christian.koenig@amd.com>
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* Marek Olšák <maraeo@gmail.com>
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*/
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#include "si_pipe.h"
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#include "sid.h"
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2015-08-30 02:17:30 +01:00
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#include "radeon/r600_cs.h"
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2014-12-07 16:53:56 +00:00
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#include "tgsi/tgsi_parse.h"
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2015-05-18 00:59:37 +01:00
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#include "tgsi/tgsi_ureg.h"
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2016-02-11 14:49:34 +00:00
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#include "util/hash_table.h"
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2016-11-18 18:20:54 +00:00
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#include "util/crc32.h"
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2014-12-07 16:53:56 +00:00
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#include "util/u_memory.h"
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2015-11-08 12:34:44 +00:00
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#include "util/u_prim.h"
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2014-12-07 16:53:56 +00:00
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2017-01-24 16:08:22 +00:00
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#include "util/disk_cache.h"
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#include "util/mesa-sha1.h"
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2016-02-11 14:49:34 +00:00
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/* SHADER_CACHE */
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/**
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* Return the TGSI binary in a buffer. The first 4 bytes contain its size as
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* integer.
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*/
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static void *si_get_tgsi_binary(struct si_shader_selector *sel)
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{
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unsigned tgsi_size = tgsi_num_tokens(sel->tokens) *
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sizeof(struct tgsi_token);
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unsigned size = 4 + tgsi_size + sizeof(sel->so);
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char *result = (char*)MALLOC(size);
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if (!result)
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return NULL;
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*((uint32_t*)result) = size;
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memcpy(result + 4, sel->tokens, tgsi_size);
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memcpy(result + 4 + tgsi_size, &sel->so, sizeof(sel->so));
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return result;
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}
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/** Copy "data" to "ptr" and return the next dword following copied data. */
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static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
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{
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2016-04-30 05:41:59 +01:00
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/* data may be NULL if size == 0 */
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if (size)
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memcpy(ptr, data, size);
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2016-02-11 14:49:34 +00:00
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ptr += DIV_ROUND_UP(size, 4);
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return ptr;
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}
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/** Read data from "ptr". Return the next dword following the data. */
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static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
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{
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memcpy(data, ptr, size);
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ptr += DIV_ROUND_UP(size, 4);
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return ptr;
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}
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/**
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* Write the size as uint followed by the data. Return the next dword
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* following the copied data.
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*/
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static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
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{
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*ptr++ = size;
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return write_data(ptr, data, size);
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}
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/**
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* Read the size as uint followed by the data. Return both via parameters.
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* Return the next dword following the data.
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*/
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static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
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{
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*size = *ptr++;
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assert(*data == NULL);
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2016-06-30 23:10:15 +01:00
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if (!*size)
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return ptr;
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2016-02-11 14:49:34 +00:00
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*data = malloc(*size);
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return read_data(ptr, *data, *size);
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}
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/**
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* Return the shader binary in a buffer. The first 4 bytes contain its size
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* as integer.
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*/
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static void *si_get_shader_binary(struct si_shader *shader)
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{
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/* There is always a size of data followed by the data itself. */
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unsigned relocs_size = shader->binary.reloc_count *
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sizeof(shader->binary.relocs[0]);
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unsigned disasm_size = strlen(shader->binary.disasm_string) + 1;
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2016-06-30 23:10:15 +01:00
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unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
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strlen(shader->binary.llvm_ir_string) + 1 : 0;
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2016-02-11 14:49:34 +00:00
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unsigned size =
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4 + /* total size */
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4 + /* CRC32 of the data below */
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align(sizeof(shader->config), 4) +
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align(sizeof(shader->info), 4) +
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4 + align(shader->binary.code_size, 4) +
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4 + align(shader->binary.rodata_size, 4) +
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4 + align(relocs_size, 4) +
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2016-06-30 23:10:15 +01:00
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4 + align(disasm_size, 4) +
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4 + align(llvm_ir_size, 4);
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2016-02-11 14:49:34 +00:00
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void *buffer = CALLOC(1, size);
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uint32_t *ptr = (uint32_t*)buffer;
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if (!buffer)
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return NULL;
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*ptr++ = size;
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ptr++; /* CRC32 is calculated at the end. */
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ptr = write_data(ptr, &shader->config, sizeof(shader->config));
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ptr = write_data(ptr, &shader->info, sizeof(shader->info));
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ptr = write_chunk(ptr, shader->binary.code, shader->binary.code_size);
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ptr = write_chunk(ptr, shader->binary.rodata, shader->binary.rodata_size);
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ptr = write_chunk(ptr, shader->binary.relocs, relocs_size);
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ptr = write_chunk(ptr, shader->binary.disasm_string, disasm_size);
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2016-06-30 23:10:15 +01:00
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ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
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2016-02-11 14:49:34 +00:00
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assert((char *)ptr - (char *)buffer == size);
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/* Compute CRC32. */
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ptr = (uint32_t*)buffer;
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ptr++;
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*ptr = util_hash_crc32(ptr + 1, size - 8);
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return buffer;
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}
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static bool si_load_shader_binary(struct si_shader *shader, void *binary)
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{
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uint32_t *ptr = (uint32_t*)binary;
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uint32_t size = *ptr++;
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uint32_t crc32 = *ptr++;
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unsigned chunk_size;
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if (util_hash_crc32(ptr, size - 8) != crc32) {
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fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
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return false;
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}
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ptr = read_data(ptr, &shader->config, sizeof(shader->config));
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ptr = read_data(ptr, &shader->info, sizeof(shader->info));
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ptr = read_chunk(ptr, (void**)&shader->binary.code,
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&shader->binary.code_size);
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ptr = read_chunk(ptr, (void**)&shader->binary.rodata,
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&shader->binary.rodata_size);
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ptr = read_chunk(ptr, (void**)&shader->binary.relocs, &chunk_size);
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shader->binary.reloc_count = chunk_size / sizeof(shader->binary.relocs[0]);
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ptr = read_chunk(ptr, (void**)&shader->binary.disasm_string, &chunk_size);
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2016-06-30 23:10:15 +01:00
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ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
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2016-02-11 14:49:34 +00:00
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return true;
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}
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/**
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* Insert a shader into the cache. It's assumed the shader is not in the cache.
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* Use si_shader_cache_load_shader before calling this.
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*
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* Returns false on failure, in which case the tgsi_binary should be freed.
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*/
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static bool si_shader_cache_insert_shader(struct si_screen *sscreen,
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void *tgsi_binary,
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2017-01-24 16:08:22 +00:00
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struct si_shader *shader,
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bool insert_into_disk_cache)
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2016-02-11 14:49:34 +00:00
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{
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2016-06-11 18:32:53 +01:00
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void *hw_binary;
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struct hash_entry *entry;
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2017-01-24 16:08:22 +00:00
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uint8_t key[CACHE_KEY_SIZE];
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2016-02-11 14:49:34 +00:00
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2016-06-11 18:32:53 +01:00
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entry = _mesa_hash_table_search(sscreen->shader_cache, tgsi_binary);
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if (entry)
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return false; /* already added */
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hw_binary = si_get_shader_binary(shader);
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2016-02-11 14:49:34 +00:00
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if (!hw_binary)
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return false;
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if (_mesa_hash_table_insert(sscreen->shader_cache, tgsi_binary,
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hw_binary) == NULL) {
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FREE(hw_binary);
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return false;
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}
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2017-01-24 16:08:22 +00:00
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if (sscreen->b.disk_shader_cache && insert_into_disk_cache) {
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2017-03-15 23:09:27 +00:00
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disk_cache_compute_key(sscreen->b.disk_shader_cache, tgsi_binary,
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*((uint32_t *)tgsi_binary), key);
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2017-01-24 16:08:22 +00:00
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disk_cache_put(sscreen->b.disk_shader_cache, key, hw_binary,
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*((uint32_t *) hw_binary));
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}
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2016-02-11 14:49:34 +00:00
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return true;
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}
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static bool si_shader_cache_load_shader(struct si_screen *sscreen,
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void *tgsi_binary,
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struct si_shader *shader)
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{
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struct hash_entry *entry =
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_mesa_hash_table_search(sscreen->shader_cache, tgsi_binary);
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2017-01-24 16:08:22 +00:00
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if (!entry) {
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if (sscreen->b.disk_shader_cache) {
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unsigned char sha1[CACHE_KEY_SIZE];
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size_t tg_size = *((uint32_t *) tgsi_binary);
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2017-03-15 23:09:27 +00:00
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disk_cache_compute_key(sscreen->b.disk_shader_cache,
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tgsi_binary, tg_size, sha1);
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2017-01-24 16:08:22 +00:00
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size_t binary_size;
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uint8_t *buffer =
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disk_cache_get(sscreen->b.disk_shader_cache,
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sha1, &binary_size);
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if (!buffer)
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return false;
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if (binary_size < sizeof(uint32_t) ||
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*((uint32_t*)buffer) != binary_size) {
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/* Something has gone wrong discard the item
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* from the cache and rebuild/link from
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* source.
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*/
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assert(!"Invalid radeonsi shader disk cache "
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"item!");
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disk_cache_remove(sscreen->b.disk_shader_cache,
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sha1);
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free(buffer);
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return false;
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}
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2016-02-11 14:49:34 +00:00
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2017-01-24 16:08:22 +00:00
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if (!si_load_shader_binary(shader, buffer)) {
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free(buffer);
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return false;
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}
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free(buffer);
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2016-02-11 23:58:46 +00:00
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2017-01-24 16:08:22 +00:00
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if (!si_shader_cache_insert_shader(sscreen, tgsi_binary,
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shader, false))
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FREE(tgsi_binary);
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} else {
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return false;
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}
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} else {
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if (si_load_shader_binary(shader, entry->data))
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FREE(tgsi_binary);
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else
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return false;
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}
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2016-02-11 23:58:46 +00:00
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p_atomic_inc(&sscreen->b.num_shader_cache_hits);
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return true;
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2016-02-11 14:49:34 +00:00
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}
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static uint32_t si_shader_cache_key_hash(const void *key)
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{
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/* The first dword is the key size. */
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return util_hash_crc32(key, *(uint32_t*)key);
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}
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static bool si_shader_cache_key_equals(const void *a, const void *b)
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{
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uint32_t *keya = (uint32_t*)a;
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uint32_t *keyb = (uint32_t*)b;
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/* The first dword is the key size. */
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if (*keya != *keyb)
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return false;
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return memcmp(keya, keyb, *keya) == 0;
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}
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static void si_destroy_shader_cache_entry(struct hash_entry *entry)
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{
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FREE((void*)entry->key);
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FREE(entry->data);
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}
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bool si_init_shader_cache(struct si_screen *sscreen)
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{
|
2017-03-05 01:00:15 +00:00
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(void) mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
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2016-02-11 14:49:34 +00:00
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sscreen->shader_cache =
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_mesa_hash_table_create(NULL,
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si_shader_cache_key_hash,
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si_shader_cache_key_equals);
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2017-01-24 16:08:22 +00:00
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2016-02-11 14:49:34 +00:00
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return sscreen->shader_cache != NULL;
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}
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void si_destroy_shader_cache(struct si_screen *sscreen)
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{
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if (sscreen->shader_cache)
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_mesa_hash_table_destroy(sscreen->shader_cache,
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si_destroy_shader_cache_entry);
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2017-03-05 01:32:04 +00:00
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mtx_destroy(&sscreen->shader_cache_mutex);
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2016-02-11 14:49:34 +00:00
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}
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/* SHADER STATES */
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|
2016-04-12 19:28:46 +01:00
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static void si_set_tesseval_regs(struct si_screen *sscreen,
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struct si_shader *shader,
|
2015-02-22 16:07:34 +00:00
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struct si_pm4_state *pm4)
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|
|
|
{
|
|
|
|
struct tgsi_shader_info *info = &shader->selector->info;
|
|
|
|
unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
|
|
|
|
unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
|
|
|
|
bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
|
|
|
|
bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
|
2016-04-12 19:28:46 +01:00
|
|
|
unsigned type, partitioning, topology, distribution_mode;
|
2015-02-22 16:07:34 +00:00
|
|
|
|
|
|
|
switch (tes_prim_mode) {
|
|
|
|
case PIPE_PRIM_LINES:
|
|
|
|
type = V_028B6C_TESS_ISOLINE;
|
|
|
|
break;
|
|
|
|
case PIPE_PRIM_TRIANGLES:
|
|
|
|
type = V_028B6C_TESS_TRIANGLE;
|
|
|
|
break;
|
|
|
|
case PIPE_PRIM_QUADS:
|
|
|
|
type = V_028B6C_TESS_QUAD;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
assert(0);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (tes_spacing) {
|
|
|
|
case PIPE_TESS_SPACING_FRACTIONAL_ODD:
|
|
|
|
partitioning = V_028B6C_PART_FRAC_ODD;
|
|
|
|
break;
|
|
|
|
case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
|
|
|
|
partitioning = V_028B6C_PART_FRAC_EVEN;
|
|
|
|
break;
|
|
|
|
case PIPE_TESS_SPACING_EQUAL:
|
|
|
|
partitioning = V_028B6C_PART_INTEGER;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
assert(0);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (tes_point_mode)
|
|
|
|
topology = V_028B6C_OUTPUT_POINT;
|
|
|
|
else if (tes_prim_mode == PIPE_PRIM_LINES)
|
|
|
|
topology = V_028B6C_OUTPUT_LINE;
|
|
|
|
else if (tes_vertex_order_cw)
|
|
|
|
/* for some reason, this must be the other way around */
|
|
|
|
topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
|
|
|
|
else
|
|
|
|
topology = V_028B6C_OUTPUT_TRIANGLE_CW;
|
|
|
|
|
2016-06-28 13:19:04 +01:00
|
|
|
if (sscreen->has_distributed_tess) {
|
2016-06-17 19:08:42 +01:00
|
|
|
if (sscreen->b.family == CHIP_FIJI ||
|
|
|
|
sscreen->b.family >= CHIP_POLARIS10)
|
|
|
|
distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
|
|
|
|
else
|
|
|
|
distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
|
|
|
|
} else
|
2016-04-12 19:28:46 +01:00
|
|
|
distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
|
|
|
|
|
2015-02-22 16:07:34 +00:00
|
|
|
si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
|
|
|
|
S_028B6C_TYPE(type) |
|
|
|
|
S_028B6C_PARTITIONING(partitioning) |
|
2016-04-12 19:28:46 +01:00
|
|
|
S_028B6C_TOPOLOGY(topology) |
|
|
|
|
S_028B6C_DISTRIBUTION_MODE(distribution_mode));
|
2015-02-22 16:07:34 +00:00
|
|
|
}
|
|
|
|
|
2017-01-25 02:27:34 +00:00
|
|
|
/* Polaris needs different VTX_REUSE_DEPTH settings depending on
|
|
|
|
* whether the "fractional odd" tessellation spacing is used.
|
|
|
|
*
|
|
|
|
* Possible VGT configurations and which state should set the register:
|
|
|
|
*
|
|
|
|
* Reg set in | VGT shader configuration | Value
|
|
|
|
* ------------------------------------------------------
|
|
|
|
* VS as VS | VS | 30
|
|
|
|
* VS as ES | ES -> GS -> VS | 30
|
|
|
|
* TES as VS | LS -> HS -> VS | 14 or 30
|
|
|
|
* TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
|
|
|
|
*/
|
|
|
|
static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
|
|
|
|
struct si_shader *shader,
|
|
|
|
struct si_pm4_state *pm4)
|
|
|
|
{
|
|
|
|
unsigned type = shader->selector->type;
|
|
|
|
|
|
|
|
if (sscreen->b.family < CHIP_POLARIS10)
|
|
|
|
return;
|
|
|
|
|
|
|
|
/* VS as VS, or VS as ES: */
|
|
|
|
if ((type == PIPE_SHADER_VERTEX &&
|
|
|
|
!shader->key.as_ls &&
|
|
|
|
!shader->is_gs_copy_shader) ||
|
|
|
|
/* TES as VS, or TES as ES: */
|
|
|
|
type == PIPE_SHADER_TESS_EVAL) {
|
|
|
|
unsigned vtx_reuse_depth = 30;
|
|
|
|
|
|
|
|
if (type == PIPE_SHADER_TESS_EVAL &&
|
|
|
|
shader->selector->info.properties[TGSI_PROPERTY_TES_SPACING] ==
|
|
|
|
PIPE_TESS_SPACING_FRACTIONAL_ODD)
|
|
|
|
vtx_reuse_depth = 14;
|
|
|
|
|
|
|
|
si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
|
|
|
|
vtx_reuse_depth);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-06-11 20:07:14 +01:00
|
|
|
static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
|
|
|
|
{
|
|
|
|
if (shader->pm4)
|
|
|
|
si_pm4_clear_state(shader->pm4);
|
|
|
|
else
|
|
|
|
shader->pm4 = CALLOC_STRUCT(si_pm4_state);
|
|
|
|
|
|
|
|
return shader->pm4;
|
|
|
|
}
|
|
|
|
|
2015-02-22 16:07:34 +00:00
|
|
|
static void si_shader_ls(struct si_shader *shader)
|
|
|
|
{
|
|
|
|
struct si_pm4_state *pm4;
|
|
|
|
unsigned vgpr_comp_cnt;
|
|
|
|
uint64_t va;
|
|
|
|
|
2016-06-11 20:07:14 +01:00
|
|
|
pm4 = si_get_shader_pm4_state(shader);
|
2015-12-04 11:08:22 +00:00
|
|
|
if (!pm4)
|
2015-02-22 16:07:34 +00:00
|
|
|
return;
|
|
|
|
|
|
|
|
va = shader->bo->gpu_address;
|
2016-08-17 13:22:11 +01:00
|
|
|
si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
|
2015-02-22 16:07:34 +00:00
|
|
|
|
|
|
|
/* We need at least 2 components for LS.
|
|
|
|
* VGPR0-3: (VertexID, RelAutoindex, ???, InstanceID). */
|
2016-02-11 20:09:38 +00:00
|
|
|
vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 1;
|
2015-02-22 16:07:34 +00:00
|
|
|
|
|
|
|
si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
|
|
|
|
si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, va >> 40);
|
|
|
|
|
2015-12-27 23:14:05 +00:00
|
|
|
shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
|
2016-04-13 12:50:04 +01:00
|
|
|
S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
|
2015-10-08 21:23:18 +01:00
|
|
|
S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
|
2016-02-05 21:49:12 +00:00
|
|
|
S_00B528_DX10_CLAMP(1) |
|
|
|
|
S_00B528_FLOAT_MODE(shader->config.float_mode);
|
2016-04-13 13:15:16 +01:00
|
|
|
shader->config.rsrc2 = S_00B52C_USER_SGPR(SI_LS_NUM_USER_SGPR) |
|
2015-12-27 23:14:05 +00:00
|
|
|
S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
|
2015-02-22 16:07:34 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void si_shader_hs(struct si_shader *shader)
|
|
|
|
{
|
|
|
|
struct si_pm4_state *pm4;
|
|
|
|
uint64_t va;
|
|
|
|
|
2016-06-11 20:07:14 +01:00
|
|
|
pm4 = si_get_shader_pm4_state(shader);
|
2015-12-04 11:08:22 +00:00
|
|
|
if (!pm4)
|
2015-02-22 16:07:34 +00:00
|
|
|
return;
|
|
|
|
|
|
|
|
va = shader->bo->gpu_address;
|
2016-08-17 13:22:11 +01:00
|
|
|
si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
|
2015-02-22 16:07:34 +00:00
|
|
|
|
|
|
|
si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
|
|
|
|
si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, va >> 40);
|
|
|
|
si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
|
2015-12-27 23:14:05 +00:00
|
|
|
S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) |
|
2016-04-13 12:50:04 +01:00
|
|
|
S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) |
|
2016-02-05 21:49:12 +00:00
|
|
|
S_00B428_DX10_CLAMP(1) |
|
|
|
|
S_00B428_FLOAT_MODE(shader->config.float_mode));
|
2015-02-22 16:07:34 +00:00
|
|
|
si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
|
2016-04-13 13:15:16 +01:00
|
|
|
S_00B42C_USER_SGPR(SI_TCS_NUM_USER_SGPR) |
|
2016-05-02 12:20:43 +01:00
|
|
|
S_00B42C_OC_LDS_EN(1) |
|
2015-12-27 23:14:05 +00:00
|
|
|
S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
|
2015-02-22 16:07:34 +00:00
|
|
|
}
|
|
|
|
|
2016-04-12 19:28:46 +01:00
|
|
|
static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
|
2014-12-07 16:53:56 +00:00
|
|
|
{
|
|
|
|
struct si_pm4_state *pm4;
|
2016-04-13 12:50:04 +01:00
|
|
|
unsigned num_user_sgprs;
|
2014-12-07 16:53:56 +00:00
|
|
|
unsigned vgpr_comp_cnt;
|
|
|
|
uint64_t va;
|
2016-05-02 12:20:43 +01:00
|
|
|
unsigned oc_lds_en;
|
2014-12-07 16:53:56 +00:00
|
|
|
|
2016-06-11 20:07:14 +01:00
|
|
|
pm4 = si_get_shader_pm4_state(shader);
|
2015-12-04 11:08:22 +00:00
|
|
|
if (!pm4)
|
2014-12-07 16:53:56 +00:00
|
|
|
return;
|
|
|
|
|
|
|
|
va = shader->bo->gpu_address;
|
2016-08-17 13:22:11 +01:00
|
|
|
si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
|
2014-12-07 16:53:56 +00:00
|
|
|
|
2015-02-22 16:07:34 +00:00
|
|
|
if (shader->selector->type == PIPE_SHADER_VERTEX) {
|
2016-02-11 20:09:38 +00:00
|
|
|
vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 0;
|
2015-10-07 01:36:38 +01:00
|
|
|
num_user_sgprs = SI_ES_NUM_USER_SGPR;
|
2015-02-22 16:07:34 +00:00
|
|
|
} else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
|
|
|
|
vgpr_comp_cnt = 3; /* all components are needed for TES */
|
|
|
|
num_user_sgprs = SI_TES_NUM_USER_SGPR;
|
|
|
|
} else
|
2015-08-18 01:23:29 +01:00
|
|
|
unreachable("invalid shader selector type");
|
2014-12-07 16:53:56 +00:00
|
|
|
|
2016-05-02 12:20:43 +01:00
|
|
|
oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
|
|
|
|
|
2015-10-15 22:29:00 +01:00
|
|
|
si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
|
|
|
|
shader->selector->esgs_itemsize / 4);
|
2014-12-07 16:53:56 +00:00
|
|
|
si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
|
|
|
|
si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
|
|
|
|
si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
|
2015-12-27 23:14:05 +00:00
|
|
|
S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
|
2016-04-13 12:50:04 +01:00
|
|
|
S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
|
2014-12-10 20:08:50 +00:00
|
|
|
S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
|
2016-02-05 21:49:12 +00:00
|
|
|
S_00B328_DX10_CLAMP(1) |
|
|
|
|
S_00B328_FLOAT_MODE(shader->config.float_mode));
|
2014-12-07 16:53:56 +00:00
|
|
|
si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
|
2014-12-10 14:13:59 +00:00
|
|
|
S_00B32C_USER_SGPR(num_user_sgprs) |
|
2016-05-02 12:20:43 +01:00
|
|
|
S_00B32C_OC_LDS_EN(oc_lds_en) |
|
2015-12-27 23:14:05 +00:00
|
|
|
S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
|
2015-02-22 16:07:34 +00:00
|
|
|
|
|
|
|
if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
|
2016-04-12 19:28:46 +01:00
|
|
|
si_set_tesseval_regs(sscreen, shader, pm4);
|
2017-01-25 02:27:34 +00:00
|
|
|
|
|
|
|
polaris_set_vgt_vertex_reuse(sscreen, shader, pm4);
|
2014-12-07 16:53:56 +00:00
|
|
|
}
|
|
|
|
|
2016-01-22 21:58:15 +00:00
|
|
|
/**
|
|
|
|
* Calculate the appropriate setting of VGT_GS_MODE when \p shader is a
|
|
|
|
* geometry shader.
|
|
|
|
*/
|
2016-10-31 20:07:53 +00:00
|
|
|
static uint32_t si_vgt_gs_mode(struct si_shader_selector *sel)
|
2016-01-22 21:58:15 +00:00
|
|
|
{
|
2016-10-31 20:07:53 +00:00
|
|
|
unsigned gs_max_vert_out = sel->gs_max_out_vertices;
|
2016-01-22 21:58:15 +00:00
|
|
|
unsigned cut_mode;
|
|
|
|
|
|
|
|
if (gs_max_vert_out <= 128) {
|
|
|
|
cut_mode = V_028A40_GS_CUT_128;
|
|
|
|
} else if (gs_max_vert_out <= 256) {
|
|
|
|
cut_mode = V_028A40_GS_CUT_256;
|
|
|
|
} else if (gs_max_vert_out <= 512) {
|
|
|
|
cut_mode = V_028A40_GS_CUT_512;
|
|
|
|
} else {
|
|
|
|
assert(gs_max_vert_out <= 1024);
|
|
|
|
cut_mode = V_028A40_GS_CUT_1024;
|
|
|
|
}
|
|
|
|
|
|
|
|
return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
|
|
|
|
S_028A40_CUT_MODE(cut_mode)|
|
|
|
|
S_028A40_ES_WRITE_OPTIMIZE(1) |
|
|
|
|
S_028A40_GS_WRITE_OPTIMIZE(1);
|
|
|
|
}
|
|
|
|
|
2014-12-07 16:53:56 +00:00
|
|
|
static void si_shader_gs(struct si_shader *shader)
|
|
|
|
{
|
2016-11-30 11:25:45 +00:00
|
|
|
struct si_shader_selector *sel = shader->selector;
|
|
|
|
const ubyte *num_components = sel->info.num_stream_output_components;
|
|
|
|
unsigned gs_num_invocations = sel->gs_num_invocations;
|
2014-12-07 16:53:56 +00:00
|
|
|
struct si_pm4_state *pm4;
|
|
|
|
uint64_t va;
|
2016-11-30 11:25:45 +00:00
|
|
|
unsigned max_stream = sel->max_gs_stream;
|
|
|
|
unsigned offset;
|
2014-12-07 16:53:56 +00:00
|
|
|
|
2016-06-11 20:07:14 +01:00
|
|
|
pm4 = si_get_shader_pm4_state(shader);
|
2015-12-04 11:08:22 +00:00
|
|
|
if (!pm4)
|
2014-12-07 16:53:56 +00:00
|
|
|
return;
|
|
|
|
|
2016-10-31 20:07:53 +00:00
|
|
|
si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(shader->selector));
|
2014-12-07 16:53:56 +00:00
|
|
|
|
2016-11-30 11:25:45 +00:00
|
|
|
offset = num_components[0] * sel->gs_max_out_vertices;
|
|
|
|
si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, offset);
|
|
|
|
if (max_stream >= 1)
|
|
|
|
offset += num_components[1] * sel->gs_max_out_vertices;
|
|
|
|
si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, offset);
|
|
|
|
if (max_stream >= 2)
|
|
|
|
offset += num_components[2] * sel->gs_max_out_vertices;
|
|
|
|
si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, offset);
|
|
|
|
if (max_stream >= 3)
|
|
|
|
offset += num_components[3] * sel->gs_max_out_vertices;
|
|
|
|
si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
|
2014-12-07 16:53:56 +00:00
|
|
|
|
2016-11-30 11:25:45 +00:00
|
|
|
/* The GSVS_RING_ITEMSIZE register takes 15 bits */
|
|
|
|
assert(offset < (1 << 15));
|
2014-12-07 16:53:56 +00:00
|
|
|
|
2016-01-22 21:58:15 +00:00
|
|
|
si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, shader->selector->gs_max_out_vertices);
|
2014-12-07 16:53:56 +00:00
|
|
|
|
2016-11-30 11:25:45 +00:00
|
|
|
si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, num_components[0]);
|
|
|
|
si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, (max_stream >= 1) ? num_components[1] : 0);
|
|
|
|
si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, (max_stream >= 2) ? num_components[2] : 0);
|
|
|
|
si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, (max_stream >= 3) ? num_components[3] : 0);
|
2014-12-07 16:53:56 +00:00
|
|
|
|
2015-06-25 03:55:54 +01:00
|
|
|
si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT,
|
|
|
|
S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
|
|
|
|
S_028B90_ENABLE(gs_num_invocations > 0));
|
|
|
|
|
2014-12-07 16:53:56 +00:00
|
|
|
va = shader->bo->gpu_address;
|
2016-08-17 13:22:11 +01:00
|
|
|
si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
|
2014-12-07 16:53:56 +00:00
|
|
|
si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
|
|
|
|
si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
|
|
|
|
|
|
|
|
si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
|
2015-12-27 23:14:05 +00:00
|
|
|
S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
|
2016-04-13 12:50:04 +01:00
|
|
|
S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
|
2016-02-05 21:49:12 +00:00
|
|
|
S_00B228_DX10_CLAMP(1) |
|
|
|
|
S_00B228_FLOAT_MODE(shader->config.float_mode));
|
2014-12-07 16:53:56 +00:00
|
|
|
si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
|
2016-04-13 13:15:16 +01:00
|
|
|
S_00B22C_USER_SGPR(SI_GS_NUM_USER_SGPR) |
|
2015-12-27 23:14:05 +00:00
|
|
|
S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
|
2014-12-07 16:53:56 +00:00
|
|
|
}
|
|
|
|
|
2016-01-22 22:04:48 +00:00
|
|
|
/**
|
|
|
|
* Compute the state for \p shader, which will run as a vertex shader on the
|
|
|
|
* hardware.
|
|
|
|
*
|
|
|
|
* If \p gs is non-NULL, it points to the geometry shader for which this shader
|
|
|
|
* is the copy shader.
|
|
|
|
*/
|
2016-04-12 19:28:46 +01:00
|
|
|
static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
|
2016-10-31 20:09:20 +00:00
|
|
|
struct si_shader_selector *gs)
|
2014-12-07 16:53:56 +00:00
|
|
|
{
|
|
|
|
struct si_pm4_state *pm4;
|
2016-04-13 12:50:04 +01:00
|
|
|
unsigned num_user_sgprs;
|
2015-07-06 09:23:07 +01:00
|
|
|
unsigned nparams, vgpr_comp_cnt;
|
2014-12-07 16:53:56 +00:00
|
|
|
uint64_t va;
|
2016-05-02 12:20:43 +01:00
|
|
|
unsigned oc_lds_en;
|
2014-12-07 16:53:56 +00:00
|
|
|
unsigned window_space =
|
|
|
|
shader->selector->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
|
2015-08-10 00:50:11 +01:00
|
|
|
bool enable_prim_id = si_vs_exports_prim_id(shader);
|
2014-12-07 16:53:56 +00:00
|
|
|
|
2016-06-11 20:07:14 +01:00
|
|
|
pm4 = si_get_shader_pm4_state(shader);
|
2015-12-04 11:08:22 +00:00
|
|
|
if (!pm4)
|
2014-12-07 16:53:56 +00:00
|
|
|
return;
|
|
|
|
|
2016-01-22 22:04:48 +00:00
|
|
|
/* We always write VGT_GS_MODE in the VS state, because every switch
|
|
|
|
* between different shader pipelines involving a different GS or no
|
|
|
|
* GS at all involves a switch of the VS (different GS use different
|
|
|
|
* copy shaders). On the other hand, when the API switches from a GS to
|
|
|
|
* no GS and then back to the same GS used originally, the GS state is
|
|
|
|
* not sent again.
|
2015-08-09 23:52:21 +01:00
|
|
|
*/
|
2016-01-22 22:04:48 +00:00
|
|
|
if (!gs) {
|
2015-08-10 00:50:11 +01:00
|
|
|
si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
|
|
|
|
S_028A40_MODE(enable_prim_id ? V_028A40_GS_SCENARIO_A : 0));
|
|
|
|
si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, enable_prim_id);
|
2016-01-22 22:04:48 +00:00
|
|
|
} else {
|
|
|
|
si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(gs));
|
2015-08-10 00:50:11 +01:00
|
|
|
si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0);
|
2016-01-22 22:04:48 +00:00
|
|
|
}
|
2015-08-09 23:52:21 +01:00
|
|
|
|
2014-12-07 16:53:56 +00:00
|
|
|
va = shader->bo->gpu_address;
|
2016-08-17 13:22:11 +01:00
|
|
|
si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
|
2014-12-07 16:53:56 +00:00
|
|
|
|
2016-01-22 22:09:58 +00:00
|
|
|
if (gs) {
|
2015-02-22 14:11:49 +00:00
|
|
|
vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
|
2014-12-07 16:53:56 +00:00
|
|
|
num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
|
2015-02-22 14:11:49 +00:00
|
|
|
} else if (shader->selector->type == PIPE_SHADER_VERTEX) {
|
2016-02-11 20:09:38 +00:00
|
|
|
vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : (enable_prim_id ? 2 : 0);
|
2014-12-07 16:53:56 +00:00
|
|
|
num_user_sgprs = SI_VS_NUM_USER_SGPR;
|
2015-02-22 16:07:34 +00:00
|
|
|
} else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
|
|
|
|
vgpr_comp_cnt = 3; /* all components are needed for TES */
|
|
|
|
num_user_sgprs = SI_TES_NUM_USER_SGPR;
|
2015-02-22 14:11:49 +00:00
|
|
|
} else
|
2015-08-18 01:23:29 +01:00
|
|
|
unreachable("invalid shader selector type");
|
2014-12-07 16:53:56 +00:00
|
|
|
|
2015-07-06 09:23:07 +01:00
|
|
|
/* VS is required to export at least one param. */
|
2016-02-11 20:09:38 +00:00
|
|
|
nparams = MAX2(shader->info.nr_param_exports, 1);
|
2014-12-07 16:53:56 +00:00
|
|
|
si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
|
|
|
|
S_0286C4_VS_EXPORT_COUNT(nparams - 1));
|
|
|
|
|
|
|
|
si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
|
|
|
|
S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
|
2016-02-11 20:09:38 +00:00
|
|
|
S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
|
2014-12-07 16:53:56 +00:00
|
|
|
V_02870C_SPI_SHADER_4COMP :
|
|
|
|
V_02870C_SPI_SHADER_NONE) |
|
2016-02-11 20:09:38 +00:00
|
|
|
S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
|
2014-12-07 16:53:56 +00:00
|
|
|
V_02870C_SPI_SHADER_4COMP :
|
|
|
|
V_02870C_SPI_SHADER_NONE) |
|
2016-02-11 20:09:38 +00:00
|
|
|
S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
|
2014-12-07 16:53:56 +00:00
|
|
|
V_02870C_SPI_SHADER_4COMP :
|
|
|
|
V_02870C_SPI_SHADER_NONE));
|
|
|
|
|
2016-05-02 12:20:43 +01:00
|
|
|
oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
|
|
|
|
|
2014-12-07 16:53:56 +00:00
|
|
|
si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
|
|
|
|
si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
|
|
|
|
si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
|
2015-12-27 23:14:05 +00:00
|
|
|
S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
|
2016-04-13 12:50:04 +01:00
|
|
|
S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8) |
|
2014-12-10 20:08:50 +00:00
|
|
|
S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
|
2016-02-05 21:49:12 +00:00
|
|
|
S_00B128_DX10_CLAMP(1) |
|
|
|
|
S_00B128_FLOAT_MODE(shader->config.float_mode));
|
2014-12-07 16:53:56 +00:00
|
|
|
si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
|
|
|
|
S_00B12C_USER_SGPR(num_user_sgprs) |
|
2016-05-02 12:20:43 +01:00
|
|
|
S_00B12C_OC_LDS_EN(oc_lds_en) |
|
2014-12-07 16:53:56 +00:00
|
|
|
S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
|
|
|
|
S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
|
|
|
|
S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
|
|
|
|
S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
|
2014-12-10 14:13:59 +00:00
|
|
|
S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
|
2015-12-27 23:14:05 +00:00
|
|
|
S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
|
2014-12-07 16:53:56 +00:00
|
|
|
if (window_space)
|
|
|
|
si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
|
|
|
|
S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
|
|
|
|
else
|
|
|
|
si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
|
|
|
|
S_028818_VTX_W0_FMT(1) |
|
|
|
|
S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
|
|
|
|
S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
|
|
|
|
S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
|
2015-02-22 16:07:34 +00:00
|
|
|
|
|
|
|
if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
|
2016-04-12 19:28:46 +01:00
|
|
|
si_set_tesseval_regs(sscreen, shader, pm4);
|
2017-01-25 02:27:34 +00:00
|
|
|
|
|
|
|
polaris_set_vgt_vertex_reuse(sscreen, shader, pm4);
|
2014-12-07 16:53:56 +00:00
|
|
|
}
|
|
|
|
|
2016-01-02 01:54:29 +00:00
|
|
|
static unsigned si_get_ps_num_interp(struct si_shader *ps)
|
|
|
|
{
|
|
|
|
struct tgsi_shader_info *info = &ps->selector->info;
|
|
|
|
unsigned num_colors = !!(info->colors_read & 0x0f) +
|
|
|
|
!!(info->colors_read & 0xf0);
|
|
|
|
unsigned num_interp = ps->selector->info.num_inputs +
|
2016-11-13 02:17:46 +00:00
|
|
|
(ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
|
2016-01-02 01:54:29 +00:00
|
|
|
|
|
|
|
assert(num_interp <= 32);
|
|
|
|
return MIN2(num_interp, 32);
|
|
|
|
}
|
|
|
|
|
2016-01-11 22:51:39 +00:00
|
|
|
static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
|
|
|
|
{
|
2016-11-13 02:17:46 +00:00
|
|
|
unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
|
2016-01-11 22:51:39 +00:00
|
|
|
unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
|
|
|
|
|
|
|
|
/* If the i-th target format is set, all previous target formats must
|
|
|
|
* be non-zero to avoid hangs.
|
|
|
|
*/
|
|
|
|
for (i = 0; i < num_targets; i++)
|
|
|
|
if (!(value & (0xf << (i * 4))))
|
|
|
|
value |= V_028714_SPI_SHADER_32_R << (i * 4);
|
|
|
|
|
|
|
|
return value;
|
|
|
|
}
|
|
|
|
|
2016-01-11 23:52:12 +00:00
|
|
|
static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
|
|
|
|
{
|
|
|
|
unsigned i, cb_shader_mask = 0;
|
|
|
|
|
|
|
|
for (i = 0; i < 8; i++) {
|
|
|
|
switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
|
|
|
|
case V_028714_SPI_SHADER_ZERO:
|
|
|
|
break;
|
|
|
|
case V_028714_SPI_SHADER_32_R:
|
|
|
|
cb_shader_mask |= 0x1 << (i * 4);
|
|
|
|
break;
|
|
|
|
case V_028714_SPI_SHADER_32_GR:
|
|
|
|
cb_shader_mask |= 0x3 << (i * 4);
|
|
|
|
break;
|
|
|
|
case V_028714_SPI_SHADER_32_AR:
|
|
|
|
cb_shader_mask |= 0x9 << (i * 4);
|
|
|
|
break;
|
|
|
|
case V_028714_SPI_SHADER_FP16_ABGR:
|
|
|
|
case V_028714_SPI_SHADER_UNORM16_ABGR:
|
|
|
|
case V_028714_SPI_SHADER_SNORM16_ABGR:
|
|
|
|
case V_028714_SPI_SHADER_UINT16_ABGR:
|
|
|
|
case V_028714_SPI_SHADER_SINT16_ABGR:
|
|
|
|
case V_028714_SPI_SHADER_32_ABGR:
|
|
|
|
cb_shader_mask |= 0xf << (i * 4);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
assert(0);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return cb_shader_mask;
|
|
|
|
}
|
|
|
|
|
2014-12-07 16:53:56 +00:00
|
|
|
static void si_shader_ps(struct si_shader *shader)
|
|
|
|
{
|
|
|
|
struct tgsi_shader_info *info = &shader->selector->info;
|
|
|
|
struct si_pm4_state *pm4;
|
2016-01-11 23:52:12 +00:00
|
|
|
unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
|
2016-01-02 22:09:58 +00:00
|
|
|
unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
|
2014-12-07 16:53:56 +00:00
|
|
|
uint64_t va;
|
2016-01-03 18:00:29 +00:00
|
|
|
unsigned input_ena = shader->config.spi_ps_input_ena;
|
|
|
|
|
|
|
|
/* we need to enable at least one of them, otherwise we hang the GPU */
|
|
|
|
assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
|
|
|
|
G_0286CC_PERSP_CENTER_ENA(input_ena) ||
|
|
|
|
G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
|
|
|
|
G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
|
|
|
|
G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
|
|
|
|
G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
|
|
|
|
G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
|
|
|
|
G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
|
2016-10-04 18:53:53 +01:00
|
|
|
/* POS_W_FLOAT_ENA requires one of the perspective weights. */
|
|
|
|
assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
|
|
|
|
G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
|
|
|
|
G_0286CC_PERSP_CENTER_ENA(input_ena) ||
|
|
|
|
G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
|
|
|
|
G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
|
|
|
|
|
|
|
|
/* Validate interpolation optimization flags (read as implications). */
|
2016-11-13 02:17:46 +00:00
|
|
|
assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
|
2016-10-04 18:53:53 +01:00
|
|
|
(G_0286CC_PERSP_CENTER_ENA(input_ena) &&
|
|
|
|
G_0286CC_PERSP_CENTROID_ENA(input_ena)));
|
2016-11-13 02:17:46 +00:00
|
|
|
assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
|
2016-10-04 18:53:53 +01:00
|
|
|
(G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
|
|
|
|
G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
|
2016-11-13 02:17:46 +00:00
|
|
|
assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
|
2016-10-04 18:53:53 +01:00
|
|
|
(!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
|
|
|
|
!G_0286CC_PERSP_CENTROID_ENA(input_ena)));
|
2016-11-13 02:17:46 +00:00
|
|
|
assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
|
2016-10-04 18:53:53 +01:00
|
|
|
(!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
|
|
|
|
!G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
|
2016-11-13 02:17:46 +00:00
|
|
|
assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
|
2016-10-04 18:53:53 +01:00
|
|
|
(!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
|
|
|
|
!G_0286CC_PERSP_CENTROID_ENA(input_ena)));
|
2016-11-13 02:17:46 +00:00
|
|
|
assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
|
2016-10-04 18:53:53 +01:00
|
|
|
(!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
|
|
|
|
!G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
|
|
|
|
|
|
|
|
/* Validate cases when the optimizations are off (read as implications). */
|
2016-11-13 02:17:46 +00:00
|
|
|
assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
|
2016-10-04 18:53:53 +01:00
|
|
|
!G_0286CC_PERSP_CENTER_ENA(input_ena) ||
|
|
|
|
!G_0286CC_PERSP_CENTROID_ENA(input_ena));
|
2016-11-13 02:17:46 +00:00
|
|
|
assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
|
2016-10-04 18:53:53 +01:00
|
|
|
!G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
|
|
|
|
!G_0286CC_LINEAR_CENTROID_ENA(input_ena));
|
2014-12-07 16:53:56 +00:00
|
|
|
|
2016-06-11 20:07:14 +01:00
|
|
|
pm4 = si_get_shader_pm4_state(shader);
|
2015-12-04 11:08:22 +00:00
|
|
|
if (!pm4)
|
2014-12-07 16:53:56 +00:00
|
|
|
return;
|
|
|
|
|
2016-01-07 19:00:34 +00:00
|
|
|
/* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
|
|
|
|
* Possible vaules:
|
|
|
|
* 0 -> Position = pixel center
|
|
|
|
* 1 -> Position = pixel centroid
|
|
|
|
* 2 -> Position = at sample position
|
|
|
|
*
|
|
|
|
* From GLSL 4.5 specification, section 7.1:
|
|
|
|
* "The variable gl_FragCoord is available as an input variable from
|
|
|
|
* within fragment shaders and it holds the window relative coordinates
|
|
|
|
* (x, y, z, 1/w) values for the fragment. If multi-sampling, this
|
|
|
|
* value can be for any location within the pixel, or one of the
|
|
|
|
* fragment samples. The use of centroid does not further restrict
|
|
|
|
* this value to be inside the current primitive."
|
|
|
|
*
|
|
|
|
* Meaning that centroid has no effect and we can return anything within
|
|
|
|
* the pixel. Thus, return the value at sample position, because that's
|
|
|
|
* the most accurate one shaders can get.
|
|
|
|
*/
|
|
|
|
spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
|
|
|
|
|
|
|
|
if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
|
|
|
|
TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
|
|
|
|
spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
|
2014-12-07 16:53:56 +00:00
|
|
|
|
2016-01-11 22:51:39 +00:00
|
|
|
spi_shader_col_format = si_get_spi_shader_col_format(shader);
|
2016-01-11 23:52:12 +00:00
|
|
|
cb_shader_mask = si_get_cb_shader_mask(spi_shader_col_format);
|
2016-01-11 22:51:39 +00:00
|
|
|
|
2016-05-05 01:05:14 +01:00
|
|
|
/* Ensure that some export memory is always allocated, for two reasons:
|
|
|
|
*
|
|
|
|
* 1) Correctness: The hardware ignores the EXEC mask if no export
|
|
|
|
* memory is allocated, so KILL and alpha test do not work correctly
|
|
|
|
* without this.
|
|
|
|
* 2) Performance: Every shader needs at least a NULL export, even when
|
|
|
|
* it writes no color/depth output. The NULL export instruction
|
|
|
|
* stalls without this setting.
|
|
|
|
*
|
2016-01-11 23:52:12 +00:00
|
|
|
* Don't add this to CB_SHADER_MASK.
|
2016-01-11 22:51:39 +00:00
|
|
|
*/
|
|
|
|
if (!spi_shader_col_format &&
|
2016-05-05 01:05:14 +01:00
|
|
|
!info->writes_z && !info->writes_stencil && !info->writes_samplemask)
|
2016-01-11 22:51:39 +00:00
|
|
|
spi_shader_col_format = V_028714_SPI_SHADER_32_R;
|
|
|
|
|
2016-01-03 18:00:29 +00:00
|
|
|
si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, input_ena);
|
2016-01-06 15:03:38 +00:00
|
|
|
si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR,
|
|
|
|
shader->config.spi_ps_input_addr);
|
2016-01-03 18:00:29 +00:00
|
|
|
|
2015-12-23 15:43:54 +00:00
|
|
|
/* Set interpolation controls. */
|
2016-06-30 01:16:16 +01:00
|
|
|
spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader));
|
2015-01-13 07:38:52 +00:00
|
|
|
|
2015-12-23 15:43:54 +00:00
|
|
|
/* Set registers. */
|
2014-12-07 16:53:56 +00:00
|
|
|
si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
|
2015-01-13 07:38:52 +00:00
|
|
|
si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
|
2014-12-07 16:53:56 +00:00
|
|
|
|
2015-12-23 15:02:46 +00:00
|
|
|
si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT,
|
2016-09-10 00:21:11 +01:00
|
|
|
si_get_spi_shader_z_format(info->writes_z,
|
|
|
|
info->writes_stencil,
|
|
|
|
info->writes_samplemask));
|
2015-12-23 15:02:46 +00:00
|
|
|
|
2015-12-23 15:43:54 +00:00
|
|
|
si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT, spi_shader_col_format);
|
|
|
|
si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, cb_shader_mask);
|
2014-12-07 16:53:56 +00:00
|
|
|
|
|
|
|
va = shader->bo->gpu_address;
|
2016-08-17 13:22:11 +01:00
|
|
|
si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
|
2014-12-07 16:53:56 +00:00
|
|
|
si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
|
|
|
|
si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
|
|
|
|
|
|
|
|
si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
|
2015-12-27 23:14:05 +00:00
|
|
|
S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
|
2016-04-13 12:50:04 +01:00
|
|
|
S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8) |
|
2016-02-05 21:49:12 +00:00
|
|
|
S_00B028_DX10_CLAMP(1) |
|
|
|
|
S_00B028_FLOAT_MODE(shader->config.float_mode));
|
2014-12-07 16:53:56 +00:00
|
|
|
si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
|
2015-12-27 23:14:05 +00:00
|
|
|
S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
|
2016-04-13 13:15:16 +01:00
|
|
|
S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
|
2015-12-27 23:14:05 +00:00
|
|
|
S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
|
2014-12-07 16:53:56 +00:00
|
|
|
}
|
|
|
|
|
2016-04-12 19:28:46 +01:00
|
|
|
static void si_shader_init_pm4_state(struct si_screen *sscreen,
|
|
|
|
struct si_shader *shader)
|
2014-12-07 16:53:56 +00:00
|
|
|
{
|
|
|
|
switch (shader->selector->type) {
|
|
|
|
case PIPE_SHADER_VERTEX:
|
2016-11-13 02:17:46 +00:00
|
|
|
if (shader->key.as_ls)
|
2015-02-22 16:07:34 +00:00
|
|
|
si_shader_ls(shader);
|
2016-11-13 02:17:46 +00:00
|
|
|
else if (shader->key.as_es)
|
2016-04-12 19:28:46 +01:00
|
|
|
si_shader_es(sscreen, shader);
|
2015-02-22 16:07:34 +00:00
|
|
|
else
|
2016-04-12 19:28:46 +01:00
|
|
|
si_shader_vs(sscreen, shader, NULL);
|
2015-02-22 16:07:34 +00:00
|
|
|
break;
|
|
|
|
case PIPE_SHADER_TESS_CTRL:
|
|
|
|
si_shader_hs(shader);
|
|
|
|
break;
|
|
|
|
case PIPE_SHADER_TESS_EVAL:
|
2016-11-13 02:17:46 +00:00
|
|
|
if (shader->key.as_es)
|
2016-04-12 19:28:46 +01:00
|
|
|
si_shader_es(sscreen, shader);
|
2014-12-07 16:53:56 +00:00
|
|
|
else
|
2016-04-12 19:28:46 +01:00
|
|
|
si_shader_vs(sscreen, shader, NULL);
|
2014-12-07 16:53:56 +00:00
|
|
|
break;
|
|
|
|
case PIPE_SHADER_GEOMETRY:
|
|
|
|
si_shader_gs(shader);
|
|
|
|
break;
|
|
|
|
case PIPE_SHADER_FRAGMENT:
|
|
|
|
si_shader_ps(shader);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
assert(0);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-12-23 14:36:05 +00:00
|
|
|
static unsigned si_get_alpha_test_func(struct si_context *sctx)
|
|
|
|
{
|
|
|
|
/* Alpha-test should be disabled if colorbuffer 0 is integer. */
|
2016-09-16 21:42:54 +01:00
|
|
|
if (sctx->queued.named.dsa)
|
2015-12-23 14:36:05 +00:00
|
|
|
return sctx->queued.named.dsa->alpha_func;
|
|
|
|
|
|
|
|
return PIPE_FUNC_ALWAYS;
|
|
|
|
}
|
|
|
|
|
2016-11-13 17:41:43 +00:00
|
|
|
static void si_shader_selector_key_hw_vs(struct si_context *sctx,
|
|
|
|
struct si_shader_selector *vs,
|
|
|
|
struct si_shader_key *key)
|
|
|
|
{
|
2016-11-14 08:09:51 +00:00
|
|
|
struct si_shader_selector *ps = sctx->ps_shader.cso;
|
|
|
|
|
2016-11-13 17:41:43 +00:00
|
|
|
key->opt.hw_vs.clip_disable =
|
|
|
|
sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
|
|
|
|
(vs->info.clipdist_writemask ||
|
|
|
|
vs->info.writes_clipvertex) &&
|
|
|
|
!vs->info.culldist_writemask;
|
2016-11-14 08:09:51 +00:00
|
|
|
|
|
|
|
/* Find out if PS is disabled. */
|
2016-11-15 20:15:55 +00:00
|
|
|
bool ps_disabled = true;
|
|
|
|
if (ps) {
|
|
|
|
bool ps_modifies_zs = ps->info.uses_kill ||
|
|
|
|
ps->info.writes_z ||
|
|
|
|
ps->info.writes_stencil ||
|
|
|
|
ps->info.writes_samplemask ||
|
|
|
|
si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
|
|
|
|
|
|
|
|
unsigned ps_colormask = sctx->framebuffer.colorbuf_enabled_4bit &
|
|
|
|
sctx->queued.named.blend->cb_target_mask;
|
|
|
|
if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
|
|
|
|
ps_colormask &= ps->colors_written_4bit;
|
|
|
|
|
|
|
|
ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
|
|
|
|
(!ps_colormask &&
|
|
|
|
!ps_modifies_zs &&
|
|
|
|
!ps->info.writes_memory);
|
|
|
|
}
|
2016-11-14 08:09:51 +00:00
|
|
|
|
|
|
|
/* Find out which VS outputs aren't used by the PS. */
|
|
|
|
uint64_t outputs_written = vs->outputs_written;
|
|
|
|
uint32_t outputs_written2 = vs->outputs_written2;
|
|
|
|
uint64_t inputs_read = 0;
|
|
|
|
uint32_t inputs_read2 = 0;
|
|
|
|
|
|
|
|
outputs_written &= ~0x3; /* ignore POSITION, PSIZE */
|
|
|
|
|
|
|
|
if (!ps_disabled) {
|
|
|
|
inputs_read = ps->inputs_read;
|
|
|
|
inputs_read2 = ps->inputs_read2;
|
|
|
|
}
|
|
|
|
|
|
|
|
uint64_t linked = outputs_written & inputs_read;
|
|
|
|
uint32_t linked2 = outputs_written2 & inputs_read2;
|
|
|
|
|
|
|
|
key->opt.hw_vs.kill_outputs = ~linked & outputs_written;
|
|
|
|
key->opt.hw_vs.kill_outputs2 = ~linked2 & outputs_written2;
|
2016-11-13 17:41:43 +00:00
|
|
|
}
|
|
|
|
|
2014-12-07 16:53:56 +00:00
|
|
|
/* Compute the key for the hw shader variant */
|
2015-07-21 00:58:43 +01:00
|
|
|
static inline void si_shader_selector_key(struct pipe_context *ctx,
|
2014-12-07 16:53:56 +00:00
|
|
|
struct si_shader_selector *sel,
|
2016-11-13 02:17:46 +00:00
|
|
|
struct si_shader_key *key)
|
2014-12-07 16:53:56 +00:00
|
|
|
{
|
|
|
|
struct si_context *sctx = (struct si_context *)ctx;
|
2015-02-22 14:21:59 +00:00
|
|
|
unsigned i;
|
2014-12-07 16:53:56 +00:00
|
|
|
|
2015-02-22 14:21:59 +00:00
|
|
|
memset(key, 0, sizeof(*key));
|
2014-12-07 16:53:56 +00:00
|
|
|
|
2015-02-22 14:21:59 +00:00
|
|
|
switch (sel->type) {
|
|
|
|
case PIPE_SHADER_VERTEX:
|
2016-01-26 17:46:31 +00:00
|
|
|
if (sctx->vertex_elements) {
|
|
|
|
unsigned count = MIN2(sel->info.num_inputs,
|
|
|
|
sctx->vertex_elements->count);
|
|
|
|
for (i = 0; i < count; ++i)
|
2016-11-13 02:17:46 +00:00
|
|
|
key->part.vs.prolog.instance_divisors[i] =
|
2015-02-22 14:21:59 +00:00
|
|
|
sctx->vertex_elements->elements[i].instance_divisor;
|
2016-11-02 18:07:40 +00:00
|
|
|
|
2017-02-15 23:47:48 +00:00
|
|
|
memcpy(key->mono.vs.fix_fetch,
|
|
|
|
sctx->vertex_elements->fix_fetch, count);
|
2016-01-26 17:46:31 +00:00
|
|
|
}
|
2015-10-07 00:48:18 +01:00
|
|
|
if (sctx->tes_shader.cso)
|
2016-11-13 02:17:46 +00:00
|
|
|
key->as_ls = 1;
|
2015-10-15 22:29:00 +01:00
|
|
|
else if (sctx->gs_shader.cso)
|
2016-11-13 02:17:46 +00:00
|
|
|
key->as_es = 1;
|
2016-11-13 16:30:54 +00:00
|
|
|
else {
|
2016-11-13 17:41:43 +00:00
|
|
|
si_shader_selector_key_hw_vs(sctx, sel, key);
|
|
|
|
|
2016-11-13 16:30:54 +00:00
|
|
|
if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
|
|
|
|
key->part.vs.epilog.export_prim_id = 1;
|
|
|
|
}
|
2015-02-22 14:09:35 +00:00
|
|
|
break;
|
|
|
|
case PIPE_SHADER_TESS_CTRL:
|
2016-11-13 02:17:46 +00:00
|
|
|
key->part.tcs.epilog.prim_mode =
|
2015-10-07 00:48:18 +01:00
|
|
|
sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
|
2017-02-18 15:55:50 +00:00
|
|
|
key->part.tcs.epilog.tes_reads_tess_factors =
|
|
|
|
sctx->tes_shader.cso->info.reads_tess_factors;
|
2016-05-03 20:31:00 +01:00
|
|
|
|
|
|
|
if (sel == sctx->fixed_func_tcs_shader.cso)
|
2016-11-13 02:17:46 +00:00
|
|
|
key->mono.tcs.inputs_to_copy = sctx->vs_shader.cso->outputs_written;
|
2015-02-22 14:09:35 +00:00
|
|
|
break;
|
|
|
|
case PIPE_SHADER_TESS_EVAL:
|
2015-10-15 22:29:00 +01:00
|
|
|
if (sctx->gs_shader.cso)
|
2016-11-13 02:17:46 +00:00
|
|
|
key->as_es = 1;
|
2016-11-13 17:41:43 +00:00
|
|
|
else {
|
|
|
|
si_shader_selector_key_hw_vs(sctx, sel, key);
|
|
|
|
|
|
|
|
if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
|
|
|
|
key->part.tes.epilog.export_prim_id = 1;
|
|
|
|
}
|
2015-02-22 14:21:59 +00:00
|
|
|
break;
|
|
|
|
case PIPE_SHADER_GEOMETRY:
|
2016-11-13 02:17:46 +00:00
|
|
|
key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
|
2015-02-22 14:21:59 +00:00
|
|
|
break;
|
|
|
|
case PIPE_SHADER_FRAGMENT: {
|
2015-02-28 16:22:54 +00:00
|
|
|
struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
|
2016-01-11 22:51:39 +00:00
|
|
|
struct si_state_blend *blend = sctx->queued.named.blend;
|
2015-02-28 16:22:54 +00:00
|
|
|
|
2015-12-23 15:24:02 +00:00
|
|
|
if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
|
|
|
|
sel->info.colors_written == 0x1)
|
2016-11-13 02:17:46 +00:00
|
|
|
key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
|
2015-12-23 15:24:02 +00:00
|
|
|
|
2016-01-15 13:40:19 +00:00
|
|
|
if (blend) {
|
|
|
|
/* Select the shader color format based on whether
|
|
|
|
* blending or alpha are needed.
|
|
|
|
*/
|
2016-11-13 02:17:46 +00:00
|
|
|
key->part.ps.epilog.spi_shader_col_format =
|
2016-01-15 13:40:19 +00:00
|
|
|
(blend->blend_enable_4bit & blend->need_src_alpha_4bit &
|
|
|
|
sctx->framebuffer.spi_shader_col_format_blend_alpha) |
|
|
|
|
(blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
|
|
|
|
sctx->framebuffer.spi_shader_col_format_blend) |
|
|
|
|
(~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
|
|
|
|
sctx->framebuffer.spi_shader_col_format_alpha) |
|
|
|
|
(~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
|
|
|
|
sctx->framebuffer.spi_shader_col_format);
|
2016-08-10 11:19:49 +01:00
|
|
|
|
|
|
|
/* The output for dual source blending should have
|
|
|
|
* the same format as the first output.
|
|
|
|
*/
|
|
|
|
if (blend->dual_src_blend)
|
2016-11-13 02:17:46 +00:00
|
|
|
key->part.ps.epilog.spi_shader_col_format |=
|
|
|
|
(key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
|
2016-01-15 13:40:19 +00:00
|
|
|
} else
|
2016-11-13 02:17:46 +00:00
|
|
|
key->part.ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
|
2016-01-11 22:51:39 +00:00
|
|
|
|
|
|
|
/* If alpha-to-coverage is enabled, we have to export alpha
|
|
|
|
* even if there is no color buffer.
|
|
|
|
*/
|
2016-11-13 02:17:46 +00:00
|
|
|
if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
|
2016-01-11 22:51:39 +00:00
|
|
|
blend && blend->alpha_to_coverage)
|
2016-11-13 02:17:46 +00:00
|
|
|
key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
|
2014-12-07 16:53:56 +00:00
|
|
|
|
2016-01-15 13:40:19 +00:00
|
|
|
/* On SI and CIK except Hawaii, the CB doesn't clamp outputs
|
|
|
|
* to the range supported by the type if a channel has less
|
|
|
|
* than 16 bits and the export format is 16_ABGR.
|
|
|
|
*/
|
2017-02-20 11:07:21 +00:00
|
|
|
if (sctx->b.chip_class <= CIK && sctx->b.family != CHIP_HAWAII) {
|
2016-11-13 02:17:46 +00:00
|
|
|
key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
|
2017-02-20 11:07:21 +00:00
|
|
|
key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
|
|
|
|
}
|
2016-01-15 13:40:19 +00:00
|
|
|
|
2016-01-15 20:58:53 +00:00
|
|
|
/* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
|
2016-11-13 02:17:46 +00:00
|
|
|
if (!key->part.ps.epilog.last_cbuf) {
|
|
|
|
key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
|
|
|
|
key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
|
2017-02-20 11:07:21 +00:00
|
|
|
key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
|
2016-01-15 20:58:53 +00:00
|
|
|
}
|
|
|
|
|
2015-02-28 16:22:54 +00:00
|
|
|
if (rs) {
|
2015-03-15 17:20:19 +00:00
|
|
|
bool is_poly = (sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES &&
|
|
|
|
sctx->current_rast_prim <= PIPE_PRIM_POLYGON) ||
|
|
|
|
sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY;
|
|
|
|
bool is_line = !is_poly && sctx->current_rast_prim != PIPE_PRIM_POINTS;
|
|
|
|
|
2016-11-13 02:17:46 +00:00
|
|
|
key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
|
|
|
|
key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
|
2014-12-07 16:53:56 +00:00
|
|
|
|
|
|
|
if (sctx->queued.named.blend) {
|
2016-11-13 02:17:46 +00:00
|
|
|
key->part.ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
|
2016-09-16 21:42:54 +01:00
|
|
|
rs->multisample_enable;
|
2014-12-07 16:53:56 +00:00
|
|
|
}
|
2015-01-31 20:43:37 +00:00
|
|
|
|
2016-11-13 02:17:46 +00:00
|
|
|
key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
|
|
|
|
key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
|
2016-01-26 17:46:31 +00:00
|
|
|
(is_line && rs->line_smooth)) &&
|
|
|
|
sctx->framebuffer.nr_samples <= 1;
|
2016-11-13 02:17:46 +00:00
|
|
|
key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
|
2016-01-26 17:46:31 +00:00
|
|
|
|
2016-06-30 09:50:26 +01:00
|
|
|
if (rs->force_persample_interp &&
|
|
|
|
rs->multisample_enable &&
|
|
|
|
sctx->framebuffer.nr_samples > 1 &&
|
|
|
|
sctx->ps_iter_samples > 1) {
|
2016-11-13 02:17:46 +00:00
|
|
|
key->part.ps.prolog.force_persp_sample_interp =
|
2016-06-30 09:50:26 +01:00
|
|
|
sel->info.uses_persp_center ||
|
|
|
|
sel->info.uses_persp_centroid;
|
|
|
|
|
2016-11-13 02:17:46 +00:00
|
|
|
key->part.ps.prolog.force_linear_sample_interp =
|
2016-06-30 09:50:26 +01:00
|
|
|
sel->info.uses_linear_center ||
|
|
|
|
sel->info.uses_linear_centroid;
|
2016-06-30 01:16:16 +01:00
|
|
|
} else if (rs->multisample_enable &&
|
|
|
|
sctx->framebuffer.nr_samples > 1) {
|
2016-11-13 02:17:46 +00:00
|
|
|
key->part.ps.prolog.bc_optimize_for_persp =
|
2016-06-30 01:16:16 +01:00
|
|
|
sel->info.uses_persp_center &&
|
|
|
|
sel->info.uses_persp_centroid;
|
2016-11-13 02:17:46 +00:00
|
|
|
key->part.ps.prolog.bc_optimize_for_linear =
|
2016-06-30 01:16:16 +01:00
|
|
|
sel->info.uses_linear_center &&
|
|
|
|
sel->info.uses_linear_centroid;
|
|
|
|
} else {
|
2016-06-30 09:57:34 +01:00
|
|
|
/* Make sure SPI doesn't compute more than 1 pair
|
|
|
|
* of (i,j), which is the optimization here. */
|
2016-11-13 02:17:46 +00:00
|
|
|
key->part.ps.prolog.force_persp_center_interp =
|
2016-06-30 09:57:34 +01:00
|
|
|
sel->info.uses_persp_center +
|
|
|
|
sel->info.uses_persp_centroid +
|
|
|
|
sel->info.uses_persp_sample > 1;
|
|
|
|
|
2016-11-13 02:17:46 +00:00
|
|
|
key->part.ps.prolog.force_linear_center_interp =
|
2016-06-30 09:57:34 +01:00
|
|
|
sel->info.uses_linear_center +
|
|
|
|
sel->info.uses_linear_centroid +
|
|
|
|
sel->info.uses_linear_sample > 1;
|
2016-06-30 09:50:26 +01:00
|
|
|
}
|
2014-12-07 16:53:56 +00:00
|
|
|
}
|
|
|
|
|
2016-11-13 02:17:46 +00:00
|
|
|
key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
|
2015-02-22 14:21:59 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
default:
|
|
|
|
assert(0);
|
2014-12-07 16:53:56 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-10-13 11:18:53 +01:00
|
|
|
static void si_build_shader_variant(void *job, int thread_index)
|
|
|
|
{
|
|
|
|
struct si_shader *shader = (struct si_shader *)job;
|
|
|
|
struct si_shader_selector *sel = shader->selector;
|
|
|
|
struct si_screen *sscreen = sel->screen;
|
|
|
|
LLVMTargetMachineRef tm;
|
2017-01-17 17:04:13 +00:00
|
|
|
struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
|
2016-10-13 11:18:53 +01:00
|
|
|
int r;
|
|
|
|
|
|
|
|
if (thread_index >= 0) {
|
|
|
|
assert(thread_index < ARRAY_SIZE(sscreen->tm));
|
|
|
|
tm = sscreen->tm[thread_index];
|
|
|
|
if (!debug->async)
|
|
|
|
debug = NULL;
|
|
|
|
} else {
|
2017-01-17 17:04:13 +00:00
|
|
|
tm = shader->compiler_ctx_state.tm;
|
2016-10-13 11:18:53 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
r = si_shader_create(sscreen, tm, shader, debug);
|
|
|
|
if (unlikely(r)) {
|
|
|
|
R600_ERR("Failed to build shader variant (type=%u) %d\n",
|
|
|
|
sel->type, r);
|
|
|
|
shader->compilation_failed = true;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2017-01-17 17:04:13 +00:00
|
|
|
if (shader->compiler_ctx_state.is_debug_context) {
|
2016-10-13 11:18:53 +01:00
|
|
|
FILE *f = open_memstream(&shader->shader_log,
|
|
|
|
&shader->shader_log_size);
|
|
|
|
if (f) {
|
2017-01-03 13:19:37 +00:00
|
|
|
si_shader_dump(sscreen, shader, NULL, sel->type, f, false);
|
2016-10-13 11:18:53 +01:00
|
|
|
fclose(f);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
si_shader_init_pm4_state(sscreen, shader);
|
|
|
|
}
|
|
|
|
|
2014-12-07 16:53:56 +00:00
|
|
|
/* Select the hw shader variant depending on the current state. */
|
2016-06-11 17:59:26 +01:00
|
|
|
static int si_shader_select_with_key(struct si_screen *sscreen,
|
2016-01-23 16:00:00 +00:00
|
|
|
struct si_shader_ctx_state *state,
|
2017-01-17 17:04:13 +00:00
|
|
|
struct si_compiler_ctx_state *compiler_state,
|
2016-11-13 02:17:46 +00:00
|
|
|
struct si_shader_key *key,
|
2016-10-13 11:18:53 +01:00
|
|
|
int thread_index)
|
2014-12-07 16:53:56 +00:00
|
|
|
{
|
2016-11-13 18:21:46 +00:00
|
|
|
static const struct si_shader_key zeroed;
|
2015-10-07 00:48:18 +01:00
|
|
|
struct si_shader_selector *sel = state->cso;
|
|
|
|
struct si_shader *current = state->current;
|
|
|
|
struct si_shader *iter, *shader = NULL;
|
2016-11-21 19:39:27 +00:00
|
|
|
|
2017-01-16 15:44:08 +00:00
|
|
|
if (unlikely(sscreen->b.debug_flags & DBG_NO_OPT_VARIANT)) {
|
2016-11-21 19:39:27 +00:00
|
|
|
memset(&key->opt, 0, sizeof(key->opt));
|
|
|
|
}
|
|
|
|
|
2016-10-13 11:18:53 +01:00
|
|
|
again:
|
2014-12-07 16:53:56 +00:00
|
|
|
/* Check if we don't need to change anything.
|
|
|
|
* This path is also used for most shaders that don't need multiple
|
|
|
|
* variants, it will cost just a computation of the key and this
|
|
|
|
* test. */
|
2016-10-13 11:18:53 +01:00
|
|
|
if (likely(current &&
|
|
|
|
memcmp(¤t->key, key, sizeof(*key)) == 0 &&
|
|
|
|
(!current->is_optimized ||
|
|
|
|
util_queue_fence_is_signalled(¤t->optimized_ready))))
|
2017-03-23 23:17:23 +00:00
|
|
|
return current->compilation_failed ? -1 : 0;
|
2014-12-07 16:53:56 +00:00
|
|
|
|
2016-06-11 18:57:40 +01:00
|
|
|
/* This must be done before the mutex is locked, because async GS
|
|
|
|
* compilation calls this function too, and therefore must enter
|
|
|
|
* the mutex first.
|
2016-10-13 11:18:53 +01:00
|
|
|
*
|
|
|
|
* Only wait if we are in a draw call. Don't wait if we are
|
|
|
|
* in a compiler thread.
|
2016-06-11 18:57:40 +01:00
|
|
|
*/
|
2016-10-13 11:18:53 +01:00
|
|
|
if (thread_index < 0)
|
2017-02-20 17:42:41 +00:00
|
|
|
util_queue_fence_wait(&sel->ready);
|
2016-06-11 18:57:40 +01:00
|
|
|
|
2017-03-05 01:12:30 +00:00
|
|
|
mtx_lock(&sel->mutex);
|
2014-12-07 16:53:56 +00:00
|
|
|
|
2015-10-07 00:48:18 +01:00
|
|
|
/* Find the shader variant. */
|
|
|
|
for (iter = sel->first_variant; iter; iter = iter->next_variant) {
|
|
|
|
/* Don't check the "current" shader. We checked it above. */
|
|
|
|
if (current != iter &&
|
2016-01-23 16:00:00 +00:00
|
|
|
memcmp(&iter->key, key, sizeof(*key)) == 0) {
|
2016-10-13 11:18:53 +01:00
|
|
|
/* If it's an optimized shader and its compilation has
|
|
|
|
* been started but isn't done, use the unoptimized
|
|
|
|
* shader so as not to cause a stall due to compilation.
|
|
|
|
*/
|
|
|
|
if (iter->is_optimized &&
|
|
|
|
!util_queue_fence_is_signalled(&iter->optimized_ready)) {
|
|
|
|
memset(&key->opt, 0, sizeof(key->opt));
|
2017-03-05 01:32:06 +00:00
|
|
|
mtx_unlock(&sel->mutex);
|
2016-10-13 11:18:53 +01:00
|
|
|
goto again;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (iter->compilation_failed) {
|
2017-03-05 01:32:06 +00:00
|
|
|
mtx_unlock(&sel->mutex);
|
2016-10-13 11:18:53 +01:00
|
|
|
return -1; /* skip the draw call */
|
|
|
|
}
|
|
|
|
|
2015-10-07 00:48:18 +01:00
|
|
|
state->current = iter;
|
2017-03-05 01:32:06 +00:00
|
|
|
mtx_unlock(&sel->mutex);
|
2015-10-07 00:48:18 +01:00
|
|
|
return 0;
|
2014-12-07 16:53:56 +00:00
|
|
|
}
|
2015-10-07 00:48:18 +01:00
|
|
|
}
|
2014-12-07 16:53:56 +00:00
|
|
|
|
2015-10-07 00:48:18 +01:00
|
|
|
/* Build a new shader. */
|
|
|
|
shader = CALLOC_STRUCT(si_shader);
|
|
|
|
if (!shader) {
|
2017-03-05 01:32:06 +00:00
|
|
|
mtx_unlock(&sel->mutex);
|
2015-10-07 00:48:18 +01:00
|
|
|
return -ENOMEM;
|
2014-12-07 16:53:56 +00:00
|
|
|
}
|
2015-10-07 00:48:18 +01:00
|
|
|
shader->selector = sel;
|
2016-01-23 16:00:00 +00:00
|
|
|
shader->key = *key;
|
2017-01-17 17:04:13 +00:00
|
|
|
shader->compiler_ctx_state = *compiler_state;
|
2016-10-13 11:18:53 +01:00
|
|
|
|
2017-02-14 21:08:32 +00:00
|
|
|
/* Compile the main shader part if it doesn't exist. This can happen
|
|
|
|
* if the initial guess was wrong. */
|
|
|
|
struct si_shader **mainp = si_get_main_shader_part(sel, key);
|
2017-02-14 21:06:51 +00:00
|
|
|
bool is_pure_monolithic =
|
2017-02-18 16:08:34 +00:00
|
|
|
sscreen->use_monolithic_shaders ||
|
2017-02-14 21:06:51 +00:00
|
|
|
memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
|
|
|
|
|
2017-02-14 21:08:32 +00:00
|
|
|
if (!*mainp && !is_pure_monolithic) {
|
|
|
|
struct si_shader *main_part = CALLOC_STRUCT(si_shader);
|
|
|
|
|
|
|
|
if (!main_part) {
|
|
|
|
FREE(shader);
|
2017-03-05 01:32:06 +00:00
|
|
|
mtx_unlock(&sel->mutex);
|
2017-02-14 21:08:32 +00:00
|
|
|
return -ENOMEM; /* skip the draw call */
|
|
|
|
}
|
|
|
|
|
|
|
|
main_part->selector = sel;
|
|
|
|
main_part->key.as_es = key->as_es;
|
|
|
|
main_part->key.as_ls = key->as_ls;
|
|
|
|
|
|
|
|
if (si_compile_tgsi_shader(sscreen, compiler_state->tm,
|
|
|
|
main_part, false,
|
|
|
|
&compiler_state->debug) != 0) {
|
|
|
|
FREE(main_part);
|
|
|
|
FREE(shader);
|
2017-03-05 01:32:06 +00:00
|
|
|
mtx_unlock(&sel->mutex);
|
2017-02-14 21:08:32 +00:00
|
|
|
return -ENOMEM; /* skip the draw call */
|
|
|
|
}
|
|
|
|
*mainp = main_part;
|
|
|
|
}
|
|
|
|
|
2016-10-13 11:18:53 +01:00
|
|
|
/* Monolithic-only shaders don't make a distinction between optimized
|
|
|
|
* and unoptimized. */
|
2016-11-13 18:21:46 +00:00
|
|
|
shader->is_monolithic =
|
2017-02-14 21:06:51 +00:00
|
|
|
is_pure_monolithic ||
|
|
|
|
memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
|
2015-10-07 00:48:18 +01:00
|
|
|
|
2016-10-13 11:18:53 +01:00
|
|
|
shader->is_optimized =
|
2017-02-18 16:08:34 +00:00
|
|
|
!is_pure_monolithic &&
|
2016-10-13 11:18:53 +01:00
|
|
|
memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
|
|
|
|
if (shader->is_optimized)
|
|
|
|
util_queue_fence_init(&shader->optimized_ready);
|
2014-12-07 16:53:56 +00:00
|
|
|
|
2015-10-07 00:48:18 +01:00
|
|
|
if (!sel->last_variant) {
|
|
|
|
sel->first_variant = shader;
|
|
|
|
sel->last_variant = shader;
|
2014-12-07 16:53:56 +00:00
|
|
|
} else {
|
2015-10-07 00:48:18 +01:00
|
|
|
sel->last_variant->next_variant = shader;
|
|
|
|
sel->last_variant = shader;
|
2014-12-07 16:53:56 +00:00
|
|
|
}
|
2016-10-13 11:18:53 +01:00
|
|
|
|
|
|
|
/* If it's an optimized shader, compile it asynchronously. */
|
|
|
|
if (shader->is_optimized &&
|
2017-02-14 21:06:51 +00:00
|
|
|
!is_pure_monolithic &&
|
2016-10-13 11:18:53 +01:00
|
|
|
thread_index < 0) {
|
|
|
|
/* Compile it asynchronously. */
|
|
|
|
util_queue_add_job(&sscreen->shader_compiler_queue,
|
|
|
|
shader, &shader->optimized_ready,
|
|
|
|
si_build_shader_variant, NULL);
|
|
|
|
|
|
|
|
/* Use the default (unoptimized) shader for now. */
|
|
|
|
memset(&key->opt, 0, sizeof(key->opt));
|
2017-03-05 01:32:06 +00:00
|
|
|
mtx_unlock(&sel->mutex);
|
2016-10-13 11:18:53 +01:00
|
|
|
goto again;
|
|
|
|
}
|
|
|
|
|
|
|
|
assert(!shader->is_optimized);
|
|
|
|
si_build_shader_variant(shader, thread_index);
|
|
|
|
|
|
|
|
if (!shader->compilation_failed)
|
|
|
|
state->current = shader;
|
|
|
|
|
2017-03-05 01:32:06 +00:00
|
|
|
mtx_unlock(&sel->mutex);
|
2016-10-13 11:18:53 +01:00
|
|
|
return shader->compilation_failed ? -1 : 0;
|
2014-12-07 16:53:56 +00:00
|
|
|
}
|
|
|
|
|
2016-01-23 16:00:00 +00:00
|
|
|
static int si_shader_select(struct pipe_context *ctx,
|
2017-01-17 17:04:13 +00:00
|
|
|
struct si_shader_ctx_state *state,
|
|
|
|
struct si_compiler_ctx_state *compiler_state)
|
2016-01-23 16:00:00 +00:00
|
|
|
{
|
2016-06-11 17:59:26 +01:00
|
|
|
struct si_context *sctx = (struct si_context *)ctx;
|
2016-11-13 02:17:46 +00:00
|
|
|
struct si_shader_key key;
|
2016-01-23 16:00:00 +00:00
|
|
|
|
|
|
|
si_shader_selector_key(ctx, state->cso, &key);
|
2017-01-17 17:04:13 +00:00
|
|
|
return si_shader_select_with_key(sctx->screen, state, compiler_state,
|
|
|
|
&key, -1);
|
2016-01-23 16:00:00 +00:00
|
|
|
}
|
|
|
|
|
2016-03-10 12:29:12 +00:00
|
|
|
static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
|
2016-11-13 02:17:46 +00:00
|
|
|
struct si_shader_key *key)
|
2016-03-10 12:29:12 +00:00
|
|
|
{
|
|
|
|
unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
|
|
|
|
|
|
|
|
switch (info->processor) {
|
2016-04-16 13:41:57 +01:00
|
|
|
case PIPE_SHADER_VERTEX:
|
2016-03-10 12:29:12 +00:00
|
|
|
switch (next_shader) {
|
2016-04-16 13:41:57 +01:00
|
|
|
case PIPE_SHADER_GEOMETRY:
|
2016-11-13 02:17:46 +00:00
|
|
|
key->as_es = 1;
|
2016-03-10 12:29:12 +00:00
|
|
|
break;
|
2016-04-16 13:41:57 +01:00
|
|
|
case PIPE_SHADER_TESS_CTRL:
|
|
|
|
case PIPE_SHADER_TESS_EVAL:
|
2016-11-13 02:17:46 +00:00
|
|
|
key->as_ls = 1;
|
2016-03-10 12:29:12 +00:00
|
|
|
break;
|
2016-11-14 01:03:28 +00:00
|
|
|
default:
|
|
|
|
/* If POSITION isn't written, it can't be a HW VS.
|
|
|
|
* Assume that it's a HW LS. (the next shader is TCS)
|
|
|
|
* This heuristic is needed for separate shader objects.
|
|
|
|
*/
|
|
|
|
if (!info->writes_position)
|
|
|
|
key->as_ls = 1;
|
2016-03-10 12:29:12 +00:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
2016-04-16 13:41:57 +01:00
|
|
|
case PIPE_SHADER_TESS_EVAL:
|
2016-12-21 14:16:54 +00:00
|
|
|
if (next_shader == PIPE_SHADER_GEOMETRY ||
|
|
|
|
!info->writes_position)
|
2016-11-13 02:17:46 +00:00
|
|
|
key->as_es = 1;
|
2016-03-10 12:29:12 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-06-11 17:59:26 +01:00
|
|
|
/**
|
|
|
|
* Compile the main shader part or the monolithic shader as part of
|
|
|
|
* si_shader_selector initialization. Since it can be done asynchronously,
|
|
|
|
* there is no way to report compile failures to applications.
|
|
|
|
*/
|
|
|
|
void si_init_shader_selector_async(void *job, int thread_index)
|
|
|
|
{
|
|
|
|
struct si_shader_selector *sel = (struct si_shader_selector *)job;
|
|
|
|
struct si_screen *sscreen = sel->screen;
|
2016-06-11 18:57:40 +01:00
|
|
|
LLVMTargetMachineRef tm;
|
2017-01-17 16:39:16 +00:00
|
|
|
struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
|
2016-06-11 17:59:26 +01:00
|
|
|
unsigned i;
|
|
|
|
|
2016-06-11 18:57:40 +01:00
|
|
|
if (thread_index >= 0) {
|
|
|
|
assert(thread_index < ARRAY_SIZE(sscreen->tm));
|
|
|
|
tm = sscreen->tm[thread_index];
|
2016-07-07 08:28:25 +01:00
|
|
|
if (!debug->async)
|
|
|
|
debug = NULL;
|
2016-06-11 18:57:40 +01:00
|
|
|
} else {
|
2017-01-17 16:39:16 +00:00
|
|
|
tm = sel->compiler_ctx_state.tm;
|
2016-06-11 18:57:40 +01:00
|
|
|
}
|
|
|
|
|
2016-06-11 17:59:26 +01:00
|
|
|
/* Compile the main shader part for use with a prolog and/or epilog.
|
|
|
|
* If this fails, the driver will try to compile a monolithic shader
|
|
|
|
* on demand.
|
|
|
|
*/
|
2016-10-31 11:50:09 +00:00
|
|
|
if (!sscreen->use_monolithic_shaders) {
|
2016-06-11 17:59:26 +01:00
|
|
|
struct si_shader *shader = CALLOC_STRUCT(si_shader);
|
|
|
|
void *tgsi_binary;
|
|
|
|
|
|
|
|
if (!shader) {
|
|
|
|
fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
shader->selector = sel;
|
|
|
|
si_parse_next_shader_property(&sel->info, &shader->key);
|
|
|
|
|
|
|
|
tgsi_binary = si_get_tgsi_binary(sel);
|
|
|
|
|
|
|
|
/* Try to load the shader from the shader cache. */
|
2017-03-05 01:12:30 +00:00
|
|
|
mtx_lock(&sscreen->shader_cache_mutex);
|
2016-06-11 17:59:26 +01:00
|
|
|
|
|
|
|
if (tgsi_binary &&
|
|
|
|
si_shader_cache_load_shader(sscreen, tgsi_binary, shader)) {
|
2017-03-05 01:32:06 +00:00
|
|
|
mtx_unlock(&sscreen->shader_cache_mutex);
|
2016-06-11 17:59:26 +01:00
|
|
|
} else {
|
2017-03-05 01:32:06 +00:00
|
|
|
mtx_unlock(&sscreen->shader_cache_mutex);
|
2016-06-11 18:32:53 +01:00
|
|
|
|
2016-06-11 17:59:26 +01:00
|
|
|
/* Compile the shader if it hasn't been loaded from the cache. */
|
|
|
|
if (si_compile_tgsi_shader(sscreen, tm, shader, false,
|
|
|
|
debug) != 0) {
|
|
|
|
FREE(shader);
|
|
|
|
FREE(tgsi_binary);
|
|
|
|
fprintf(stderr, "radeonsi: can't compile a main shader part\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2016-06-11 18:32:53 +01:00
|
|
|
if (tgsi_binary) {
|
2017-03-05 01:12:30 +00:00
|
|
|
mtx_lock(&sscreen->shader_cache_mutex);
|
2017-01-24 16:08:22 +00:00
|
|
|
if (!si_shader_cache_insert_shader(sscreen, tgsi_binary, shader, true))
|
2016-06-11 18:32:53 +01:00
|
|
|
FREE(tgsi_binary);
|
2017-03-05 01:32:06 +00:00
|
|
|
mtx_unlock(&sscreen->shader_cache_mutex);
|
2016-06-11 18:32:53 +01:00
|
|
|
}
|
2016-06-11 17:59:26 +01:00
|
|
|
}
|
|
|
|
|
2017-02-14 21:08:32 +00:00
|
|
|
*si_get_main_shader_part(sel, &shader->key) = shader;
|
2016-11-14 06:56:57 +00:00
|
|
|
|
|
|
|
/* Unset "outputs_written" flags for outputs converted to
|
|
|
|
* DEFAULT_VAL, so that later inter-shader optimizations don't
|
|
|
|
* try to eliminate outputs that don't exist in the final
|
|
|
|
* shader.
|
|
|
|
*
|
|
|
|
* This is only done if non-monolithic shaders are enabled.
|
|
|
|
*/
|
|
|
|
if ((sel->type == PIPE_SHADER_VERTEX ||
|
|
|
|
sel->type == PIPE_SHADER_TESS_EVAL) &&
|
|
|
|
!shader->key.as_ls &&
|
|
|
|
!shader->key.as_es) {
|
|
|
|
unsigned i;
|
|
|
|
|
|
|
|
for (i = 0; i < sel->info.num_outputs; i++) {
|
|
|
|
unsigned offset = shader->info.vs_output_param_offset[i];
|
|
|
|
|
|
|
|
if (offset <= EXP_PARAM_OFFSET_31)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
unsigned name = sel->info.output_semantic_name[i];
|
|
|
|
unsigned index = sel->info.output_semantic_index[i];
|
|
|
|
unsigned id;
|
|
|
|
|
|
|
|
switch (name) {
|
|
|
|
case TGSI_SEMANTIC_GENERIC:
|
|
|
|
/* don't process indices the function can't handle */
|
|
|
|
if (index >= 60)
|
|
|
|
break;
|
|
|
|
/* fall through */
|
|
|
|
case TGSI_SEMANTIC_CLIPDIST:
|
|
|
|
id = si_shader_io_get_unique_index(name, index);
|
|
|
|
sel->outputs_written &= ~(1ull << id);
|
|
|
|
break;
|
|
|
|
case TGSI_SEMANTIC_POSITION: /* ignore these */
|
|
|
|
case TGSI_SEMANTIC_PSIZE:
|
|
|
|
case TGSI_SEMANTIC_CLIPVERTEX:
|
|
|
|
case TGSI_SEMANTIC_EDGEFLAG:
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
id = si_shader_io_get_unique_index2(name, index);
|
|
|
|
sel->outputs_written2 &= ~(1u << id);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2016-06-11 17:59:26 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Pre-compilation. */
|
2016-10-31 11:50:09 +00:00
|
|
|
if (sscreen->b.debug_flags & DBG_PRECOMPILE) {
|
2016-06-11 17:59:26 +01:00
|
|
|
struct si_shader_ctx_state state = {sel};
|
2016-11-13 02:17:46 +00:00
|
|
|
struct si_shader_key key;
|
2016-06-11 17:59:26 +01:00
|
|
|
|
|
|
|
memset(&key, 0, sizeof(key));
|
|
|
|
si_parse_next_shader_property(&sel->info, &key);
|
|
|
|
|
|
|
|
/* Set reasonable defaults, so that the shader key doesn't
|
|
|
|
* cause any code to be eliminated.
|
|
|
|
*/
|
|
|
|
switch (sel->type) {
|
|
|
|
case PIPE_SHADER_TESS_CTRL:
|
2016-11-13 02:17:46 +00:00
|
|
|
key.part.tcs.epilog.prim_mode = PIPE_PRIM_TRIANGLES;
|
2016-06-11 17:59:26 +01:00
|
|
|
break;
|
|
|
|
case PIPE_SHADER_FRAGMENT:
|
2016-11-13 02:17:46 +00:00
|
|
|
key.part.ps.prolog.bc_optimize_for_persp =
|
2016-10-11 15:55:41 +01:00
|
|
|
sel->info.uses_persp_center &&
|
|
|
|
sel->info.uses_persp_centroid;
|
2016-11-13 02:17:46 +00:00
|
|
|
key.part.ps.prolog.bc_optimize_for_linear =
|
2016-10-11 15:55:41 +01:00
|
|
|
sel->info.uses_linear_center &&
|
|
|
|
sel->info.uses_linear_centroid;
|
2016-11-13 02:17:46 +00:00
|
|
|
key.part.ps.epilog.alpha_func = PIPE_FUNC_ALWAYS;
|
2016-06-11 17:59:26 +01:00
|
|
|
for (i = 0; i < 8; i++)
|
|
|
|
if (sel->info.colors_written & (1 << i))
|
2016-11-13 02:17:46 +00:00
|
|
|
key.part.ps.epilog.spi_shader_col_format |=
|
2016-06-11 17:59:26 +01:00
|
|
|
V_028710_SPI_SHADER_FP16_ABGR << (i * 4);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2017-01-17 17:04:13 +00:00
|
|
|
if (si_shader_select_with_key(sscreen, &state,
|
|
|
|
&sel->compiler_ctx_state, &key,
|
|
|
|
thread_index))
|
2016-06-11 17:59:26 +01:00
|
|
|
fprintf(stderr, "radeonsi: can't create a monolithic shader\n");
|
|
|
|
}
|
2016-10-31 20:10:37 +00:00
|
|
|
|
|
|
|
/* The GS copy shader is always pre-compiled. */
|
|
|
|
if (sel->type == PIPE_SHADER_GEOMETRY) {
|
|
|
|
sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, tm, sel, debug);
|
|
|
|
if (!sel->gs_copy_shader) {
|
|
|
|
fprintf(stderr, "radeonsi: can't create GS copy shader\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
si_shader_vs(sscreen, sel->gs_copy_shader, sel);
|
|
|
|
}
|
2016-06-11 17:59:26 +01:00
|
|
|
}
|
|
|
|
|
2015-10-09 00:14:12 +01:00
|
|
|
static void *si_create_shader_selector(struct pipe_context *ctx,
|
|
|
|
const struct pipe_shader_state *state)
|
2014-12-07 16:53:56 +00:00
|
|
|
{
|
2015-04-10 22:58:34 +01:00
|
|
|
struct si_screen *sscreen = (struct si_screen *)ctx->screen;
|
2016-01-28 01:53:13 +00:00
|
|
|
struct si_context *sctx = (struct si_context*)ctx;
|
2014-12-07 16:53:56 +00:00
|
|
|
struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
|
|
|
|
int i;
|
|
|
|
|
2015-09-10 17:16:26 +01:00
|
|
|
if (!sel)
|
|
|
|
return NULL;
|
|
|
|
|
2016-06-11 17:59:26 +01:00
|
|
|
sel->screen = sscreen;
|
2017-01-17 16:39:16 +00:00
|
|
|
sel->compiler_ctx_state.tm = sctx->tm;
|
|
|
|
sel->compiler_ctx_state.debug = sctx->b.debug;
|
|
|
|
sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
|
2014-12-07 16:53:56 +00:00
|
|
|
sel->tokens = tgsi_dup_tokens(state->tokens);
|
2015-09-10 17:16:26 +01:00
|
|
|
if (!sel->tokens) {
|
|
|
|
FREE(sel);
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2014-12-07 16:53:56 +00:00
|
|
|
sel->so = state->stream_output;
|
|
|
|
tgsi_scan_shader(state->tokens, &sel->info);
|
2016-04-16 13:48:34 +01:00
|
|
|
sel->type = sel->info.processor;
|
2015-08-02 20:12:18 +01:00
|
|
|
p_atomic_inc(&sscreen->b.num_shaders_created);
|
2014-12-07 16:53:56 +00:00
|
|
|
|
2016-01-03 18:00:29 +00:00
|
|
|
/* Set which opcode uses which (i,j) pair. */
|
2015-09-28 22:46:04 +01:00
|
|
|
if (sel->info.uses_persp_opcode_interp_centroid)
|
|
|
|
sel->info.uses_persp_centroid = true;
|
|
|
|
|
|
|
|
if (sel->info.uses_linear_opcode_interp_centroid)
|
|
|
|
sel->info.uses_linear_centroid = true;
|
|
|
|
|
|
|
|
if (sel->info.uses_persp_opcode_interp_offset ||
|
|
|
|
sel->info.uses_persp_opcode_interp_sample)
|
|
|
|
sel->info.uses_persp_center = true;
|
|
|
|
|
|
|
|
if (sel->info.uses_linear_opcode_interp_offset ||
|
|
|
|
sel->info.uses_linear_opcode_interp_sample)
|
|
|
|
sel->info.uses_linear_center = true;
|
|
|
|
|
2015-10-09 00:14:12 +01:00
|
|
|
switch (sel->type) {
|
2014-12-07 16:53:56 +00:00
|
|
|
case PIPE_SHADER_GEOMETRY:
|
|
|
|
sel->gs_output_prim =
|
|
|
|
sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
|
|
|
|
sel->gs_max_out_vertices =
|
|
|
|
sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
|
2015-06-25 03:55:54 +01:00
|
|
|
sel->gs_num_invocations =
|
|
|
|
sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
|
2015-11-08 10:49:33 +00:00
|
|
|
sel->gsvs_vertex_size = sel->info.num_outputs * 16;
|
|
|
|
sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
|
|
|
|
sel->gs_max_out_vertices;
|
2014-12-07 16:53:56 +00:00
|
|
|
|
2015-11-08 11:05:39 +00:00
|
|
|
sel->max_gs_stream = 0;
|
|
|
|
for (i = 0; i < sel->so.num_outputs; i++)
|
|
|
|
sel->max_gs_stream = MAX2(sel->max_gs_stream,
|
|
|
|
sel->so.output[i].stream);
|
|
|
|
|
2015-11-08 12:34:44 +00:00
|
|
|
sel->gs_input_verts_per_prim =
|
|
|
|
u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
|
2015-02-22 14:09:35 +00:00
|
|
|
break;
|
|
|
|
|
|
|
|
case PIPE_SHADER_TESS_CTRL:
|
2016-05-27 11:39:30 +01:00
|
|
|
/* Always reserve space for these. */
|
|
|
|
sel->patch_outputs_written |=
|
|
|
|
(1llu << si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0)) |
|
|
|
|
(1llu << si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0));
|
|
|
|
/* fall through */
|
|
|
|
case PIPE_SHADER_VERTEX:
|
2015-11-08 12:34:44 +00:00
|
|
|
case PIPE_SHADER_TESS_EVAL:
|
2015-02-22 14:09:35 +00:00
|
|
|
for (i = 0; i < sel->info.num_outputs; i++) {
|
|
|
|
unsigned name = sel->info.output_semantic_name[i];
|
|
|
|
unsigned index = sel->info.output_semantic_index[i];
|
|
|
|
|
|
|
|
switch (name) {
|
|
|
|
case TGSI_SEMANTIC_TESSINNER:
|
|
|
|
case TGSI_SEMANTIC_TESSOUTER:
|
|
|
|
case TGSI_SEMANTIC_PATCH:
|
|
|
|
sel->patch_outputs_written |=
|
|
|
|
1llu << si_shader_io_get_unique_index(name, index);
|
|
|
|
break;
|
2016-11-13 18:54:13 +00:00
|
|
|
|
|
|
|
case TGSI_SEMANTIC_GENERIC:
|
|
|
|
/* don't process indices the function can't handle */
|
|
|
|
if (index >= 60)
|
|
|
|
break;
|
|
|
|
/* fall through */
|
|
|
|
case TGSI_SEMANTIC_POSITION:
|
|
|
|
case TGSI_SEMANTIC_PSIZE:
|
|
|
|
case TGSI_SEMANTIC_CLIPDIST:
|
2015-02-22 14:09:35 +00:00
|
|
|
sel->outputs_written |=
|
|
|
|
1llu << si_shader_io_get_unique_index(name, index);
|
2016-11-13 18:54:13 +00:00
|
|
|
break;
|
2016-11-14 06:56:57 +00:00
|
|
|
case TGSI_SEMANTIC_CLIPVERTEX: /* ignore these */
|
|
|
|
case TGSI_SEMANTIC_EDGEFLAG:
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
sel->outputs_written2 |=
|
|
|
|
1u << si_shader_io_get_unique_index2(name, index);
|
2015-02-22 14:09:35 +00:00
|
|
|
}
|
|
|
|
}
|
2015-11-08 11:12:46 +00:00
|
|
|
sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
|
2015-02-22 14:09:35 +00:00
|
|
|
break;
|
2016-01-15 20:58:53 +00:00
|
|
|
|
|
|
|
case PIPE_SHADER_FRAGMENT:
|
2016-11-14 06:56:57 +00:00
|
|
|
for (i = 0; i < sel->info.num_inputs; i++) {
|
|
|
|
unsigned name = sel->info.input_semantic_name[i];
|
|
|
|
unsigned index = sel->info.input_semantic_index[i];
|
|
|
|
|
|
|
|
switch (name) {
|
|
|
|
case TGSI_SEMANTIC_CLIPDIST:
|
|
|
|
case TGSI_SEMANTIC_GENERIC:
|
|
|
|
sel->inputs_read |=
|
|
|
|
1llu << si_shader_io_get_unique_index(name, index);
|
|
|
|
break;
|
|
|
|
case TGSI_SEMANTIC_PCOORD: /* ignore this */
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
sel->inputs_read2 |=
|
|
|
|
1u << si_shader_io_get_unique_index2(name, index);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-01-15 20:58:53 +00:00
|
|
|
for (i = 0; i < 8; i++)
|
|
|
|
if (sel->info.colors_written & (1 << i))
|
|
|
|
sel->colors_written_4bit |= 0xf << (4 * i);
|
2016-02-15 22:57:54 +00:00
|
|
|
|
|
|
|
for (i = 0; i < sel->info.num_inputs; i++) {
|
|
|
|
if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
|
|
|
|
int index = sel->info.input_semantic_index[i];
|
|
|
|
sel->color_attr_index[index] = i;
|
|
|
|
}
|
|
|
|
}
|
2016-01-15 20:58:53 +00:00
|
|
|
break;
|
2014-12-07 16:53:56 +00:00
|
|
|
}
|
|
|
|
|
2015-12-23 14:36:05 +00:00
|
|
|
/* DB_SHADER_CONTROL */
|
|
|
|
sel->db_shader_control =
|
|
|
|
S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
|
|
|
|
S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
|
|
|
|
S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
|
|
|
|
S_02880C_KILL_ENABLE(sel->info.uses_kill);
|
|
|
|
|
|
|
|
switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
|
|
|
|
case TGSI_FS_DEPTH_LAYOUT_GREATER:
|
|
|
|
sel->db_shader_control |=
|
|
|
|
S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
|
|
|
|
break;
|
|
|
|
case TGSI_FS_DEPTH_LAYOUT_LESS:
|
|
|
|
sel->db_shader_control |=
|
|
|
|
S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2016-10-12 21:15:31 +01:00
|
|
|
/* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
|
|
|
|
*
|
|
|
|
* | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
|
|
|
|
* --|-----------|------------|------------|--------------------|-------------------|-------------
|
|
|
|
* 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
|
|
|
|
* 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
|
|
|
|
* 2 | false | true | n/a | LateZ | 1 | 0
|
|
|
|
* 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
|
|
|
|
* 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
|
|
|
|
*
|
|
|
|
* In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
|
|
|
|
* In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
|
|
|
|
*
|
|
|
|
* Don't use ReZ without profiling !!!
|
|
|
|
*
|
|
|
|
* ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
|
|
|
|
* shaders.
|
|
|
|
*/
|
|
|
|
if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
|
|
|
|
/* Cases 3, 4. */
|
|
|
|
sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
|
|
|
|
S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
|
|
|
|
S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
|
|
|
|
} else if (sel->info.writes_memory) {
|
|
|
|
/* Case 2. */
|
|
|
|
sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
|
|
|
|
S_02880C_EXEC_ON_HIER_FAIL(1);
|
|
|
|
} else {
|
|
|
|
/* Case 1. */
|
|
|
|
sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
|
|
|
|
}
|
2016-03-11 23:20:00 +00:00
|
|
|
|
2017-03-05 01:00:15 +00:00
|
|
|
(void) mtx_init(&sel->mutex, mtx_plain);
|
2016-06-11 18:57:40 +01:00
|
|
|
util_queue_fence_init(&sel->ready);
|
2016-03-16 01:58:12 +00:00
|
|
|
|
2016-07-07 08:28:25 +01:00
|
|
|
if ((sctx->b.debug.debug_message && !sctx->b.debug.async) ||
|
2016-07-22 22:40:45 +01:00
|
|
|
sctx->is_debug ||
|
2017-03-02 23:24:03 +00:00
|
|
|
r600_can_dump_shader(&sscreen->b, sel->info.processor))
|
2016-06-11 18:57:40 +01:00
|
|
|
si_init_shader_selector_async(sel, -1);
|
|
|
|
else
|
|
|
|
util_queue_add_job(&sscreen->shader_compiler_queue, sel,
|
2016-07-13 17:17:05 +01:00
|
|
|
&sel->ready, si_init_shader_selector_async,
|
|
|
|
NULL);
|
2015-04-10 22:58:34 +01:00
|
|
|
|
2014-12-07 16:53:56 +00:00
|
|
|
return sel;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
|
|
|
|
{
|
|
|
|
struct si_context *sctx = (struct si_context *)ctx;
|
|
|
|
struct si_shader_selector *sel = state;
|
|
|
|
|
2015-10-22 20:32:23 +01:00
|
|
|
if (sctx->vs_shader.cso == sel)
|
2014-12-07 16:53:56 +00:00
|
|
|
return;
|
|
|
|
|
2015-10-07 00:48:18 +01:00
|
|
|
sctx->vs_shader.cso = sel;
|
2015-10-22 20:32:23 +01:00
|
|
|
sctx->vs_shader.current = sel ? sel->first_variant : NULL;
|
2016-08-02 10:51:21 +01:00
|
|
|
sctx->do_update_shaders = true;
|
2015-08-09 22:42:32 +01:00
|
|
|
si_mark_atom_dirty(sctx, &sctx->clip_regs);
|
2016-04-10 03:26:50 +01:00
|
|
|
r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
|
2014-12-07 16:53:56 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
|
|
|
|
{
|
|
|
|
struct si_context *sctx = (struct si_context *)ctx;
|
|
|
|
struct si_shader_selector *sel = state;
|
2015-10-07 00:48:18 +01:00
|
|
|
bool enable_changed = !!sctx->gs_shader.cso != !!sel;
|
2014-12-07 16:53:56 +00:00
|
|
|
|
2015-10-07 00:48:18 +01:00
|
|
|
if (sctx->gs_shader.cso == sel)
|
2014-12-07 16:53:56 +00:00
|
|
|
return;
|
|
|
|
|
2015-10-07 00:48:18 +01:00
|
|
|
sctx->gs_shader.cso = sel;
|
|
|
|
sctx->gs_shader.current = sel ? sel->first_variant : NULL;
|
2017-01-25 01:47:15 +00:00
|
|
|
sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
|
2016-08-02 10:51:21 +01:00
|
|
|
sctx->do_update_shaders = true;
|
2015-08-09 22:42:32 +01:00
|
|
|
si_mark_atom_dirty(sctx, &sctx->clip_regs);
|
2014-12-08 12:35:36 +00:00
|
|
|
sctx->last_rast_prim = -1; /* reset this so that it gets updated */
|
2014-09-15 22:34:28 +01:00
|
|
|
|
|
|
|
if (enable_changed)
|
|
|
|
si_shader_change_notify(sctx);
|
2016-04-10 03:26:50 +01:00
|
|
|
r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
|
2014-12-07 16:53:56 +00:00
|
|
|
}
|
|
|
|
|
2017-01-25 01:47:15 +00:00
|
|
|
static void si_update_tcs_tes_uses_prim_id(struct si_context *sctx)
|
|
|
|
{
|
|
|
|
sctx->ia_multi_vgt_param_key.u.tcs_tes_uses_prim_id =
|
|
|
|
(sctx->tes_shader.cso &&
|
|
|
|
sctx->tes_shader.cso->info.uses_primid) ||
|
|
|
|
(sctx->tcs_shader.cso &&
|
|
|
|
sctx->tcs_shader.cso->info.uses_primid);
|
|
|
|
}
|
|
|
|
|
2014-09-18 21:50:52 +01:00
|
|
|
static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
|
|
|
|
{
|
|
|
|
struct si_context *sctx = (struct si_context *)ctx;
|
|
|
|
struct si_shader_selector *sel = state;
|
2015-10-07 00:48:18 +01:00
|
|
|
bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
|
2014-09-18 21:50:52 +01:00
|
|
|
|
2015-10-07 00:48:18 +01:00
|
|
|
if (sctx->tcs_shader.cso == sel)
|
2014-09-18 21:50:52 +01:00
|
|
|
return;
|
|
|
|
|
2015-10-07 00:48:18 +01:00
|
|
|
sctx->tcs_shader.cso = sel;
|
|
|
|
sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
|
2017-01-25 01:47:15 +00:00
|
|
|
si_update_tcs_tes_uses_prim_id(sctx);
|
2016-08-02 10:51:21 +01:00
|
|
|
sctx->do_update_shaders = true;
|
2015-02-22 17:01:18 +00:00
|
|
|
|
|
|
|
if (enable_changed)
|
|
|
|
sctx->last_tcs = NULL; /* invalidate derived tess state */
|
2014-09-18 21:50:52 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
|
|
|
|
{
|
|
|
|
struct si_context *sctx = (struct si_context *)ctx;
|
|
|
|
struct si_shader_selector *sel = state;
|
2015-10-07 00:48:18 +01:00
|
|
|
bool enable_changed = !!sctx->tes_shader.cso != !!sel;
|
2014-09-18 21:50:52 +01:00
|
|
|
|
2015-10-07 00:48:18 +01:00
|
|
|
if (sctx->tes_shader.cso == sel)
|
2014-09-18 21:50:52 +01:00
|
|
|
return;
|
|
|
|
|
2015-10-07 00:48:18 +01:00
|
|
|
sctx->tes_shader.cso = sel;
|
|
|
|
sctx->tes_shader.current = sel ? sel->first_variant : NULL;
|
2017-01-25 01:47:15 +00:00
|
|
|
sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
|
|
|
|
si_update_tcs_tes_uses_prim_id(sctx);
|
2016-08-02 10:51:21 +01:00
|
|
|
sctx->do_update_shaders = true;
|
2015-08-09 22:42:32 +01:00
|
|
|
si_mark_atom_dirty(sctx, &sctx->clip_regs);
|
2014-09-18 21:50:52 +01:00
|
|
|
sctx->last_rast_prim = -1; /* reset this so that it gets updated */
|
|
|
|
|
2015-02-22 17:01:18 +00:00
|
|
|
if (enable_changed) {
|
2014-09-18 21:50:52 +01:00
|
|
|
si_shader_change_notify(sctx);
|
2015-02-22 17:01:18 +00:00
|
|
|
sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
|
|
|
|
}
|
2016-04-10 03:26:50 +01:00
|
|
|
r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
|
2014-09-18 21:50:52 +01:00
|
|
|
}
|
|
|
|
|
2014-12-07 16:53:56 +00:00
|
|
|
static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
|
|
|
|
{
|
|
|
|
struct si_context *sctx = (struct si_context *)ctx;
|
|
|
|
struct si_shader_selector *sel = state;
|
|
|
|
|
|
|
|
/* skip if supplied shader is one already in use */
|
2015-10-07 00:48:18 +01:00
|
|
|
if (sctx->ps_shader.cso == sel)
|
2014-12-07 16:53:56 +00:00
|
|
|
return;
|
|
|
|
|
2015-10-07 00:48:18 +01:00
|
|
|
sctx->ps_shader.cso = sel;
|
2015-10-22 21:19:34 +01:00
|
|
|
sctx->ps_shader.current = sel ? sel->first_variant : NULL;
|
2016-08-02 10:51:21 +01:00
|
|
|
sctx->do_update_shaders = true;
|
2015-12-23 14:51:25 +00:00
|
|
|
si_mark_atom_dirty(sctx, &sctx->cb_render_state);
|
2014-12-07 16:53:56 +00:00
|
|
|
}
|
|
|
|
|
2016-01-28 00:29:25 +00:00
|
|
|
static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
|
|
|
|
{
|
2016-10-13 11:18:53 +01:00
|
|
|
if (shader->is_optimized) {
|
2017-02-20 17:42:41 +00:00
|
|
|
util_queue_fence_wait(&shader->optimized_ready);
|
2016-10-13 11:18:53 +01:00
|
|
|
util_queue_fence_destroy(&shader->optimized_ready);
|
|
|
|
}
|
|
|
|
|
2016-01-28 00:29:25 +00:00
|
|
|
if (shader->pm4) {
|
|
|
|
switch (shader->selector->type) {
|
|
|
|
case PIPE_SHADER_VERTEX:
|
2016-11-13 02:17:46 +00:00
|
|
|
if (shader->key.as_ls)
|
2016-01-28 00:29:25 +00:00
|
|
|
si_pm4_delete_state(sctx, ls, shader->pm4);
|
2016-11-13 02:17:46 +00:00
|
|
|
else if (shader->key.as_es)
|
2016-01-28 00:29:25 +00:00
|
|
|
si_pm4_delete_state(sctx, es, shader->pm4);
|
|
|
|
else
|
|
|
|
si_pm4_delete_state(sctx, vs, shader->pm4);
|
|
|
|
break;
|
|
|
|
case PIPE_SHADER_TESS_CTRL:
|
|
|
|
si_pm4_delete_state(sctx, hs, shader->pm4);
|
|
|
|
break;
|
|
|
|
case PIPE_SHADER_TESS_EVAL:
|
2016-11-13 02:17:46 +00:00
|
|
|
if (shader->key.as_es)
|
2016-01-28 00:29:25 +00:00
|
|
|
si_pm4_delete_state(sctx, es, shader->pm4);
|
|
|
|
else
|
|
|
|
si_pm4_delete_state(sctx, vs, shader->pm4);
|
|
|
|
break;
|
|
|
|
case PIPE_SHADER_GEOMETRY:
|
2016-10-31 20:10:37 +00:00
|
|
|
if (shader->is_gs_copy_shader)
|
|
|
|
si_pm4_delete_state(sctx, vs, shader->pm4);
|
|
|
|
else
|
|
|
|
si_pm4_delete_state(sctx, gs, shader->pm4);
|
2016-01-28 00:29:25 +00:00
|
|
|
break;
|
|
|
|
case PIPE_SHADER_FRAGMENT:
|
|
|
|
si_pm4_delete_state(sctx, ps, shader->pm4);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
si_shader_destroy(shader);
|
|
|
|
free(shader);
|
|
|
|
}
|
|
|
|
|
2015-10-09 00:08:42 +01:00
|
|
|
static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
|
2014-12-07 16:53:56 +00:00
|
|
|
{
|
|
|
|
struct si_context *sctx = (struct si_context *)ctx;
|
2015-10-09 00:08:42 +01:00
|
|
|
struct si_shader_selector *sel = (struct si_shader_selector *)state;
|
2015-10-07 00:48:18 +01:00
|
|
|
struct si_shader *p = sel->first_variant, *c;
|
|
|
|
struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
|
2015-10-09 00:08:42 +01:00
|
|
|
[PIPE_SHADER_VERTEX] = &sctx->vs_shader,
|
|
|
|
[PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
|
|
|
|
[PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
|
|
|
|
[PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
|
|
|
|
[PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
|
|
|
|
};
|
|
|
|
|
2017-02-20 17:42:41 +00:00
|
|
|
util_queue_fence_wait(&sel->ready);
|
2016-06-11 18:57:40 +01:00
|
|
|
|
2015-10-07 00:48:18 +01:00
|
|
|
if (current_shader[sel->type]->cso == sel) {
|
|
|
|
current_shader[sel->type]->cso = NULL;
|
|
|
|
current_shader[sel->type]->current = NULL;
|
|
|
|
}
|
2014-12-07 16:53:56 +00:00
|
|
|
|
|
|
|
while (p) {
|
|
|
|
c = p->next_variant;
|
2016-01-28 00:29:25 +00:00
|
|
|
si_delete_shader(sctx, p);
|
2014-12-07 16:53:56 +00:00
|
|
|
p = c;
|
|
|
|
}
|
|
|
|
|
2016-01-28 01:53:13 +00:00
|
|
|
if (sel->main_shader_part)
|
|
|
|
si_delete_shader(sctx, sel->main_shader_part);
|
2017-02-14 21:08:32 +00:00
|
|
|
if (sel->main_shader_part_ls)
|
|
|
|
si_delete_shader(sctx, sel->main_shader_part_ls);
|
|
|
|
if (sel->main_shader_part_es)
|
|
|
|
si_delete_shader(sctx, sel->main_shader_part_es);
|
2016-10-31 20:10:37 +00:00
|
|
|
if (sel->gs_copy_shader)
|
|
|
|
si_delete_shader(sctx, sel->gs_copy_shader);
|
2016-01-28 01:53:13 +00:00
|
|
|
|
2016-06-11 18:57:40 +01:00
|
|
|
util_queue_fence_destroy(&sel->ready);
|
2017-03-05 01:32:04 +00:00
|
|
|
mtx_destroy(&sel->mutex);
|
2014-12-07 16:53:56 +00:00
|
|
|
free(sel->tokens);
|
|
|
|
free(sel);
|
|
|
|
}
|
|
|
|
|
2016-01-02 01:25:51 +00:00
|
|
|
static unsigned si_get_ps_input_cntl(struct si_context *sctx,
|
|
|
|
struct si_shader *vs, unsigned name,
|
|
|
|
unsigned index, unsigned interpolate)
|
|
|
|
{
|
|
|
|
struct tgsi_shader_info *vsinfo = &vs->selector->info;
|
radeonsi: eliminate trivial constant VS outputs
These constant value VS PARAM exports:
- 0,0,0,0
- 0,0,0,1
- 1,1,1,0
- 1,1,1,1
can be loaded into PS inputs using the DEFAULT_VAL field, and the VS exports
can be removed from the IR to save export & parameter memory.
After LLVM optimizations, analyze the IR to see which exports are equal to
the ones listed above (or undef) and remove them if they are.
Targeted use cases:
- All DX9 eON ports always clear 10 VS outputs to 0.0 even if most of them
are unused by PS (such as Witcher 2 below).
- VS output arrays with unused elements that the GLSL compiler can't
eliminate (such as Batman below).
The shader-db deltas are quite interesting:
(not from upstream si-report.py, it won't be upstreamed)
PERCENTAGE DELTAS Shaders PARAM exports (affected only)
batman_arkham_origins 589 -67.17 %
bioshock-infinite 1769 -0.47 %
dirt-showdown 548 -2.68 %
dota2 1747 -3.36 %
f1-2015 776 -4.94 %
left_4_dead_2 1762 -0.07 %
metro_2033_redux 2670 -0.43 %
portal 474 -0.22 %
talos_principle 324 -3.63 %
warsow 176 -2.20 %
witcher2 1040 -73.78 %
----------------------------------------
All affected 991 -65.37 % ... 9681 -> 3353
----------------------------------------
Total 26725 -10.82 % ... 58490 -> 52162
v2: treat Undef as both 0 and 1
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v1)
Tested-by: Edmondo Tommasina <edmondo.tommasina@gmail.com> (v1)
2016-10-18 14:20:22 +01:00
|
|
|
unsigned j, offset, ps_input_cntl = 0;
|
2016-01-02 01:25:51 +00:00
|
|
|
|
|
|
|
if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
|
|
|
|
(interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
|
|
|
|
ps_input_cntl |= S_028644_FLAT_SHADE(1);
|
|
|
|
|
|
|
|
if (name == TGSI_SEMANTIC_PCOORD ||
|
|
|
|
(name == TGSI_SEMANTIC_TEXCOORD &&
|
|
|
|
sctx->sprite_coord_enable & (1 << index))) {
|
|
|
|
ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
|
|
|
|
}
|
|
|
|
|
|
|
|
for (j = 0; j < vsinfo->num_outputs; j++) {
|
|
|
|
if (name == vsinfo->output_semantic_name[j] &&
|
|
|
|
index == vsinfo->output_semantic_index[j]) {
|
radeonsi: eliminate trivial constant VS outputs
These constant value VS PARAM exports:
- 0,0,0,0
- 0,0,0,1
- 1,1,1,0
- 1,1,1,1
can be loaded into PS inputs using the DEFAULT_VAL field, and the VS exports
can be removed from the IR to save export & parameter memory.
After LLVM optimizations, analyze the IR to see which exports are equal to
the ones listed above (or undef) and remove them if they are.
Targeted use cases:
- All DX9 eON ports always clear 10 VS outputs to 0.0 even if most of them
are unused by PS (such as Witcher 2 below).
- VS output arrays with unused elements that the GLSL compiler can't
eliminate (such as Batman below).
The shader-db deltas are quite interesting:
(not from upstream si-report.py, it won't be upstreamed)
PERCENTAGE DELTAS Shaders PARAM exports (affected only)
batman_arkham_origins 589 -67.17 %
bioshock-infinite 1769 -0.47 %
dirt-showdown 548 -2.68 %
dota2 1747 -3.36 %
f1-2015 776 -4.94 %
left_4_dead_2 1762 -0.07 %
metro_2033_redux 2670 -0.43 %
portal 474 -0.22 %
talos_principle 324 -3.63 %
warsow 176 -2.20 %
witcher2 1040 -73.78 %
----------------------------------------
All affected 991 -65.37 % ... 9681 -> 3353
----------------------------------------
Total 26725 -10.82 % ... 58490 -> 52162
v2: treat Undef as both 0 and 1
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v1)
Tested-by: Edmondo Tommasina <edmondo.tommasina@gmail.com> (v1)
2016-10-18 14:20:22 +01:00
|
|
|
offset = vs->info.vs_output_param_offset[j];
|
|
|
|
|
|
|
|
if (offset <= EXP_PARAM_OFFSET_31) {
|
|
|
|
/* The input is loaded from parameter memory. */
|
|
|
|
ps_input_cntl |= S_028644_OFFSET(offset);
|
|
|
|
} else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
|
2016-11-14 08:09:51 +00:00
|
|
|
if (offset == EXP_PARAM_UNDEFINED) {
|
|
|
|
/* This can happen with depth-only rendering. */
|
|
|
|
offset = 0;
|
|
|
|
} else {
|
|
|
|
/* The input is a DEFAULT_VAL constant. */
|
|
|
|
assert(offset >= EXP_PARAM_DEFAULT_VAL_0000 &&
|
|
|
|
offset <= EXP_PARAM_DEFAULT_VAL_1111);
|
|
|
|
offset -= EXP_PARAM_DEFAULT_VAL_0000;
|
|
|
|
}
|
radeonsi: eliminate trivial constant VS outputs
These constant value VS PARAM exports:
- 0,0,0,0
- 0,0,0,1
- 1,1,1,0
- 1,1,1,1
can be loaded into PS inputs using the DEFAULT_VAL field, and the VS exports
can be removed from the IR to save export & parameter memory.
After LLVM optimizations, analyze the IR to see which exports are equal to
the ones listed above (or undef) and remove them if they are.
Targeted use cases:
- All DX9 eON ports always clear 10 VS outputs to 0.0 even if most of them
are unused by PS (such as Witcher 2 below).
- VS output arrays with unused elements that the GLSL compiler can't
eliminate (such as Batman below).
The shader-db deltas are quite interesting:
(not from upstream si-report.py, it won't be upstreamed)
PERCENTAGE DELTAS Shaders PARAM exports (affected only)
batman_arkham_origins 589 -67.17 %
bioshock-infinite 1769 -0.47 %
dirt-showdown 548 -2.68 %
dota2 1747 -3.36 %
f1-2015 776 -4.94 %
left_4_dead_2 1762 -0.07 %
metro_2033_redux 2670 -0.43 %
portal 474 -0.22 %
talos_principle 324 -3.63 %
warsow 176 -2.20 %
witcher2 1040 -73.78 %
----------------------------------------
All affected 991 -65.37 % ... 9681 -> 3353
----------------------------------------
Total 26725 -10.82 % ... 58490 -> 52162
v2: treat Undef as both 0 and 1
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v1)
Tested-by: Edmondo Tommasina <edmondo.tommasina@gmail.com> (v1)
2016-10-18 14:20:22 +01:00
|
|
|
|
|
|
|
ps_input_cntl = S_028644_OFFSET(0x20) |
|
|
|
|
S_028644_DEFAULT_VAL(offset);
|
|
|
|
}
|
2016-01-02 01:25:51 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (name == TGSI_SEMANTIC_PRIMID)
|
|
|
|
/* PrimID is written after the last output. */
|
2016-02-11 20:09:38 +00:00
|
|
|
ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
|
2016-01-02 01:25:51 +00:00
|
|
|
else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
|
|
|
|
/* No corresponding output found, load defaults into input.
|
|
|
|
* Don't set any other bits.
|
|
|
|
* (FLAT_SHADE=1 completely changes behavior) */
|
|
|
|
ps_input_cntl = S_028644_OFFSET(0x20);
|
2016-03-19 18:57:00 +00:00
|
|
|
/* D3D 9 behaviour. GL is undefined */
|
|
|
|
if (name == TGSI_SEMANTIC_COLOR && index == 0)
|
|
|
|
ps_input_cntl |= S_028644_DEFAULT_VAL(3);
|
2016-01-02 01:25:51 +00:00
|
|
|
}
|
|
|
|
return ps_input_cntl;
|
|
|
|
}
|
|
|
|
|
2015-08-30 02:17:30 +01:00
|
|
|
static void si_emit_spi_map(struct si_context *sctx, struct r600_atom *atom)
|
2014-12-07 16:53:56 +00:00
|
|
|
{
|
2015-11-07 13:00:30 +00:00
|
|
|
struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
|
2015-10-07 00:48:18 +01:00
|
|
|
struct si_shader *ps = sctx->ps_shader.current;
|
2014-12-07 16:53:56 +00:00
|
|
|
struct si_shader *vs = si_get_vs_state(sctx);
|
2016-01-02 01:54:29 +00:00
|
|
|
struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
|
|
|
|
unsigned i, num_interp, num_written = 0, bcol_interp[2];
|
2015-08-30 02:17:30 +01:00
|
|
|
|
2016-01-02 01:54:29 +00:00
|
|
|
if (!ps || !ps->selector->info.num_inputs)
|
2015-08-30 02:17:30 +01:00
|
|
|
return;
|
|
|
|
|
2016-01-02 01:54:29 +00:00
|
|
|
num_interp = si_get_ps_num_interp(ps);
|
|
|
|
assert(num_interp > 0);
|
|
|
|
radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, num_interp);
|
2014-12-07 16:53:56 +00:00
|
|
|
|
|
|
|
for (i = 0; i < psinfo->num_inputs; i++) {
|
|
|
|
unsigned name = psinfo->input_semantic_name[i];
|
|
|
|
unsigned index = psinfo->input_semantic_index[i];
|
|
|
|
unsigned interpolate = psinfo->input_interpolate[i];
|
2016-01-02 01:54:29 +00:00
|
|
|
|
2016-01-02 01:25:51 +00:00
|
|
|
radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, name, index,
|
|
|
|
interpolate));
|
2015-08-30 02:17:30 +01:00
|
|
|
num_written++;
|
2014-12-07 16:53:56 +00:00
|
|
|
|
2016-01-02 01:54:29 +00:00
|
|
|
if (name == TGSI_SEMANTIC_COLOR) {
|
|
|
|
assert(index < ARRAY_SIZE(bcol_interp));
|
|
|
|
bcol_interp[index] = interpolate;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-11-13 02:17:46 +00:00
|
|
|
if (ps->key.part.ps.prolog.color_two_side) {
|
2016-01-02 01:54:29 +00:00
|
|
|
unsigned bcol = TGSI_SEMANTIC_BCOLOR;
|
|
|
|
|
|
|
|
for (i = 0; i < 2; i++) {
|
|
|
|
if (!(psinfo->colors_read & (0xf << (i * 4))))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, bcol,
|
|
|
|
i, bcol_interp[i]));
|
|
|
|
num_written++;
|
2014-12-07 16:53:56 +00:00
|
|
|
}
|
|
|
|
}
|
2016-01-02 01:54:29 +00:00
|
|
|
assert(num_interp == num_written);
|
2014-12-07 16:53:56 +00:00
|
|
|
}
|
|
|
|
|
2015-10-02 18:21:54 +01:00
|
|
|
/**
|
|
|
|
* Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
|
|
|
|
*/
|
|
|
|
static void si_init_config_add_vgt_flush(struct si_context *sctx)
|
|
|
|
{
|
|
|
|
if (sctx->init_config_has_vgt_flush)
|
|
|
|
return;
|
|
|
|
|
2016-08-23 14:26:01 +01:00
|
|
|
/* Done by Vulkan before VGT_FLUSH. */
|
|
|
|
si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
|
|
|
|
si_pm4_cmd_add(sctx->init_config,
|
|
|
|
EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
|
|
|
|
si_pm4_cmd_end(sctx->init_config, false);
|
|
|
|
|
2015-11-08 12:34:44 +00:00
|
|
|
/* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
|
2015-10-02 18:21:54 +01:00
|
|
|
si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
|
|
|
|
si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
|
|
|
|
si_pm4_cmd_end(sctx->init_config, false);
|
|
|
|
sctx->init_config_has_vgt_flush = true;
|
|
|
|
}
|
|
|
|
|
2014-12-07 16:53:56 +00:00
|
|
|
/* Initialize state related to ESGS / GSVS ring buffers */
|
2015-11-08 12:34:44 +00:00
|
|
|
static bool si_update_gs_ring_buffers(struct si_context *sctx)
|
2014-12-07 16:53:56 +00:00
|
|
|
{
|
2015-11-08 12:34:44 +00:00
|
|
|
struct si_shader_selector *es =
|
|
|
|
sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
|
|
|
|
struct si_shader_selector *gs = sctx->gs_shader.cso;
|
|
|
|
struct si_pm4_state *pm4;
|
2014-12-07 16:53:56 +00:00
|
|
|
|
2015-11-08 12:34:44 +00:00
|
|
|
/* Chip constants. */
|
|
|
|
unsigned num_se = sctx->screen->b.info.max_se;
|
|
|
|
unsigned wave_size = 64;
|
|
|
|
unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
|
|
|
|
unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
|
|
|
|
unsigned alignment = 256 * num_se;
|
|
|
|
/* The maximum size is 63.999 MB per SE. */
|
|
|
|
unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
|
|
|
|
|
|
|
|
/* Calculate the minimum size. */
|
|
|
|
unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
|
|
|
|
wave_size, alignment);
|
|
|
|
|
|
|
|
/* These are recommended sizes, not minimum sizes. */
|
|
|
|
unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
|
|
|
|
es->esgs_itemsize * gs->gs_input_verts_per_prim;
|
|
|
|
unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
|
2016-11-30 11:26:49 +00:00
|
|
|
gs->max_gsvs_emit_size;
|
2015-11-08 12:34:44 +00:00
|
|
|
|
|
|
|
min_esgs_ring_size = align(min_esgs_ring_size, alignment);
|
|
|
|
esgs_ring_size = align(esgs_ring_size, alignment);
|
|
|
|
gsvs_ring_size = align(gsvs_ring_size, alignment);
|
|
|
|
|
|
|
|
esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
|
|
|
|
gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
|
|
|
|
|
|
|
|
/* Some rings don't have to be allocated if shaders don't use them.
|
|
|
|
* (e.g. no varyings between ES and GS or GS and VS)
|
|
|
|
*/
|
|
|
|
bool update_esgs = esgs_ring_size &&
|
|
|
|
(!sctx->esgs_ring ||
|
|
|
|
sctx->esgs_ring->width0 < esgs_ring_size);
|
|
|
|
bool update_gsvs = gsvs_ring_size &&
|
|
|
|
(!sctx->gsvs_ring ||
|
|
|
|
sctx->gsvs_ring->width0 < gsvs_ring_size);
|
2014-12-07 16:53:56 +00:00
|
|
|
|
2015-11-08 12:34:44 +00:00
|
|
|
if (!update_esgs && !update_gsvs)
|
|
|
|
return true;
|
2014-12-07 16:53:56 +00:00
|
|
|
|
2015-11-08 12:34:44 +00:00
|
|
|
if (update_esgs) {
|
2015-09-10 17:27:53 +01:00
|
|
|
pipe_resource_reference(&sctx->esgs_ring, NULL);
|
2017-02-15 19:44:24 +00:00
|
|
|
sctx->esgs_ring =
|
|
|
|
r600_aligned_buffer_create(sctx->b.b.screen,
|
|
|
|
R600_RESOURCE_FLAG_UNMAPPABLE,
|
|
|
|
PIPE_USAGE_DEFAULT,
|
|
|
|
esgs_ring_size, alignment);
|
2015-11-08 12:34:44 +00:00
|
|
|
if (!sctx->esgs_ring)
|
|
|
|
return false;
|
2015-09-10 17:27:53 +01:00
|
|
|
}
|
2014-12-07 16:53:56 +00:00
|
|
|
|
2015-11-08 12:34:44 +00:00
|
|
|
if (update_gsvs) {
|
|
|
|
pipe_resource_reference(&sctx->gsvs_ring, NULL);
|
2017-02-15 19:44:24 +00:00
|
|
|
sctx->gsvs_ring =
|
|
|
|
r600_aligned_buffer_create(sctx->b.b.screen,
|
|
|
|
R600_RESOURCE_FLAG_UNMAPPABLE,
|
|
|
|
PIPE_USAGE_DEFAULT,
|
|
|
|
gsvs_ring_size, alignment);
|
2015-11-08 12:34:44 +00:00
|
|
|
if (!sctx->gsvs_ring)
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Create the "init_config_gs_rings" state. */
|
|
|
|
pm4 = CALLOC_STRUCT(si_pm4_state);
|
|
|
|
if (!pm4)
|
|
|
|
return false;
|
2015-10-02 18:21:54 +01:00
|
|
|
|
2014-12-07 16:53:56 +00:00
|
|
|
if (sctx->b.chip_class >= CIK) {
|
2015-11-08 12:34:44 +00:00
|
|
|
if (sctx->esgs_ring)
|
|
|
|
si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
|
|
|
|
sctx->esgs_ring->width0 / 256);
|
|
|
|
if (sctx->gsvs_ring)
|
|
|
|
si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
|
|
|
|
sctx->gsvs_ring->width0 / 256);
|
2014-12-07 16:53:56 +00:00
|
|
|
} else {
|
2015-11-08 12:34:44 +00:00
|
|
|
if (sctx->esgs_ring)
|
|
|
|
si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
|
|
|
|
sctx->esgs_ring->width0 / 256);
|
|
|
|
if (sctx->gsvs_ring)
|
|
|
|
si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
|
|
|
|
sctx->gsvs_ring->width0 / 256);
|
2014-12-07 16:53:56 +00:00
|
|
|
}
|
|
|
|
|
2015-11-08 12:34:44 +00:00
|
|
|
/* Set the state. */
|
|
|
|
if (sctx->init_config_gs_rings)
|
|
|
|
si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
|
|
|
|
sctx->init_config_gs_rings = pm4;
|
|
|
|
|
|
|
|
if (!sctx->init_config_has_vgt_flush) {
|
|
|
|
si_init_config_add_vgt_flush(sctx);
|
|
|
|
si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Flush the context to re-emit both init_config states. */
|
2015-08-29 00:45:28 +01:00
|
|
|
sctx->b.initial_gfx_cs_size = 0; /* force flush */
|
|
|
|
si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
|
|
|
|
|
2015-11-08 12:34:44 +00:00
|
|
|
/* Set ring bindings. */
|
|
|
|
if (sctx->esgs_ring) {
|
2016-04-21 16:52:29 +01:00
|
|
|
si_set_ring_buffer(&sctx->b.b, SI_ES_RING_ESGS,
|
2015-11-08 12:34:44 +00:00
|
|
|
sctx->esgs_ring, 0, sctx->esgs_ring->width0,
|
|
|
|
true, true, 4, 64, 0);
|
2016-04-21 16:52:29 +01:00
|
|
|
si_set_ring_buffer(&sctx->b.b, SI_GS_RING_ESGS,
|
2015-11-08 12:34:44 +00:00
|
|
|
sctx->esgs_ring, 0, sctx->esgs_ring->width0,
|
|
|
|
false, false, 0, 0, 0);
|
|
|
|
}
|
2016-11-28 19:30:41 +00:00
|
|
|
if (sctx->gsvs_ring) {
|
2016-11-29 16:41:59 +00:00
|
|
|
si_set_ring_buffer(&sctx->b.b, SI_RING_GSVS,
|
2015-11-08 12:34:44 +00:00
|
|
|
sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
|
|
|
|
false, false, 0, 0, 0);
|
2016-11-28 19:30:41 +00:00
|
|
|
}
|
|
|
|
|
2015-11-08 12:34:44 +00:00
|
|
|
return true;
|
2014-12-07 16:53:56 +00:00
|
|
|
}
|
|
|
|
|
2014-12-10 14:13:59 +00:00
|
|
|
/**
|
2015-09-10 17:40:51 +01:00
|
|
|
* @returns 1 if \p sel has been updated to use a new scratch buffer
|
|
|
|
* 0 if not
|
|
|
|
* < 0 if there was a failure
|
2014-12-10 14:13:59 +00:00
|
|
|
*/
|
2015-09-10 17:40:51 +01:00
|
|
|
static int si_update_scratch_buffer(struct si_context *sctx,
|
2015-10-07 00:48:18 +01:00
|
|
|
struct si_shader *shader)
|
2014-12-10 14:13:59 +00:00
|
|
|
{
|
|
|
|
uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
|
2015-09-10 17:40:51 +01:00
|
|
|
int r;
|
2014-12-10 14:13:59 +00:00
|
|
|
|
2015-10-07 00:48:18 +01:00
|
|
|
if (!shader)
|
2014-12-10 14:13:59 +00:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
/* This shader doesn't need a scratch buffer */
|
2015-12-27 23:14:05 +00:00
|
|
|
if (shader->config.scratch_bytes_per_wave == 0)
|
2014-12-10 14:13:59 +00:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
/* This shader is already configured to use the current
|
|
|
|
* scratch buffer. */
|
|
|
|
if (shader->scratch_bo == sctx->scratch_buffer)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
assert(sctx->scratch_buffer);
|
|
|
|
|
2016-04-21 17:12:48 +01:00
|
|
|
si_shader_apply_scratch_relocs(sctx, shader, &shader->config, scratch_va);
|
2014-12-10 14:13:59 +00:00
|
|
|
|
|
|
|
/* Replace the shader bo with a new bo that has the relocs applied. */
|
2015-09-10 17:40:51 +01:00
|
|
|
r = si_shader_binary_upload(sctx->screen, shader);
|
|
|
|
if (r)
|
|
|
|
return r;
|
2014-12-10 14:13:59 +00:00
|
|
|
|
|
|
|
/* Update the shader state to use the new shader bo. */
|
2016-04-12 19:28:46 +01:00
|
|
|
si_shader_init_pm4_state(sctx->screen, shader);
|
2014-12-10 14:13:59 +00:00
|
|
|
|
|
|
|
r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
|
|
|
|
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
|
|
|
|
{
|
2015-10-09 00:37:57 +01:00
|
|
|
return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
|
2014-12-10 14:13:59 +00:00
|
|
|
}
|
|
|
|
|
2015-10-07 00:48:18 +01:00
|
|
|
static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
|
2014-12-10 14:13:59 +00:00
|
|
|
{
|
2015-12-27 23:14:05 +00:00
|
|
|
return shader ? shader->config.scratch_bytes_per_wave : 0;
|
2014-12-10 14:13:59 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
|
|
|
|
{
|
2015-05-18 13:41:35 +01:00
|
|
|
unsigned bytes = 0;
|
|
|
|
|
2015-10-07 00:48:18 +01:00
|
|
|
bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
|
|
|
|
bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
|
|
|
|
bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
|
|
|
|
bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tcs_shader.current));
|
|
|
|
bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
|
2015-05-18 13:41:35 +01:00
|
|
|
return bytes;
|
2014-12-10 14:13:59 +00:00
|
|
|
}
|
|
|
|
|
2015-09-10 17:40:51 +01:00
|
|
|
static bool si_update_spi_tmpring_size(struct si_context *sctx)
|
2014-12-10 14:13:59 +00:00
|
|
|
{
|
|
|
|
unsigned current_scratch_buffer_size =
|
|
|
|
si_get_current_scratch_buffer_size(sctx);
|
|
|
|
unsigned scratch_bytes_per_wave =
|
|
|
|
si_get_max_scratch_bytes_per_wave(sctx);
|
|
|
|
unsigned scratch_needed_size = scratch_bytes_per_wave *
|
|
|
|
sctx->scratch_waves;
|
2016-01-13 17:42:02 +00:00
|
|
|
unsigned spi_tmpring_size;
|
2015-09-10 17:40:51 +01:00
|
|
|
int r;
|
2014-12-10 14:13:59 +00:00
|
|
|
|
|
|
|
if (scratch_needed_size > 0) {
|
|
|
|
if (scratch_needed_size > current_scratch_buffer_size) {
|
|
|
|
/* Create a bigger scratch buffer */
|
2016-06-21 20:13:00 +01:00
|
|
|
r600_resource_reference(&sctx->scratch_buffer, NULL);
|
2014-12-10 14:13:59 +00:00
|
|
|
|
2016-10-24 22:29:50 +01:00
|
|
|
sctx->scratch_buffer = (struct r600_resource*)
|
2017-02-15 19:44:24 +00:00
|
|
|
r600_aligned_buffer_create(&sctx->screen->b.b,
|
|
|
|
R600_RESOURCE_FLAG_UNMAPPABLE,
|
|
|
|
PIPE_USAGE_DEFAULT,
|
|
|
|
scratch_needed_size, 256);
|
2015-09-10 17:40:51 +01:00
|
|
|
if (!sctx->scratch_buffer)
|
|
|
|
return false;
|
2017-01-26 01:56:15 +00:00
|
|
|
|
|
|
|
si_mark_atom_dirty(sctx, &sctx->scratch_state);
|
|
|
|
r600_context_add_resource_size(&sctx->b.b,
|
|
|
|
&sctx->scratch_buffer->b.b);
|
2014-12-10 14:13:59 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Update the shaders, so they are using the latest scratch. The
|
|
|
|
* scratch buffer may have been changed since these shaders were
|
|
|
|
* last used, so we still need to try to update them, even if
|
|
|
|
* they require scratch buffers smaller than the current size.
|
|
|
|
*/
|
2015-10-07 00:48:18 +01:00
|
|
|
r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
|
2015-09-10 17:40:51 +01:00
|
|
|
if (r < 0)
|
|
|
|
return false;
|
|
|
|
if (r == 1)
|
2015-10-07 00:48:18 +01:00
|
|
|
si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
|
2015-09-10 17:40:51 +01:00
|
|
|
|
2015-10-07 00:48:18 +01:00
|
|
|
r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
|
2015-09-10 17:40:51 +01:00
|
|
|
if (r < 0)
|
|
|
|
return false;
|
|
|
|
if (r == 1)
|
2015-10-07 00:48:18 +01:00
|
|
|
si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
|
2015-09-10 17:40:51 +01:00
|
|
|
|
2015-10-07 00:48:18 +01:00
|
|
|
r = si_update_scratch_buffer(sctx, sctx->tcs_shader.current);
|
2015-09-10 17:40:51 +01:00
|
|
|
if (r < 0)
|
|
|
|
return false;
|
|
|
|
if (r == 1)
|
2015-10-07 00:48:18 +01:00
|
|
|
si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
|
2015-05-18 13:56:34 +01:00
|
|
|
|
2015-05-18 13:41:35 +01:00
|
|
|
/* VS can be bound as LS, ES, or VS. */
|
2015-10-07 00:48:18 +01:00
|
|
|
r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
|
2015-10-09 00:35:32 +01:00
|
|
|
if (r < 0)
|
|
|
|
return false;
|
|
|
|
if (r == 1) {
|
2015-10-07 00:48:18 +01:00
|
|
|
if (sctx->tes_shader.current)
|
|
|
|
si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
|
|
|
|
else if (sctx->gs_shader.current)
|
|
|
|
si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
|
2015-10-09 00:35:32 +01:00
|
|
|
else
|
2015-10-07 00:48:18 +01:00
|
|
|
si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
|
2015-05-18 13:56:34 +01:00
|
|
|
}
|
2015-05-18 13:41:35 +01:00
|
|
|
|
|
|
|
/* TES can be bound as ES or VS. */
|
2015-10-07 00:48:18 +01:00
|
|
|
r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
|
2015-10-09 00:35:32 +01:00
|
|
|
if (r < 0)
|
|
|
|
return false;
|
|
|
|
if (r == 1) {
|
2015-10-07 00:48:18 +01:00
|
|
|
if (sctx->gs_shader.current)
|
|
|
|
si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
|
2015-10-09 00:35:32 +01:00
|
|
|
else
|
2015-10-07 00:48:18 +01:00
|
|
|
si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
|
2015-05-18 13:41:35 +01:00
|
|
|
}
|
2014-12-10 14:13:59 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* The LLVM shader backend should be reporting aligned scratch_sizes. */
|
|
|
|
assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
|
|
|
|
"scratch size should already be aligned correctly.");
|
|
|
|
|
2016-01-13 17:42:02 +00:00
|
|
|
spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
|
|
|
|
S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
|
|
|
|
if (spi_tmpring_size != sctx->spi_tmpring_size) {
|
|
|
|
sctx->spi_tmpring_size = spi_tmpring_size;
|
2017-01-26 01:56:15 +00:00
|
|
|
si_mark_atom_dirty(sctx, &sctx->scratch_state);
|
2016-01-13 17:42:02 +00:00
|
|
|
}
|
2015-09-10 17:40:51 +01:00
|
|
|
return true;
|
2014-12-10 14:13:59 +00:00
|
|
|
}
|
|
|
|
|
2015-02-22 16:25:37 +00:00
|
|
|
static void si_init_tess_factor_ring(struct si_context *sctx)
|
|
|
|
{
|
2017-02-22 18:56:26 +00:00
|
|
|
bool double_offchip_buffers = sctx->b.chip_class >= CIK &&
|
|
|
|
sctx->b.family != CHIP_CARRIZO &&
|
|
|
|
sctx->b.family != CHIP_STONEY;
|
2016-06-28 13:11:12 +01:00
|
|
|
unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
|
|
|
|
unsigned max_offchip_buffers = max_offchip_buffers_per_se *
|
|
|
|
sctx->screen->b.info.max_se;
|
|
|
|
unsigned offchip_granularity;
|
|
|
|
|
|
|
|
switch (sctx->screen->tess_offchip_block_dw_size) {
|
|
|
|
default:
|
|
|
|
assert(0);
|
|
|
|
/* fall through */
|
|
|
|
case 8192:
|
|
|
|
offchip_granularity = V_03093C_X_8K_DWORDS;
|
|
|
|
break;
|
|
|
|
case 4096:
|
|
|
|
offchip_granularity = V_03093C_X_4K_DWORDS;
|
|
|
|
break;
|
|
|
|
}
|
2015-02-22 16:25:37 +00:00
|
|
|
|
2016-06-28 13:11:12 +01:00
|
|
|
switch (sctx->b.chip_class) {
|
|
|
|
case SI:
|
|
|
|
max_offchip_buffers = MIN2(max_offchip_buffers, 126);
|
|
|
|
break;
|
|
|
|
case CIK:
|
2016-10-15 13:17:56 +01:00
|
|
|
case GFX9:
|
2016-06-28 13:11:12 +01:00
|
|
|
max_offchip_buffers = MIN2(max_offchip_buffers, 508);
|
|
|
|
break;
|
|
|
|
case VI:
|
|
|
|
default:
|
|
|
|
max_offchip_buffers = MIN2(max_offchip_buffers, 512);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
assert(!sctx->tf_ring);
|
2017-02-15 19:44:24 +00:00
|
|
|
sctx->tf_ring = r600_aligned_buffer_create(sctx->b.b.screen,
|
|
|
|
R600_RESOURCE_FLAG_UNMAPPABLE,
|
|
|
|
PIPE_USAGE_DEFAULT,
|
|
|
|
32768 * sctx->screen->b.info.max_se,
|
|
|
|
256);
|
2015-09-10 17:27:53 +01:00
|
|
|
if (!sctx->tf_ring)
|
|
|
|
return;
|
|
|
|
|
2015-02-22 16:25:37 +00:00
|
|
|
assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0);
|
|
|
|
|
2017-02-15 19:44:24 +00:00
|
|
|
sctx->tess_offchip_ring =
|
|
|
|
r600_aligned_buffer_create(sctx->b.b.screen,
|
|
|
|
R600_RESOURCE_FLAG_UNMAPPABLE,
|
|
|
|
PIPE_USAGE_DEFAULT,
|
|
|
|
max_offchip_buffers *
|
|
|
|
sctx->screen->tess_offchip_block_dw_size * 4,
|
|
|
|
256);
|
2016-05-02 08:54:11 +01:00
|
|
|
if (!sctx->tess_offchip_ring)
|
|
|
|
return;
|
|
|
|
|
2015-10-02 18:21:54 +01:00
|
|
|
si_init_config_add_vgt_flush(sctx);
|
|
|
|
|
2015-08-29 00:45:28 +01:00
|
|
|
/* Append these registers to the init config state. */
|
2015-02-22 16:25:37 +00:00
|
|
|
if (sctx->b.chip_class >= CIK) {
|
2016-06-28 13:11:12 +01:00
|
|
|
if (sctx->b.chip_class >= VI)
|
|
|
|
--max_offchip_buffers;
|
2016-05-29 17:35:22 +01:00
|
|
|
|
2015-08-29 00:45:28 +01:00
|
|
|
si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
|
2015-02-22 16:25:37 +00:00
|
|
|
S_030938_SIZE(sctx->tf_ring->width0 / 4));
|
2015-08-29 00:45:28 +01:00
|
|
|
si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
|
2015-02-22 16:25:37 +00:00
|
|
|
r600_resource(sctx->tf_ring)->gpu_address >> 8);
|
2016-05-02 08:54:11 +01:00
|
|
|
si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
|
2016-06-28 13:11:12 +01:00
|
|
|
S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
|
|
|
|
S_03093C_OFFCHIP_GRANULARITY(offchip_granularity));
|
2015-02-22 16:25:37 +00:00
|
|
|
} else {
|
2016-06-28 13:11:12 +01:00
|
|
|
assert(offchip_granularity == V_03093C_X_8K_DWORDS);
|
2015-08-29 00:45:28 +01:00
|
|
|
si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
|
2015-02-22 16:25:37 +00:00
|
|
|
S_008988_SIZE(sctx->tf_ring->width0 / 4));
|
2015-08-29 00:45:28 +01:00
|
|
|
si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
|
2015-02-22 16:25:37 +00:00
|
|
|
r600_resource(sctx->tf_ring)->gpu_address >> 8);
|
2016-05-02 08:54:11 +01:00
|
|
|
si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
|
2016-06-28 13:11:12 +01:00
|
|
|
S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers));
|
2015-02-22 16:25:37 +00:00
|
|
|
}
|
2015-08-29 00:45:28 +01:00
|
|
|
|
|
|
|
/* Flush the context to re-emit the init_config state.
|
|
|
|
* This is done only once in a lifetime of a context.
|
|
|
|
*/
|
2015-08-30 17:46:06 +01:00
|
|
|
si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
|
2015-08-29 00:45:28 +01:00
|
|
|
sctx->b.initial_gfx_cs_size = 0; /* force flush */
|
|
|
|
si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
|
2015-02-22 16:25:37 +00:00
|
|
|
|
2016-04-21 16:52:29 +01:00
|
|
|
si_set_ring_buffer(&sctx->b.b, SI_HS_RING_TESS_FACTOR, sctx->tf_ring,
|
|
|
|
0, sctx->tf_ring->width0, false, false, 0, 0, 0);
|
2016-05-02 08:54:11 +01:00
|
|
|
|
|
|
|
si_set_ring_buffer(&sctx->b.b, SI_HS_RING_TESS_OFFCHIP,
|
|
|
|
sctx->tess_offchip_ring, 0,
|
|
|
|
sctx->tess_offchip_ring->width0, false, false, 0, 0, 0);
|
2015-02-22 16:25:37 +00:00
|
|
|
}
|
|
|
|
|
2015-05-18 00:59:37 +01:00
|
|
|
/**
|
|
|
|
* This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
|
|
|
|
* VS passes its outputs to TES directly, so the fixed-function shader only
|
|
|
|
* has to write TESSOUTER and TESSINNER.
|
|
|
|
*/
|
|
|
|
static void si_generate_fixed_func_tcs(struct si_context *sctx)
|
|
|
|
{
|
2016-04-19 01:09:55 +01:00
|
|
|
struct ureg_src outer, inner;
|
2015-05-18 00:59:37 +01:00
|
|
|
struct ureg_dst tessouter, tessinner;
|
2016-04-16 13:41:57 +01:00
|
|
|
struct ureg_program *ureg = ureg_create(PIPE_SHADER_TESS_CTRL);
|
2015-05-18 00:59:37 +01:00
|
|
|
|
|
|
|
if (!ureg)
|
|
|
|
return; /* if we get here, we're screwed */
|
|
|
|
|
2015-10-07 00:48:18 +01:00
|
|
|
assert(!sctx->fixed_func_tcs_shader.cso);
|
2015-05-18 00:59:37 +01:00
|
|
|
|
2016-04-19 01:09:55 +01:00
|
|
|
outer = ureg_DECL_system_value(ureg,
|
|
|
|
TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI, 0);
|
|
|
|
inner = ureg_DECL_system_value(ureg,
|
|
|
|
TGSI_SEMANTIC_DEFAULT_TESSINNER_SI, 0);
|
2015-05-18 00:59:37 +01:00
|
|
|
|
|
|
|
tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
|
|
|
|
tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
|
|
|
|
|
2016-04-19 01:09:55 +01:00
|
|
|
ureg_MOV(ureg, tessouter, outer);
|
|
|
|
ureg_MOV(ureg, tessinner, inner);
|
2015-05-18 00:59:37 +01:00
|
|
|
ureg_END(ureg);
|
|
|
|
|
2015-10-07 00:48:18 +01:00
|
|
|
sctx->fixed_func_tcs_shader.cso =
|
2015-05-18 00:59:37 +01:00
|
|
|
ureg_create_shader_and_destroy(ureg, &sctx->b.b);
|
|
|
|
}
|
|
|
|
|
2014-09-18 23:16:12 +01:00
|
|
|
static void si_update_vgt_shader_config(struct si_context *sctx)
|
|
|
|
{
|
|
|
|
/* Calculate the index of the config.
|
|
|
|
* 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
|
2015-10-07 00:48:18 +01:00
|
|
|
unsigned index = 2*!!sctx->tes_shader.cso + !!sctx->gs_shader.cso;
|
2014-09-18 23:16:12 +01:00
|
|
|
struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
|
|
|
|
|
|
|
|
if (!*pm4) {
|
|
|
|
uint32_t stages = 0;
|
|
|
|
|
|
|
|
*pm4 = CALLOC_STRUCT(si_pm4_state);
|
|
|
|
|
2015-10-07 00:48:18 +01:00
|
|
|
if (sctx->tes_shader.cso) {
|
2014-09-18 23:16:12 +01:00
|
|
|
stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
|
2016-05-02 13:59:43 +01:00
|
|
|
S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
|
2014-09-18 23:16:12 +01:00
|
|
|
|
2015-10-07 00:48:18 +01:00
|
|
|
if (sctx->gs_shader.cso)
|
2014-09-18 23:16:12 +01:00
|
|
|
stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
|
|
|
|
S_028B54_GS_EN(1) |
|
|
|
|
S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
|
|
|
|
else
|
|
|
|
stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
|
2015-10-07 00:48:18 +01:00
|
|
|
} else if (sctx->gs_shader.cso) {
|
2014-09-18 23:16:12 +01:00
|
|
|
stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
|
|
|
|
S_028B54_GS_EN(1) |
|
|
|
|
S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
|
|
|
|
}
|
|
|
|
|
|
|
|
si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
|
|
|
|
}
|
|
|
|
si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
|
|
|
|
}
|
|
|
|
|
2015-07-09 07:34:59 +01:00
|
|
|
static void si_update_so(struct si_context *sctx, struct si_shader_selector *shader)
|
|
|
|
{
|
|
|
|
struct pipe_stream_output_info *so = &shader->so;
|
|
|
|
uint32_t enabled_stream_buffers_mask = 0;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < so->num_outputs; i++)
|
2015-07-20 02:37:14 +01:00
|
|
|
enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << (so->output[i].stream * 4);
|
2015-07-09 07:34:59 +01:00
|
|
|
sctx->b.streamout.enabled_stream_buffers_mask = enabled_stream_buffers_mask;
|
|
|
|
sctx->b.streamout.stride_in_dw = shader->so.stride;
|
|
|
|
}
|
|
|
|
|
2015-09-10 17:27:53 +01:00
|
|
|
bool si_update_shaders(struct si_context *sctx)
|
2014-12-07 16:53:56 +00:00
|
|
|
{
|
|
|
|
struct pipe_context *ctx = (struct pipe_context*)sctx;
|
2017-01-17 17:04:13 +00:00
|
|
|
struct si_compiler_ctx_state compiler_state;
|
2015-01-04 19:23:51 +00:00
|
|
|
struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
|
2017-01-03 10:02:41 +00:00
|
|
|
struct si_shader *old_vs = si_get_vs_state(sctx);
|
|
|
|
bool old_clip_disable = old_vs ? old_vs->key.opt.hw_vs.clip_disable : false;
|
2015-09-10 17:32:22 +01:00
|
|
|
int r;
|
2014-12-07 16:53:56 +00:00
|
|
|
|
2017-01-17 17:04:13 +00:00
|
|
|
compiler_state.tm = sctx->tm;
|
|
|
|
compiler_state.debug = sctx->b.debug;
|
|
|
|
compiler_state.is_debug_context = sctx->is_debug;
|
|
|
|
|
2015-02-22 16:07:34 +00:00
|
|
|
/* Update stages before GS. */
|
2015-10-07 00:48:18 +01:00
|
|
|
if (sctx->tes_shader.cso) {
|
2015-09-10 17:27:53 +01:00
|
|
|
if (!sctx->tf_ring) {
|
2015-02-22 16:25:37 +00:00
|
|
|
si_init_tess_factor_ring(sctx);
|
2015-09-10 17:27:53 +01:00
|
|
|
if (!sctx->tf_ring)
|
|
|
|
return false;
|
|
|
|
}
|
2015-02-22 16:25:37 +00:00
|
|
|
|
2015-02-22 16:07:34 +00:00
|
|
|
/* VS as LS */
|
2017-01-17 17:04:13 +00:00
|
|
|
r = si_shader_select(ctx, &sctx->vs_shader, &compiler_state);
|
2015-09-10 17:32:22 +01:00
|
|
|
if (r)
|
|
|
|
return false;
|
2015-10-07 00:48:18 +01:00
|
|
|
si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
|
2015-02-22 16:07:34 +00:00
|
|
|
|
2015-10-07 00:48:18 +01:00
|
|
|
if (sctx->tcs_shader.cso) {
|
2017-01-17 17:04:13 +00:00
|
|
|
r = si_shader_select(ctx, &sctx->tcs_shader,
|
|
|
|
&compiler_state);
|
2015-09-10 17:32:22 +01:00
|
|
|
if (r)
|
|
|
|
return false;
|
2015-10-07 00:48:18 +01:00
|
|
|
si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
|
2015-02-22 16:07:34 +00:00
|
|
|
} else {
|
2015-10-07 00:48:18 +01:00
|
|
|
if (!sctx->fixed_func_tcs_shader.cso) {
|
2015-05-18 00:59:37 +01:00
|
|
|
si_generate_fixed_func_tcs(sctx);
|
2015-10-07 00:48:18 +01:00
|
|
|
if (!sctx->fixed_func_tcs_shader.cso)
|
2015-09-10 17:31:33 +01:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2017-01-17 17:04:13 +00:00
|
|
|
r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
|
|
|
|
&compiler_state);
|
2015-09-10 17:32:22 +01:00
|
|
|
if (r)
|
|
|
|
return false;
|
2015-05-18 00:59:37 +01:00
|
|
|
si_pm4_bind_state(sctx, hs,
|
2015-10-07 00:48:18 +01:00
|
|
|
sctx->fixed_func_tcs_shader.current->pm4);
|
2015-02-22 16:07:34 +00:00
|
|
|
}
|
|
|
|
|
2017-01-17 17:04:13 +00:00
|
|
|
r = si_shader_select(ctx, &sctx->tes_shader, &compiler_state);
|
2015-09-10 17:32:22 +01:00
|
|
|
if (r)
|
|
|
|
return false;
|
|
|
|
|
2015-10-07 00:48:18 +01:00
|
|
|
if (sctx->gs_shader.cso) {
|
2015-02-22 16:07:34 +00:00
|
|
|
/* TES as ES */
|
2015-10-07 00:48:18 +01:00
|
|
|
si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
|
2015-02-22 16:07:34 +00:00
|
|
|
} else {
|
|
|
|
/* TES as VS */
|
2015-10-07 00:48:18 +01:00
|
|
|
si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
|
|
|
|
si_update_so(sctx, sctx->tes_shader.cso);
|
2015-02-22 16:07:34 +00:00
|
|
|
}
|
2015-10-07 00:48:18 +01:00
|
|
|
} else if (sctx->gs_shader.cso) {
|
2015-02-22 16:07:34 +00:00
|
|
|
/* VS as ES */
|
2017-01-17 17:04:13 +00:00
|
|
|
r = si_shader_select(ctx, &sctx->vs_shader, &compiler_state);
|
2015-09-10 17:32:22 +01:00
|
|
|
if (r)
|
|
|
|
return false;
|
2015-10-07 00:48:18 +01:00
|
|
|
si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
|
2017-01-24 21:54:06 +00:00
|
|
|
|
|
|
|
si_pm4_bind_state(sctx, ls, NULL);
|
|
|
|
si_pm4_bind_state(sctx, hs, NULL);
|
2015-02-22 16:07:34 +00:00
|
|
|
} else {
|
|
|
|
/* VS as VS */
|
2017-01-17 17:04:13 +00:00
|
|
|
r = si_shader_select(ctx, &sctx->vs_shader, &compiler_state);
|
2015-09-10 17:32:22 +01:00
|
|
|
if (r)
|
|
|
|
return false;
|
2015-10-07 00:48:18 +01:00
|
|
|
si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
|
|
|
|
si_update_so(sctx, sctx->vs_shader.cso);
|
2017-01-24 21:54:06 +00:00
|
|
|
|
|
|
|
si_pm4_bind_state(sctx, ls, NULL);
|
|
|
|
si_pm4_bind_state(sctx, hs, NULL);
|
2015-02-22 16:07:34 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Update GS. */
|
2015-10-07 00:48:18 +01:00
|
|
|
if (sctx->gs_shader.cso) {
|
2017-01-17 17:04:13 +00:00
|
|
|
r = si_shader_select(ctx, &sctx->gs_shader, &compiler_state);
|
2015-09-10 17:32:22 +01:00
|
|
|
if (r)
|
|
|
|
return false;
|
2015-10-07 00:48:18 +01:00
|
|
|
si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
|
2016-10-31 20:10:37 +00:00
|
|
|
si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
|
2015-10-07 00:48:18 +01:00
|
|
|
si_update_so(sctx, sctx->gs_shader.cso);
|
2014-12-07 16:53:56 +00:00
|
|
|
|
2015-11-08 12:34:44 +00:00
|
|
|
if (!si_update_gs_ring_buffers(sctx))
|
|
|
|
return false;
|
2014-12-07 16:53:56 +00:00
|
|
|
} else {
|
|
|
|
si_pm4_bind_state(sctx, gs, NULL);
|
|
|
|
si_pm4_bind_state(sctx, es, NULL);
|
|
|
|
}
|
|
|
|
|
2014-09-18 23:16:12 +01:00
|
|
|
si_update_vgt_shader_config(sctx);
|
|
|
|
|
2017-01-03 10:02:41 +00:00
|
|
|
if (old_clip_disable != si_get_vs_state(sctx)->key.opt.hw_vs.clip_disable)
|
|
|
|
si_mark_atom_dirty(sctx, &sctx->clip_regs);
|
|
|
|
|
2015-10-22 21:17:28 +01:00
|
|
|
if (sctx->ps_shader.cso) {
|
2016-02-21 23:40:04 +00:00
|
|
|
unsigned db_shader_control;
|
2015-12-23 14:36:05 +00:00
|
|
|
|
2017-01-17 17:04:13 +00:00
|
|
|
r = si_shader_select(ctx, &sctx->ps_shader, &compiler_state);
|
2015-10-22 21:17:28 +01:00
|
|
|
if (r)
|
|
|
|
return false;
|
|
|
|
si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
|
|
|
|
|
2016-02-21 23:40:04 +00:00
|
|
|
db_shader_control =
|
|
|
|
sctx->ps_shader.cso->db_shader_control |
|
2016-10-12 21:15:31 +01:00
|
|
|
S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
|
2016-02-21 23:40:04 +00:00
|
|
|
|
2015-10-22 21:17:28 +01:00
|
|
|
if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
|
|
|
|
sctx->sprite_coord_enable != rs->sprite_coord_enable ||
|
|
|
|
sctx->flatshade != rs->flatshade) {
|
|
|
|
sctx->sprite_coord_enable = rs->sprite_coord_enable;
|
|
|
|
sctx->flatshade = rs->flatshade;
|
|
|
|
si_mark_atom_dirty(sctx, &sctx->spi_map);
|
|
|
|
}
|
|
|
|
|
2016-01-17 20:13:16 +00:00
|
|
|
if (sctx->b.family == CHIP_STONEY && si_pm4_state_changed(sctx, ps))
|
|
|
|
si_mark_atom_dirty(sctx, &sctx->cb_render_state);
|
|
|
|
|
2015-12-23 14:36:05 +00:00
|
|
|
if (sctx->ps_db_shader_control != db_shader_control) {
|
|
|
|
sctx->ps_db_shader_control = db_shader_control;
|
2015-10-22 21:17:28 +01:00
|
|
|
si_mark_atom_dirty(sctx, &sctx->db_render_state);
|
|
|
|
}
|
|
|
|
|
2016-11-13 02:17:46 +00:00
|
|
|
if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
|
|
|
|
sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
|
2015-10-22 21:17:28 +01:00
|
|
|
si_mark_atom_dirty(sctx, &sctx->msaa_config);
|
|
|
|
|
|
|
|
if (sctx->b.chip_class == SI)
|
|
|
|
si_mark_atom_dirty(sctx, &sctx->db_render_state);
|
2016-07-06 15:33:43 +01:00
|
|
|
|
2016-07-16 19:41:18 +01:00
|
|
|
if (sctx->framebuffer.nr_samples <= 1)
|
2016-07-06 15:33:43 +01:00
|
|
|
si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
|
2015-10-22 21:17:28 +01:00
|
|
|
}
|
2015-09-28 16:21:10 +01:00
|
|
|
}
|
2015-09-28 16:01:21 +01:00
|
|
|
|
2015-09-10 17:42:22 +01:00
|
|
|
if (si_pm4_state_changed(sctx, ls) ||
|
|
|
|
si_pm4_state_changed(sctx, hs) ||
|
|
|
|
si_pm4_state_changed(sctx, es) ||
|
|
|
|
si_pm4_state_changed(sctx, gs) ||
|
|
|
|
si_pm4_state_changed(sctx, vs) ||
|
|
|
|
si_pm4_state_changed(sctx, ps)) {
|
2015-09-10 17:40:51 +01:00
|
|
|
if (!si_update_spi_tmpring_size(sctx))
|
|
|
|
return false;
|
2014-12-10 14:13:59 +00:00
|
|
|
}
|
2016-08-02 10:51:21 +01:00
|
|
|
|
2017-01-24 22:28:32 +00:00
|
|
|
if (sctx->b.chip_class >= CIK)
|
|
|
|
si_mark_atom_dirty(sctx, &sctx->prefetch_L2);
|
|
|
|
|
2016-08-02 10:51:21 +01:00
|
|
|
sctx->do_update_shaders = false;
|
2015-09-10 17:27:53 +01:00
|
|
|
return true;
|
2014-12-07 16:53:56 +00:00
|
|
|
}
|
|
|
|
|
2017-01-26 01:56:15 +00:00
|
|
|
static void si_emit_scratch_state(struct si_context *sctx,
|
|
|
|
struct r600_atom *atom)
|
|
|
|
{
|
|
|
|
struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
|
|
|
|
|
|
|
|
radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
|
|
|
|
sctx->spi_tmpring_size);
|
|
|
|
|
|
|
|
if (sctx->scratch_buffer) {
|
|
|
|
radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
|
|
|
|
sctx->scratch_buffer, RADEON_USAGE_READWRITE,
|
|
|
|
RADEON_PRIO_SCRATCH_BUFFER);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-12-07 16:53:56 +00:00
|
|
|
void si_init_shader_functions(struct si_context *sctx)
|
|
|
|
{
|
2015-08-30 02:53:39 +01:00
|
|
|
si_init_atom(sctx, &sctx->spi_map, &sctx->atoms.s.spi_map, si_emit_spi_map);
|
2017-01-26 01:56:15 +00:00
|
|
|
si_init_atom(sctx, &sctx->scratch_state, &sctx->atoms.s.scratch_state,
|
|
|
|
si_emit_scratch_state);
|
2015-08-30 02:17:30 +01:00
|
|
|
|
2015-10-09 00:14:12 +01:00
|
|
|
sctx->b.b.create_vs_state = si_create_shader_selector;
|
|
|
|
sctx->b.b.create_tcs_state = si_create_shader_selector;
|
|
|
|
sctx->b.b.create_tes_state = si_create_shader_selector;
|
|
|
|
sctx->b.b.create_gs_state = si_create_shader_selector;
|
|
|
|
sctx->b.b.create_fs_state = si_create_shader_selector;
|
2014-12-07 16:53:56 +00:00
|
|
|
|
|
|
|
sctx->b.b.bind_vs_state = si_bind_vs_shader;
|
2014-09-18 21:50:52 +01:00
|
|
|
sctx->b.b.bind_tcs_state = si_bind_tcs_shader;
|
|
|
|
sctx->b.b.bind_tes_state = si_bind_tes_shader;
|
2014-12-07 16:53:56 +00:00
|
|
|
sctx->b.b.bind_gs_state = si_bind_gs_shader;
|
|
|
|
sctx->b.b.bind_fs_state = si_bind_ps_shader;
|
|
|
|
|
2015-10-09 00:08:42 +01:00
|
|
|
sctx->b.b.delete_vs_state = si_delete_shader_selector;
|
|
|
|
sctx->b.b.delete_tcs_state = si_delete_shader_selector;
|
|
|
|
sctx->b.b.delete_tes_state = si_delete_shader_selector;
|
|
|
|
sctx->b.b.delete_gs_state = si_delete_shader_selector;
|
|
|
|
sctx->b.b.delete_fs_state = si_delete_shader_selector;
|
2014-12-07 16:53:56 +00:00
|
|
|
}
|