radeonsi: remove all varyings for depth-only rendering or rasterization off
Tested-by: Edmondo Tommasina <edmondo.tommasina@gmail.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
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@ -167,6 +167,7 @@ struct si_framebuffer {
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unsigned nr_samples;
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unsigned log_samples;
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unsigned compressed_cb_mask;
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unsigned colorbuf_enabled_4bit;
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unsigned spi_shader_col_format;
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unsigned spi_shader_col_format_alpha;
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unsigned spi_shader_col_format_blend;
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@ -2360,6 +2360,7 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
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si_dec_framebuffer_counters(&sctx->framebuffer.state);
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util_copy_framebuffer_state(&sctx->framebuffer.state, state);
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sctx->framebuffer.colorbuf_enabled_4bit = 0;
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sctx->framebuffer.spi_shader_col_format = 0;
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sctx->framebuffer.spi_shader_col_format_alpha = 0;
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sctx->framebuffer.spi_shader_col_format_blend = 0;
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@ -2382,6 +2383,7 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
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si_initialize_color_surface(sctx, surf);
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}
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sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
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sctx->framebuffer.spi_shader_col_format |=
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surf->spi_shader_col_format << (i * 4);
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sctx->framebuffer.spi_shader_col_format_alpha |=
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@ -867,7 +867,24 @@ static void si_shader_selector_key_hw_vs(struct si_context *sctx,
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!vs->info.culldist_writemask;
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/* Find out if PS is disabled. */
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bool ps_disabled = ps == NULL;
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bool ps_disabled = true;
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if (ps) {
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bool ps_modifies_zs = ps->info.uses_kill ||
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ps->info.writes_z ||
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ps->info.writes_stencil ||
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ps->info.writes_samplemask ||
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si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
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unsigned ps_colormask = sctx->framebuffer.colorbuf_enabled_4bit &
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sctx->queued.named.blend->cb_target_mask;
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if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
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ps_colormask &= ps->colors_written_4bit;
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ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
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(!ps_colormask &&
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!ps_modifies_zs &&
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!ps->info.writes_memory);
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}
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/* Find out which VS outputs aren't used by the PS. */
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uint64_t outputs_written = vs->outputs_written;
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