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radeonsi: eliminate PS OUT[1] if dual src blending is off and CB1 is not bound 

All VP DX9 ports benefit from this.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák 2016-08-10 12:19:49 +02:00
parent 3de8ffe836
commit e722b90bc9
2 changed files with 7 additions and 11 deletions
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11
src/gallium/drivers/radeonsi/si_state.c
View File

@ -2350,17 +2350,6 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
vi_separate_dcc_start_query(ctx, rtex);
}
}
/* Set the second SPI format for possible dual-src blending. */
if (i == 1 && surf) {
sctx->framebuffer.spi_shader_col_format |=
surf->spi_shader_col_format << (i * 4);
sctx->framebuffer.spi_shader_col_format_alpha |=
surf->spi_shader_col_format_alpha << (i * 4);
sctx->framebuffer.spi_shader_col_format_blend |=
surf->spi_shader_col_format_blend << (i * 4);
sctx->framebuffer.spi_shader_col_format_blend_alpha |=
surf->spi_shader_col_format_blend_alpha << (i * 4);
}
if (state->zsbuf) {
surf = (struct r600_surface*)state->zsbuf;

7
src/gallium/drivers/radeonsi/si_state_shaders.c
View File

@ -900,6 +900,13 @@ static inline void si_shader_selector_key(struct pipe_context *ctx,
sctx->framebuffer.spi_shader_col_format_alpha) |
(~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
sctx->framebuffer.spi_shader_col_format);
/* The output for dual source blending should have
* the same format as the first output.
*/
if (blend->dual_src_blend)
key->ps.epilog.spi_shader_col_format |=
(key->ps.epilog.spi_shader_col_format & 0xf) << 4;
} else
key->ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;