radeonsi: remove the gs_rings state, add the registers to init_config
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com>
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87c1e9e19c
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@ -49,7 +49,6 @@ static void si_destroy_context(struct pipe_context *context)
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sctx->b.ws->fence_reference(&sctx->last_gfx_fence, NULL);
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si_pm4_free_state(sctx, sctx->init_config, ~0);
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si_pm4_delete_state(sctx, gs_rings, sctx->gs_rings);
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si_pm4_delete_state(sctx, tf_ring, sctx->tf_state);
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for (i = 0; i < Elements(sctx->vgt_shader_config); i++)
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si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
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@ -201,7 +201,6 @@ struct si_context {
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/* VGT states. */
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struct si_pm4_state *vgt_shader_config[4];
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struct si_pm4_state *gs_rings;
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struct pipe_resource *esgs_ring;
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struct pipe_resource *gsvs_ring;
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struct si_pm4_state *tf_state;
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@ -96,7 +96,6 @@ union si_state {
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struct si_pm4_state *hs;
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struct si_pm4_state *es;
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struct si_pm4_state *gs;
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struct si_pm4_state *gs_rings;
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struct si_pm4_state *tf_ring;
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struct si_pm4_state *vgt_shader_config;
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struct si_pm4_state *vs;
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@ -1050,8 +1050,7 @@ static void si_init_gs_rings(struct si_context *sctx)
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unsigned esgs_ring_size = 128 * 1024;
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unsigned gsvs_ring_size = 60 * 1024 * 1024;
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assert(!sctx->gs_rings);
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sctx->gs_rings = CALLOC_STRUCT(si_pm4_state);
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assert(!sctx->esgs_ring && !sctx->gsvs_ring);
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sctx->esgs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
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PIPE_USAGE_DEFAULT, esgs_ring_size);
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@ -1059,6 +1058,7 @@ static void si_init_gs_rings(struct si_context *sctx)
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sctx->gsvs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
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PIPE_USAGE_DEFAULT, gsvs_ring_size);
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/* Append these registers to the init config state. */
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if (sctx->b.chip_class >= CIK) {
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if (sctx->b.chip_class >= VI) {
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/* The maximum sizes are 63.999 MB on VI, because
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@ -1066,17 +1066,23 @@ static void si_init_gs_rings(struct si_context *sctx)
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assert(esgs_ring_size / 256 < (1 << 18));
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assert(gsvs_ring_size / 256 < (1 << 18));
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}
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si_pm4_set_reg(sctx->gs_rings, R_030900_VGT_ESGS_RING_SIZE,
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si_pm4_set_reg(sctx->init_config, R_030900_VGT_ESGS_RING_SIZE,
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esgs_ring_size / 256);
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si_pm4_set_reg(sctx->gs_rings, R_030904_VGT_GSVS_RING_SIZE,
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si_pm4_set_reg(sctx->init_config, R_030904_VGT_GSVS_RING_SIZE,
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gsvs_ring_size / 256);
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} else {
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si_pm4_set_reg(sctx->gs_rings, R_0088C8_VGT_ESGS_RING_SIZE,
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si_pm4_set_reg(sctx->init_config, R_0088C8_VGT_ESGS_RING_SIZE,
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esgs_ring_size / 256);
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si_pm4_set_reg(sctx->gs_rings, R_0088CC_VGT_GSVS_RING_SIZE,
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si_pm4_set_reg(sctx->init_config, R_0088CC_VGT_GSVS_RING_SIZE,
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gsvs_ring_size / 256);
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}
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/* Flush the context to re-emit the init_config state.
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* This is done only once in a lifetime of a context.
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*/
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sctx->b.initial_gfx_cs_size = 0; /* force flush */
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si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
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si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_ESGS,
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sctx->esgs_ring, 0, esgs_ring_size,
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true, true, 4, 64, 0);
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@ -1113,8 +1119,8 @@ static void si_update_gs_rings(struct si_context *sctx)
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si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS_3,
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sctx->gsvs_ring, gsvs_itemsize,
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64, true, true, 4, 16, offset);
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}
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/**
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* @returns 1 if \p sel has been updated to use a new scratch buffer and 0
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* otherwise.
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@ -1412,16 +1418,11 @@ void si_update_shaders(struct si_context *sctx)
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si_pm4_bind_state(sctx, vs, sctx->gs_shader->current->gs_copy_shader->pm4);
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si_update_so(sctx, sctx->gs_shader);
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if (!sctx->gs_rings)
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if (!sctx->gsvs_ring)
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si_init_gs_rings(sctx);
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if (sctx->emitted.named.gs_rings != sctx->gs_rings)
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sctx->b.flags |= SI_CONTEXT_VGT_FLUSH;
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si_pm4_bind_state(sctx, gs_rings, sctx->gs_rings);
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si_update_gs_rings(sctx);
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} else {
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si_pm4_bind_state(sctx, gs_rings, NULL);
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si_pm4_bind_state(sctx, gs, NULL);
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si_pm4_bind_state(sctx, es, NULL);
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}
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