2011-05-26 17:57:36 +01:00
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/*
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* Copyright © 2010 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "brw_context.h"
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2014-05-19 18:20:37 +01:00
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#include "brw_cfg.h"
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2015-11-23 02:27:42 +00:00
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#include "brw_eu.h"
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2015-11-10 22:35:27 +00:00
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#include "brw_fs.h"
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2015-04-07 23:15:09 +01:00
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#include "brw_nir.h"
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2015-11-17 09:30:35 +00:00
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#include "brw_vec4_tes.h"
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2015-11-23 02:27:42 +00:00
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#include "main/uniforms.h"
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2015-04-16 20:01:09 +01:00
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2015-11-23 05:54:28 +00:00
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extern "C" void
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2015-10-07 00:11:08 +01:00
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brw_mark_surface_used(struct brw_stage_prog_data *prog_data,
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unsigned surf_index)
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{
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assert(surf_index < BRW_MAX_SURFACES);
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prog_data->binding_table.size_bytes =
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MAX2(prog_data->binding_table.size_bytes, (surf_index + 1) * 4);
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}
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2014-06-30 00:02:59 +01:00
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enum brw_reg_type
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2011-05-26 18:01:10 +01:00
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brw_type_for_base_type(const struct glsl_type *type)
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{
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switch (type->base_type) {
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case GLSL_TYPE_FLOAT:
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return BRW_REGISTER_TYPE_F;
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case GLSL_TYPE_INT:
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2014-10-16 20:16:08 +01:00
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case GLSL_TYPE_BOOL:
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2015-07-21 05:22:11 +01:00
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case GLSL_TYPE_SUBROUTINE:
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2014-12-02 20:30:27 +00:00
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return BRW_REGISTER_TYPE_D;
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2011-05-26 18:01:10 +01:00
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case GLSL_TYPE_UINT:
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return BRW_REGISTER_TYPE_UD;
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case GLSL_TYPE_ARRAY:
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2011-11-09 03:26:38 +00:00
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return brw_type_for_base_type(type->fields.array);
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2011-05-26 18:01:10 +01:00
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case GLSL_TYPE_STRUCT:
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case GLSL_TYPE_SAMPLER:
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2013-10-20 20:35:47 +01:00
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case GLSL_TYPE_ATOMIC_UINT:
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2011-05-26 18:01:10 +01:00
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/* These should be overridden with the type of the member when
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* dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
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* way to trip up if we don't.
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*/
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return BRW_REGISTER_TYPE_UD;
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2013-11-25 21:50:47 +00:00
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case GLSL_TYPE_IMAGE:
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return BRW_REGISTER_TYPE_UD;
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2014-09-16 10:02:22 +01:00
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case GLSL_TYPE_DOUBLE:
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return BRW_REGISTER_TYPE_DF;
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2012-12-11 20:56:03 +00:00
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case GLSL_TYPE_VOID:
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case GLSL_TYPE_ERROR:
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2012-12-11 20:11:16 +00:00
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case GLSL_TYPE_INTERFACE:
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2016-02-10 02:17:06 +00:00
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case GLSL_TYPE_FUNCTION:
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2014-06-29 22:54:01 +01:00
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unreachable("not reached");
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2011-05-26 18:01:10 +01:00
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}
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2012-12-11 20:56:03 +00:00
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return BRW_REGISTER_TYPE_F;
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2011-05-26 18:01:10 +01:00
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}
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2014-06-30 01:50:20 +01:00
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enum brw_conditional_mod
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2011-05-26 18:01:10 +01:00
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brw_conditional_for_comparison(unsigned int op)
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{
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switch (op) {
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case ir_binop_less:
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return BRW_CONDITIONAL_L;
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case ir_binop_greater:
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return BRW_CONDITIONAL_G;
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case ir_binop_lequal:
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return BRW_CONDITIONAL_LE;
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case ir_binop_gequal:
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return BRW_CONDITIONAL_GE;
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case ir_binop_equal:
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case ir_binop_all_equal: /* same as equal for scalars */
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return BRW_CONDITIONAL_Z;
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case ir_binop_nequal:
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case ir_binop_any_nequal: /* same as nequal for scalars */
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return BRW_CONDITIONAL_NZ;
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default:
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2014-06-29 22:54:01 +01:00
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unreachable("not reached: bad operation for comparison");
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2011-05-26 18:01:10 +01:00
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}
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}
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2011-05-02 17:45:40 +01:00
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uint32_t
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brw_math_function(enum opcode op)
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{
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switch (op) {
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case SHADER_OPCODE_RCP:
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return BRW_MATH_FUNCTION_INV;
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case SHADER_OPCODE_RSQ:
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return BRW_MATH_FUNCTION_RSQ;
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case SHADER_OPCODE_SQRT:
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return BRW_MATH_FUNCTION_SQRT;
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case SHADER_OPCODE_EXP2:
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return BRW_MATH_FUNCTION_EXP;
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case SHADER_OPCODE_LOG2:
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return BRW_MATH_FUNCTION_LOG;
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case SHADER_OPCODE_POW:
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return BRW_MATH_FUNCTION_POW;
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case SHADER_OPCODE_SIN:
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return BRW_MATH_FUNCTION_SIN;
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case SHADER_OPCODE_COS:
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return BRW_MATH_FUNCTION_COS;
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2011-09-29 01:37:54 +01:00
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case SHADER_OPCODE_INT_QUOTIENT:
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return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
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case SHADER_OPCODE_INT_REMAINDER:
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return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
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2011-05-02 17:45:40 +01:00
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default:
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2014-06-29 22:54:01 +01:00
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unreachable("not reached: unknown math function");
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2011-05-02 17:45:40 +01:00
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}
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}
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2011-10-26 21:51:28 +01:00
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uint32_t
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2015-04-14 22:23:40 +01:00
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brw_texture_offset(int *offsets, unsigned num_components)
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2011-10-26 21:51:28 +01:00
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{
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2014-08-04 23:20:38 +01:00
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if (!offsets) return 0; /* nonconstant offset; caller will handle it. */
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2011-10-26 21:51:28 +01:00
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/* Combine all three offsets into a single unsigned dword:
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*
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* bits 11:8 - U Offset (X component)
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* bits 7:4 - V Offset (Y component)
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* bits 3:0 - R Offset (Z component)
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*/
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unsigned offset_bits = 0;
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2014-08-04 23:20:38 +01:00
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for (unsigned i = 0; i < num_components; i++) {
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2011-10-26 21:51:28 +01:00
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const unsigned shift = 4 * (2 - i);
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offset_bits |= (offsets[i] << shift) & (0xF << shift);
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}
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return offset_bits;
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}
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2013-03-12 00:36:54 +00:00
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const char *
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2016-08-22 23:01:08 +01:00
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brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
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2013-03-12 00:36:54 +00:00
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{
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switch (op) {
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2015-06-29 22:03:55 +01:00
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case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
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2016-05-09 23:58:20 +01:00
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/* The DO instruction doesn't exist on Gen6+, but we use it to mark the
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* start of a loop in the IR.
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*/
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if (devinfo->gen >= 6 && op == BRW_OPCODE_DO)
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return "do";
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2016-04-28 08:19:14 +01:00
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assert(brw_opcode_desc(devinfo, op)->name);
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return brw_opcode_desc(devinfo, op)->name;
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2013-03-12 00:36:54 +00:00
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case FS_OPCODE_FB_WRITE:
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return "fb_write";
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2015-07-27 14:14:36 +01:00
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case FS_OPCODE_FB_WRITE_LOGICAL:
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return "fb_write_logical";
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2014-12-06 22:16:13 +00:00
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case FS_OPCODE_REP_FB_WRITE:
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return "rep_fb_write";
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2016-07-22 00:52:33 +01:00
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case FS_OPCODE_FB_READ:
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return "fb_read";
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2016-07-22 00:55:45 +01:00
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case FS_OPCODE_FB_READ_LOGICAL:
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return "fb_read_logical";
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2013-03-12 00:36:54 +00:00
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case SHADER_OPCODE_RCP:
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return "rcp";
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case SHADER_OPCODE_RSQ:
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return "rsq";
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case SHADER_OPCODE_SQRT:
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return "sqrt";
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case SHADER_OPCODE_EXP2:
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return "exp2";
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case SHADER_OPCODE_LOG2:
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return "log2";
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case SHADER_OPCODE_POW:
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return "pow";
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case SHADER_OPCODE_INT_QUOTIENT:
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return "int_quot";
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case SHADER_OPCODE_INT_REMAINDER:
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return "int_rem";
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case SHADER_OPCODE_SIN:
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return "sin";
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case SHADER_OPCODE_COS:
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return "cos";
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case SHADER_OPCODE_TEX:
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return "tex";
|
i965/fs: Define logical texture sampling opcodes.
Each logical variant is largely equivalent to the original opcode but
instead of taking a single payload source it expects the arguments
separately as individual sources, like:
tex_logical dst, coordinates, shadow_c, lod, lod2,
sample_index, mcs, sampler, offset,
num_coordinate_components, num_grad_components
This patch defines the opcodes and usual instruction boilerplate,
including a placeholder lowering function provided mostly as
documentation for their source registers.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-07-21 16:42:27 +01:00
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case SHADER_OPCODE_TEX_LOGICAL:
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return "tex_logical";
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2013-03-12 00:36:54 +00:00
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case SHADER_OPCODE_TXD:
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return "txd";
|
i965/fs: Define logical texture sampling opcodes.
Each logical variant is largely equivalent to the original opcode but
instead of taking a single payload source it expects the arguments
separately as individual sources, like:
tex_logical dst, coordinates, shadow_c, lod, lod2,
sample_index, mcs, sampler, offset,
num_coordinate_components, num_grad_components
This patch defines the opcodes and usual instruction boilerplate,
including a placeholder lowering function provided mostly as
documentation for their source registers.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-07-21 16:42:27 +01:00
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case SHADER_OPCODE_TXD_LOGICAL:
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return "txd_logical";
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2013-03-12 00:36:54 +00:00
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case SHADER_OPCODE_TXF:
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return "txf";
|
i965/fs: Define logical texture sampling opcodes.
Each logical variant is largely equivalent to the original opcode but
instead of taking a single payload source it expects the arguments
separately as individual sources, like:
tex_logical dst, coordinates, shadow_c, lod, lod2,
sample_index, mcs, sampler, offset,
num_coordinate_components, num_grad_components
This patch defines the opcodes and usual instruction boilerplate,
including a placeholder lowering function provided mostly as
documentation for their source registers.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-07-21 16:42:27 +01:00
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case SHADER_OPCODE_TXF_LOGICAL:
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return "txf_logical";
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2016-05-04 23:46:45 +01:00
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case SHADER_OPCODE_TXF_LZ:
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return "txf_lz";
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2013-03-12 00:36:54 +00:00
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case SHADER_OPCODE_TXL:
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return "txl";
|
i965/fs: Define logical texture sampling opcodes.
Each logical variant is largely equivalent to the original opcode but
instead of taking a single payload source it expects the arguments
separately as individual sources, like:
tex_logical dst, coordinates, shadow_c, lod, lod2,
sample_index, mcs, sampler, offset,
num_coordinate_components, num_grad_components
This patch defines the opcodes and usual instruction boilerplate,
including a placeholder lowering function provided mostly as
documentation for their source registers.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-07-21 16:42:27 +01:00
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case SHADER_OPCODE_TXL_LOGICAL:
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return "txl_logical";
|
2016-05-04 23:46:45 +01:00
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case SHADER_OPCODE_TXL_LZ:
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return "txl_lz";
|
2013-03-12 00:36:54 +00:00
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case SHADER_OPCODE_TXS:
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return "txs";
|
i965/fs: Define logical texture sampling opcodes.
Each logical variant is largely equivalent to the original opcode but
instead of taking a single payload source it expects the arguments
separately as individual sources, like:
tex_logical dst, coordinates, shadow_c, lod, lod2,
sample_index, mcs, sampler, offset,
num_coordinate_components, num_grad_components
This patch defines the opcodes and usual instruction boilerplate,
including a placeholder lowering function provided mostly as
documentation for their source registers.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-07-21 16:42:27 +01:00
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case SHADER_OPCODE_TXS_LOGICAL:
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return "txs_logical";
|
2013-03-12 00:36:54 +00:00
|
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case FS_OPCODE_TXB:
|
|
|
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return "txb";
|
i965/fs: Define logical texture sampling opcodes.
Each logical variant is largely equivalent to the original opcode but
instead of taking a single payload source it expects the arguments
separately as individual sources, like:
tex_logical dst, coordinates, shadow_c, lod, lod2,
sample_index, mcs, sampler, offset,
num_coordinate_components, num_grad_components
This patch defines the opcodes and usual instruction boilerplate,
including a placeholder lowering function provided mostly as
documentation for their source registers.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-07-21 16:42:27 +01:00
|
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case FS_OPCODE_TXB_LOGICAL:
|
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|
|
return "txb_logical";
|
2013-12-10 14:36:31 +00:00
|
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case SHADER_OPCODE_TXF_CMS:
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|
|
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return "txf_cms";
|
i965/fs: Define logical texture sampling opcodes.
Each logical variant is largely equivalent to the original opcode but
instead of taking a single payload source it expects the arguments
separately as individual sources, like:
tex_logical dst, coordinates, shadow_c, lod, lod2,
sample_index, mcs, sampler, offset,
num_coordinate_components, num_grad_components
This patch defines the opcodes and usual instruction boilerplate,
including a placeholder lowering function provided mostly as
documentation for their source registers.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-07-21 16:42:27 +01:00
|
|
|
case SHADER_OPCODE_TXF_CMS_LOGICAL:
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|
|
return "txf_cms_logical";
|
2015-09-08 15:52:09 +01:00
|
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|
case SHADER_OPCODE_TXF_CMS_W:
|
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|
|
return "txf_cms_w";
|
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case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
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|
|
return "txf_cms_w_logical";
|
2013-12-10 14:38:15 +00:00
|
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|
case SHADER_OPCODE_TXF_UMS:
|
|
|
|
return "txf_ums";
|
i965/fs: Define logical texture sampling opcodes.
Each logical variant is largely equivalent to the original opcode but
instead of taking a single payload source it expects the arguments
separately as individual sources, like:
tex_logical dst, coordinates, shadow_c, lod, lod2,
sample_index, mcs, sampler, offset,
num_coordinate_components, num_grad_components
This patch defines the opcodes and usual instruction boilerplate,
including a placeholder lowering function provided mostly as
documentation for their source registers.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-07-21 16:42:27 +01:00
|
|
|
case SHADER_OPCODE_TXF_UMS_LOGICAL:
|
|
|
|
return "txf_ums_logical";
|
2013-11-29 21:32:16 +00:00
|
|
|
case SHADER_OPCODE_TXF_MCS:
|
|
|
|
return "txf_mcs";
|
i965/fs: Define logical texture sampling opcodes.
Each logical variant is largely equivalent to the original opcode but
instead of taking a single payload source it expects the arguments
separately as individual sources, like:
tex_logical dst, coordinates, shadow_c, lod, lod2,
sample_index, mcs, sampler, offset,
num_coordinate_components, num_grad_components
This patch defines the opcodes and usual instruction boilerplate,
including a placeholder lowering function provided mostly as
documentation for their source registers.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-07-21 16:42:27 +01:00
|
|
|
case SHADER_OPCODE_TXF_MCS_LOGICAL:
|
|
|
|
return "txf_mcs_logical";
|
2014-12-06 22:16:13 +00:00
|
|
|
case SHADER_OPCODE_LOD:
|
|
|
|
return "lod";
|
i965/fs: Define logical texture sampling opcodes.
Each logical variant is largely equivalent to the original opcode but
instead of taking a single payload source it expects the arguments
separately as individual sources, like:
tex_logical dst, coordinates, shadow_c, lod, lod2,
sample_index, mcs, sampler, offset,
num_coordinate_components, num_grad_components
This patch defines the opcodes and usual instruction boilerplate,
including a placeholder lowering function provided mostly as
documentation for their source registers.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-07-21 16:42:27 +01:00
|
|
|
case SHADER_OPCODE_LOD_LOGICAL:
|
|
|
|
return "lod_logical";
|
2013-10-08 09:34:22 +01:00
|
|
|
case SHADER_OPCODE_TG4:
|
|
|
|
return "tg4";
|
i965/fs: Define logical texture sampling opcodes.
Each logical variant is largely equivalent to the original opcode but
instead of taking a single payload source it expects the arguments
separately as individual sources, like:
tex_logical dst, coordinates, shadow_c, lod, lod2,
sample_index, mcs, sampler, offset,
num_coordinate_components, num_grad_components
This patch defines the opcodes and usual instruction boilerplate,
including a placeholder lowering function provided mostly as
documentation for their source registers.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-07-21 16:42:27 +01:00
|
|
|
case SHADER_OPCODE_TG4_LOGICAL:
|
|
|
|
return "tg4_logical";
|
2013-10-08 09:42:10 +01:00
|
|
|
case SHADER_OPCODE_TG4_OFFSET:
|
|
|
|
return "tg4_offset";
|
i965/fs: Define logical texture sampling opcodes.
Each logical variant is largely equivalent to the original opcode but
instead of taking a single payload source it expects the arguments
separately as individual sources, like:
tex_logical dst, coordinates, shadow_c, lod, lod2,
sample_index, mcs, sampler, offset,
num_coordinate_components, num_grad_components
This patch defines the opcodes and usual instruction boilerplate,
including a placeholder lowering function provided mostly as
documentation for their source registers.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-07-21 16:42:27 +01:00
|
|
|
case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
|
|
|
|
return "tg4_offset_logical";
|
2015-08-12 01:37:32 +01:00
|
|
|
case SHADER_OPCODE_SAMPLEINFO:
|
|
|
|
return "sampleinfo";
|
2016-05-20 08:37:37 +01:00
|
|
|
case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
|
|
|
|
return "sampleinfo_logical";
|
i965/fs: Define logical texture sampling opcodes.
Each logical variant is largely equivalent to the original opcode but
instead of taking a single payload source it expects the arguments
separately as individual sources, like:
tex_logical dst, coordinates, shadow_c, lod, lod2,
sample_index, mcs, sampler, offset,
num_coordinate_components, num_grad_components
This patch defines the opcodes and usual instruction boilerplate,
including a placeholder lowering function provided mostly as
documentation for their source registers.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-07-21 16:42:27 +01:00
|
|
|
|
2014-06-14 11:13:27 +01:00
|
|
|
case SHADER_OPCODE_SHADER_TIME_ADD:
|
|
|
|
return "shader_time_add";
|
2013-03-12 00:36:54 +00:00
|
|
|
|
2014-12-06 22:16:13 +00:00
|
|
|
case SHADER_OPCODE_UNTYPED_ATOMIC:
|
|
|
|
return "untyped_atomic";
|
2015-07-21 16:45:32 +01:00
|
|
|
case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
|
|
|
|
return "untyped_atomic_logical";
|
2014-12-06 22:16:13 +00:00
|
|
|
case SHADER_OPCODE_UNTYPED_SURFACE_READ:
|
|
|
|
return "untyped_surface_read";
|
2015-07-21 16:45:32 +01:00
|
|
|
case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
|
|
|
|
return "untyped_surface_read_logical";
|
2015-04-23 12:24:14 +01:00
|
|
|
case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
|
|
|
|
return "untyped_surface_write";
|
2015-07-21 16:45:32 +01:00
|
|
|
case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
|
|
|
|
return "untyped_surface_write_logical";
|
2015-04-23 12:28:25 +01:00
|
|
|
case SHADER_OPCODE_TYPED_ATOMIC:
|
|
|
|
return "typed_atomic";
|
2015-07-21 16:45:32 +01:00
|
|
|
case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
|
|
|
|
return "typed_atomic_logical";
|
2015-04-23 12:28:25 +01:00
|
|
|
case SHADER_OPCODE_TYPED_SURFACE_READ:
|
|
|
|
return "typed_surface_read";
|
2015-07-21 16:45:32 +01:00
|
|
|
case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
|
|
|
|
return "typed_surface_read_logical";
|
2015-04-23 12:28:25 +01:00
|
|
|
case SHADER_OPCODE_TYPED_SURFACE_WRITE:
|
|
|
|
return "typed_surface_write";
|
2015-07-21 16:45:32 +01:00
|
|
|
case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
|
|
|
|
return "typed_surface_write_logical";
|
2015-04-23 12:30:28 +01:00
|
|
|
case SHADER_OPCODE_MEMORY_FENCE:
|
|
|
|
return "memory_fence";
|
2014-12-06 22:16:13 +00:00
|
|
|
|
2014-05-28 02:47:40 +01:00
|
|
|
case SHADER_OPCODE_LOAD_PAYLOAD:
|
|
|
|
return "load_payload";
|
2016-05-05 10:40:41 +01:00
|
|
|
case FS_OPCODE_PACK:
|
|
|
|
return "pack";
|
2014-05-28 02:47:40 +01:00
|
|
|
|
2013-10-16 19:45:06 +01:00
|
|
|
case SHADER_OPCODE_GEN4_SCRATCH_READ:
|
|
|
|
return "gen4_scratch_read";
|
|
|
|
case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
|
|
|
|
return "gen4_scratch_write";
|
2013-10-16 19:51:22 +01:00
|
|
|
case SHADER_OPCODE_GEN7_SCRATCH_READ:
|
|
|
|
return "gen7_scratch_read";
|
2014-10-21 07:00:50 +01:00
|
|
|
case SHADER_OPCODE_URB_WRITE_SIMD8:
|
|
|
|
return "gen8_urb_write_simd8";
|
2015-05-06 08:04:10 +01:00
|
|
|
case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
|
|
|
|
return "gen8_urb_write_simd8_per_slot";
|
|
|
|
case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
|
|
|
|
return "gen8_urb_write_simd8_masked";
|
|
|
|
case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
|
|
|
|
return "gen8_urb_write_simd8_masked_per_slot";
|
2015-09-29 22:32:02 +01:00
|
|
|
case SHADER_OPCODE_URB_READ_SIMD8:
|
|
|
|
return "urb_read_simd8";
|
2015-11-07 09:37:33 +00:00
|
|
|
case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
|
|
|
|
return "urb_read_simd8_per_slot";
|
2013-10-16 19:45:06 +01:00
|
|
|
|
2015-04-23 12:42:53 +01:00
|
|
|
case SHADER_OPCODE_FIND_LIVE_CHANNEL:
|
|
|
|
return "find_live_channel";
|
2015-02-20 18:14:24 +00:00
|
|
|
case SHADER_OPCODE_BROADCAST:
|
|
|
|
return "broadcast";
|
|
|
|
|
2015-02-12 01:42:43 +00:00
|
|
|
case VEC4_OPCODE_MOV_BYTES:
|
|
|
|
return "mov_bytes";
|
2014-03-10 20:26:30 +00:00
|
|
|
case VEC4_OPCODE_PACK_BYTES:
|
|
|
|
return "pack_bytes";
|
2014-10-24 07:22:09 +01:00
|
|
|
case VEC4_OPCODE_UNPACK_UNIFORM:
|
|
|
|
return "unpack_uniform";
|
2014-03-10 20:26:30 +00:00
|
|
|
|
2014-11-08 09:39:14 +00:00
|
|
|
case FS_OPCODE_DDX_COARSE:
|
|
|
|
return "ddx_coarse";
|
|
|
|
case FS_OPCODE_DDX_FINE:
|
|
|
|
return "ddx_fine";
|
|
|
|
case FS_OPCODE_DDY_COARSE:
|
|
|
|
return "ddy_coarse";
|
|
|
|
case FS_OPCODE_DDY_FINE:
|
|
|
|
return "ddy_fine";
|
2013-03-12 00:36:54 +00:00
|
|
|
|
|
|
|
case FS_OPCODE_CINTERP:
|
|
|
|
return "cinterp";
|
|
|
|
case FS_OPCODE_LINTERP:
|
|
|
|
return "linterp";
|
|
|
|
|
2015-04-25 00:23:46 +01:00
|
|
|
case FS_OPCODE_PIXEL_X:
|
|
|
|
return "pixel_x";
|
|
|
|
case FS_OPCODE_PIXEL_Y:
|
|
|
|
return "pixel_y";
|
|
|
|
|
2015-04-13 15:55:49 +01:00
|
|
|
case FS_OPCODE_GET_BUFFER_SIZE:
|
|
|
|
return "fs_get_buffer_size";
|
|
|
|
|
2013-03-12 00:36:54 +00:00
|
|
|
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
|
|
|
|
return "uniform_pull_const";
|
|
|
|
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
|
|
|
|
return "uniform_pull_const_gen7";
|
2016-05-20 21:03:31 +01:00
|
|
|
case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
|
|
|
|
return "varying_pull_const_gen4";
|
2013-03-12 00:36:54 +00:00
|
|
|
case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
|
|
|
|
return "varying_pull_const_gen7";
|
2016-05-18 07:18:38 +01:00
|
|
|
case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL:
|
|
|
|
return "varying_pull_const_logical";
|
2013-03-12 00:36:54 +00:00
|
|
|
|
|
|
|
case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
|
|
|
|
return "mov_dispatch_to_flags";
|
|
|
|
case FS_OPCODE_DISCARD_JUMP:
|
|
|
|
return "discard_jump";
|
|
|
|
|
2014-12-06 21:34:13 +00:00
|
|
|
case FS_OPCODE_SET_SAMPLE_ID:
|
|
|
|
return "set_sample_id";
|
2013-03-12 00:36:54 +00:00
|
|
|
case FS_OPCODE_SET_SIMD4X2_OFFSET:
|
|
|
|
return "set_simd4x2_offset";
|
|
|
|
|
|
|
|
case FS_OPCODE_PACK_HALF_2x16_SPLIT:
|
|
|
|
return "pack_half_2x16_split";
|
|
|
|
case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
|
|
|
|
return "unpack_half_2x16_split_x";
|
|
|
|
case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
|
|
|
|
return "unpack_half_2x16_split_y";
|
|
|
|
|
2013-03-28 06:19:39 +00:00
|
|
|
case FS_OPCODE_PLACEHOLDER_HALT:
|
|
|
|
return "placeholder_halt";
|
|
|
|
|
2014-12-06 21:07:16 +00:00
|
|
|
case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
|
|
|
|
return "interp_sample";
|
|
|
|
case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
|
|
|
|
return "interp_shared_offset";
|
|
|
|
case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
|
|
|
|
return "interp_per_slot_offset";
|
|
|
|
|
2013-03-12 00:36:54 +00:00
|
|
|
case VS_OPCODE_URB_WRITE:
|
2013-03-21 16:11:12 +00:00
|
|
|
return "vs_urb_write";
|
2013-03-12 00:36:54 +00:00
|
|
|
case VS_OPCODE_PULL_CONSTANT_LOAD:
|
|
|
|
return "pull_constant_load";
|
2013-04-04 22:10:18 +01:00
|
|
|
case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
|
|
|
|
return "pull_constant_load_gen7";
|
2015-03-24 15:52:20 +00:00
|
|
|
|
|
|
|
case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
|
|
|
|
return "set_simd4x2_header_gen9";
|
|
|
|
|
2015-08-28 08:39:49 +01:00
|
|
|
case VS_OPCODE_GET_BUFFER_SIZE:
|
|
|
|
return "vs_get_buffer_size";
|
|
|
|
|
2013-08-07 19:31:33 +01:00
|
|
|
case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
|
|
|
|
return "unpack_flags_simd4x2";
|
2013-03-12 00:36:54 +00:00
|
|
|
|
2013-03-21 16:11:12 +00:00
|
|
|
case GS_OPCODE_URB_WRITE:
|
|
|
|
return "gs_urb_write";
|
2014-07-09 15:28:30 +01:00
|
|
|
case GS_OPCODE_URB_WRITE_ALLOCATE:
|
|
|
|
return "gs_urb_write_allocate";
|
2013-03-23 14:42:32 +00:00
|
|
|
case GS_OPCODE_THREAD_END:
|
|
|
|
return "gs_thread_end";
|
2013-03-23 14:59:13 +00:00
|
|
|
case GS_OPCODE_SET_WRITE_OFFSET:
|
|
|
|
return "set_write_offset";
|
2013-03-23 15:18:43 +00:00
|
|
|
case GS_OPCODE_SET_VERTEX_COUNT:
|
|
|
|
return "set_vertex_count";
|
2014-07-17 07:54:03 +01:00
|
|
|
case GS_OPCODE_SET_DWORD_2:
|
|
|
|
return "set_dword_2";
|
2013-04-21 16:51:33 +01:00
|
|
|
case GS_OPCODE_PREPARE_CHANNEL_MASKS:
|
|
|
|
return "prepare_channel_masks";
|
|
|
|
case GS_OPCODE_SET_CHANNEL_MASKS:
|
|
|
|
return "set_channel_masks";
|
2014-01-25 20:55:24 +00:00
|
|
|
case GS_OPCODE_GET_INSTANCE_ID:
|
|
|
|
return "get_instance_id";
|
2014-07-09 07:46:17 +01:00
|
|
|
case GS_OPCODE_FF_SYNC:
|
|
|
|
return "ff_sync";
|
2014-07-24 11:14:27 +01:00
|
|
|
case GS_OPCODE_SET_PRIMITIVE_ID:
|
|
|
|
return "set_primitive_id";
|
2014-07-18 09:36:10 +01:00
|
|
|
case GS_OPCODE_SVB_WRITE:
|
|
|
|
return "gs_svb_write";
|
2014-07-18 09:47:15 +01:00
|
|
|
case GS_OPCODE_SVB_SET_DST_INDEX:
|
|
|
|
return "gs_svb_set_dst_index";
|
2014-07-23 11:56:53 +01:00
|
|
|
case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
|
|
|
|
return "gs_ff_sync_set_primitives";
|
2014-08-27 19:32:08 +01:00
|
|
|
case CS_OPCODE_CS_TERMINATE:
|
|
|
|
return "cs_terminate";
|
2014-08-27 19:32:08 +01:00
|
|
|
case SHADER_OPCODE_BARRIER:
|
|
|
|
return "barrier";
|
2015-08-04 17:04:55 +01:00
|
|
|
case SHADER_OPCODE_MULH:
|
|
|
|
return "mulh";
|
2015-11-08 02:58:34 +00:00
|
|
|
case SHADER_OPCODE_MOV_INDIRECT:
|
|
|
|
return "mov_indirect";
|
2015-11-17 09:07:39 +00:00
|
|
|
|
|
|
|
case VEC4_OPCODE_URB_READ:
|
|
|
|
return "urb_read";
|
|
|
|
case TCS_OPCODE_GET_INSTANCE_ID:
|
|
|
|
return "tcs_get_instance_id";
|
|
|
|
case TCS_OPCODE_URB_WRITE:
|
|
|
|
return "tcs_urb_write";
|
|
|
|
case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
|
|
|
|
return "tcs_set_input_urb_offsets";
|
|
|
|
case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
|
|
|
|
return "tcs_set_output_urb_offsets";
|
|
|
|
case TCS_OPCODE_GET_PRIMITIVE_ID:
|
|
|
|
return "tcs_get_primitive_id";
|
|
|
|
case TCS_OPCODE_CREATE_BARRIER_HEADER:
|
|
|
|
return "tcs_create_barrier_header";
|
2015-11-26 01:54:22 +00:00
|
|
|
case TCS_OPCODE_SRC0_010_IS_ZERO:
|
|
|
|
return "tcs_src0<0,1,0>_is_zero";
|
|
|
|
case TCS_OPCODE_RELEASE_INPUT:
|
|
|
|
return "tcs_release_input";
|
2015-12-24 21:09:26 +00:00
|
|
|
case TCS_OPCODE_THREAD_END:
|
|
|
|
return "tcs_thread_end";
|
2015-11-17 09:30:35 +00:00
|
|
|
case TES_OPCODE_CREATE_INPUT_READ_HEADER:
|
|
|
|
return "tes_create_input_read_header";
|
|
|
|
case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
|
|
|
|
return "tes_add_indirect_urb_offset";
|
|
|
|
case TES_OPCODE_GET_PRIMITIVE_ID:
|
|
|
|
return "tes_get_primitive_id";
|
2013-03-12 00:36:54 +00:00
|
|
|
}
|
2014-12-06 22:18:21 +00:00
|
|
|
|
|
|
|
unreachable("not reached");
|
2013-03-12 00:36:54 +00:00
|
|
|
}
|
2013-04-28 09:35:57 +01:00
|
|
|
|
2014-12-21 14:56:54 +00:00
|
|
|
bool
|
|
|
|
brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
|
|
|
|
{
|
|
|
|
union {
|
|
|
|
unsigned ud;
|
|
|
|
int d;
|
|
|
|
float f;
|
2015-11-18 11:09:30 +00:00
|
|
|
double df;
|
|
|
|
} imm, sat_imm = { 0 };
|
|
|
|
|
|
|
|
const unsigned size = type_sz(type);
|
|
|
|
|
|
|
|
/* We want to either do a 32-bit or 64-bit data copy, the type is otherwise
|
|
|
|
* irrelevant, so just check the size of the type and copy from/to an
|
|
|
|
* appropriately sized field.
|
|
|
|
*/
|
|
|
|
if (size < 8)
|
|
|
|
imm.ud = reg->ud;
|
|
|
|
else
|
|
|
|
imm.df = reg->df;
|
2014-12-21 14:56:54 +00:00
|
|
|
|
|
|
|
switch (type) {
|
|
|
|
case BRW_REGISTER_TYPE_UD:
|
|
|
|
case BRW_REGISTER_TYPE_D:
|
2015-11-02 19:28:35 +00:00
|
|
|
case BRW_REGISTER_TYPE_UW:
|
|
|
|
case BRW_REGISTER_TYPE_W:
|
2014-12-21 14:56:54 +00:00
|
|
|
case BRW_REGISTER_TYPE_UQ:
|
|
|
|
case BRW_REGISTER_TYPE_Q:
|
|
|
|
/* Nothing to do. */
|
|
|
|
return false;
|
|
|
|
case BRW_REGISTER_TYPE_F:
|
|
|
|
sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
|
|
|
|
break;
|
2015-11-18 11:09:30 +00:00
|
|
|
case BRW_REGISTER_TYPE_DF:
|
|
|
|
sat_imm.df = CLAMP(imm.df, 0.0, 1.0);
|
|
|
|
break;
|
2014-12-21 14:56:54 +00:00
|
|
|
case BRW_REGISTER_TYPE_UB:
|
|
|
|
case BRW_REGISTER_TYPE_B:
|
2015-01-29 19:16:43 +00:00
|
|
|
unreachable("no UB/B immediates");
|
2014-12-21 14:56:54 +00:00
|
|
|
case BRW_REGISTER_TYPE_V:
|
|
|
|
case BRW_REGISTER_TYPE_UV:
|
|
|
|
case BRW_REGISTER_TYPE_VF:
|
2015-02-11 22:53:08 +00:00
|
|
|
unreachable("unimplemented: saturate vector immediate");
|
2014-12-21 14:56:54 +00:00
|
|
|
case BRW_REGISTER_TYPE_HF:
|
2015-11-18 11:09:30 +00:00
|
|
|
unreachable("unimplemented: saturate HF immediate");
|
2014-12-21 14:56:54 +00:00
|
|
|
}
|
|
|
|
|
2015-11-18 11:09:30 +00:00
|
|
|
if (size < 8) {
|
|
|
|
if (imm.ud != sat_imm.ud) {
|
|
|
|
reg->ud = sat_imm.ud;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
if (imm.df != sat_imm.df) {
|
|
|
|
reg->df = sat_imm.df;
|
|
|
|
return true;
|
|
|
|
}
|
2014-12-21 14:56:54 +00:00
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2015-01-29 19:15:10 +00:00
|
|
|
bool
|
|
|
|
brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
|
|
|
|
{
|
|
|
|
switch (type) {
|
|
|
|
case BRW_REGISTER_TYPE_D:
|
2015-02-06 12:38:20 +00:00
|
|
|
case BRW_REGISTER_TYPE_UD:
|
2015-10-23 03:41:30 +01:00
|
|
|
reg->d = -reg->d;
|
2015-01-29 19:15:10 +00:00
|
|
|
return true;
|
|
|
|
case BRW_REGISTER_TYPE_W:
|
2015-02-06 12:38:20 +00:00
|
|
|
case BRW_REGISTER_TYPE_UW:
|
2015-10-23 03:41:30 +01:00
|
|
|
reg->d = -(int16_t)reg->ud;
|
2015-01-29 19:15:10 +00:00
|
|
|
return true;
|
|
|
|
case BRW_REGISTER_TYPE_F:
|
2015-10-23 03:41:30 +01:00
|
|
|
reg->f = -reg->f;
|
2015-01-29 19:15:10 +00:00
|
|
|
return true;
|
|
|
|
case BRW_REGISTER_TYPE_VF:
|
2015-10-23 03:41:30 +01:00
|
|
|
reg->ud ^= 0x80808080;
|
2015-01-29 19:15:10 +00:00
|
|
|
return true;
|
2015-11-18 11:38:03 +00:00
|
|
|
case BRW_REGISTER_TYPE_DF:
|
|
|
|
reg->df = -reg->df;
|
|
|
|
return true;
|
2015-01-29 19:15:10 +00:00
|
|
|
case BRW_REGISTER_TYPE_UB:
|
|
|
|
case BRW_REGISTER_TYPE_B:
|
|
|
|
unreachable("no UB/B immediates");
|
|
|
|
case BRW_REGISTER_TYPE_UV:
|
|
|
|
case BRW_REGISTER_TYPE_V:
|
|
|
|
assert(!"unimplemented: negate UV/V immediate");
|
|
|
|
case BRW_REGISTER_TYPE_UQ:
|
|
|
|
case BRW_REGISTER_TYPE_Q:
|
|
|
|
assert(!"unimplemented: negate UQ/Q immediate");
|
|
|
|
case BRW_REGISTER_TYPE_HF:
|
2015-11-18 11:38:03 +00:00
|
|
|
assert(!"unimplemented: negate HF immediate");
|
2015-01-29 19:15:10 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2015-01-30 22:14:43 +00:00
|
|
|
bool
|
|
|
|
brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
|
|
|
|
{
|
|
|
|
switch (type) {
|
|
|
|
case BRW_REGISTER_TYPE_D:
|
2015-10-23 03:41:30 +01:00
|
|
|
reg->d = abs(reg->d);
|
2015-01-30 22:14:43 +00:00
|
|
|
return true;
|
|
|
|
case BRW_REGISTER_TYPE_W:
|
2015-10-23 03:41:30 +01:00
|
|
|
reg->d = abs((int16_t)reg->ud);
|
2015-01-30 22:14:43 +00:00
|
|
|
return true;
|
|
|
|
case BRW_REGISTER_TYPE_F:
|
2015-10-23 03:41:30 +01:00
|
|
|
reg->f = fabsf(reg->f);
|
2015-01-30 22:14:43 +00:00
|
|
|
return true;
|
2015-11-18 11:11:58 +00:00
|
|
|
case BRW_REGISTER_TYPE_DF:
|
|
|
|
reg->df = fabs(reg->df);
|
|
|
|
return true;
|
2015-01-30 22:14:43 +00:00
|
|
|
case BRW_REGISTER_TYPE_VF:
|
2015-10-23 03:41:30 +01:00
|
|
|
reg->ud &= ~0x80808080;
|
2015-01-30 22:14:43 +00:00
|
|
|
return true;
|
|
|
|
case BRW_REGISTER_TYPE_UB:
|
|
|
|
case BRW_REGISTER_TYPE_B:
|
|
|
|
unreachable("no UB/B immediates");
|
|
|
|
case BRW_REGISTER_TYPE_UQ:
|
|
|
|
case BRW_REGISTER_TYPE_UD:
|
|
|
|
case BRW_REGISTER_TYPE_UW:
|
|
|
|
case BRW_REGISTER_TYPE_UV:
|
|
|
|
/* Presumably the absolute value modifier on an unsigned source is a
|
|
|
|
* nop, but it would be nice to confirm.
|
|
|
|
*/
|
|
|
|
assert(!"unimplemented: abs unsigned immediate");
|
|
|
|
case BRW_REGISTER_TYPE_V:
|
|
|
|
assert(!"unimplemented: abs V immediate");
|
|
|
|
case BRW_REGISTER_TYPE_Q:
|
|
|
|
assert(!"unimplemented: abs Q immediate");
|
|
|
|
case BRW_REGISTER_TYPE_HF:
|
2015-11-18 11:11:58 +00:00
|
|
|
assert(!"unimplemented: abs HF immediate");
|
2015-01-30 22:14:43 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2016-04-11 05:28:37 +01:00
|
|
|
unsigned
|
|
|
|
tesslevel_outer_components(GLenum tes_primitive_mode)
|
|
|
|
{
|
|
|
|
switch (tes_primitive_mode) {
|
|
|
|
case GL_QUADS:
|
|
|
|
return 4;
|
|
|
|
case GL_TRIANGLES:
|
|
|
|
return 3;
|
|
|
|
case GL_ISOLINES:
|
|
|
|
return 2;
|
|
|
|
default:
|
|
|
|
unreachable("Bogus tessellation domain");
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned
|
|
|
|
tesslevel_inner_components(GLenum tes_primitive_mode)
|
|
|
|
{
|
|
|
|
switch (tes_primitive_mode) {
|
|
|
|
case GL_QUADS:
|
|
|
|
return 2;
|
|
|
|
case GL_TRIANGLES:
|
|
|
|
return 1;
|
|
|
|
case GL_ISOLINES:
|
|
|
|
return 0;
|
|
|
|
default:
|
|
|
|
unreachable("Bogus tessellation domain");
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Given a normal .xyzw writemask, convert it to a writemask for a vector
|
|
|
|
* that's stored backwards, i.e. .wzyx.
|
|
|
|
*/
|
|
|
|
unsigned
|
|
|
|
writemask_for_backwards_vector(unsigned mask)
|
|
|
|
{
|
|
|
|
unsigned new_mask = 0;
|
|
|
|
|
|
|
|
for (int i = 0; i < 4; i++)
|
|
|
|
new_mask |= ((mask >> i) & 1) << (3 - i);
|
|
|
|
|
|
|
|
return new_mask;
|
|
|
|
}
|
|
|
|
|
2015-06-23 01:17:56 +01:00
|
|
|
backend_shader::backend_shader(const struct brw_compiler *compiler,
|
|
|
|
void *log_data,
|
2015-06-22 19:42:15 +01:00
|
|
|
void *mem_ctx,
|
2015-10-06 03:26:02 +01:00
|
|
|
const nir_shader *shader,
|
2015-10-01 23:21:57 +01:00
|
|
|
struct brw_stage_prog_data *stage_prog_data)
|
2015-06-23 01:17:56 +01:00
|
|
|
: compiler(compiler),
|
|
|
|
log_data(log_data),
|
|
|
|
devinfo(compiler->devinfo),
|
2015-10-01 23:21:57 +01:00
|
|
|
nir(shader),
|
2014-07-12 04:54:52 +01:00
|
|
|
stage_prog_data(stage_prog_data),
|
2015-06-22 19:42:15 +01:00
|
|
|
mem_ctx(mem_ctx),
|
2014-07-22 04:05:21 +01:00
|
|
|
cfg(NULL),
|
2015-10-01 23:21:57 +01:00
|
|
|
stage(shader->stage)
|
2014-02-14 09:54:02 +00:00
|
|
|
{
|
2015-02-19 01:38:45 +00:00
|
|
|
debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
|
|
|
|
stage_name = _mesa_shader_stage_to_string(stage);
|
|
|
|
stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
|
2016-05-03 21:14:31 +01:00
|
|
|
is_passthrough_shader =
|
|
|
|
nir->info.name && strcmp(nir->info.name, "passthrough") == 0;
|
2014-02-14 09:54:02 +00:00
|
|
|
}
|
|
|
|
|
2015-11-22 21:25:05 +00:00
|
|
|
bool
|
|
|
|
backend_reg::equals(const backend_reg &r) const
|
|
|
|
{
|
2016-05-14 00:41:13 +01:00
|
|
|
return brw_regs_equal(this, &r) && reg_offset == r.reg_offset;
|
2015-11-22 21:25:05 +00:00
|
|
|
}
|
|
|
|
|
2014-06-29 23:35:58 +01:00
|
|
|
bool
|
|
|
|
backend_reg::is_zero() const
|
|
|
|
{
|
|
|
|
if (file != IMM)
|
|
|
|
return false;
|
|
|
|
|
2015-11-18 11:38:31 +00:00
|
|
|
switch (type) {
|
|
|
|
case BRW_REGISTER_TYPE_F:
|
|
|
|
return f == 0;
|
|
|
|
case BRW_REGISTER_TYPE_DF:
|
|
|
|
return df == 0;
|
|
|
|
case BRW_REGISTER_TYPE_D:
|
|
|
|
case BRW_REGISTER_TYPE_UD:
|
|
|
|
return d == 0;
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
2014-06-29 23:35:58 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
bool
|
|
|
|
backend_reg::is_one() const
|
|
|
|
{
|
|
|
|
if (file != IMM)
|
|
|
|
return false;
|
|
|
|
|
2015-11-18 11:38:31 +00:00
|
|
|
switch (type) {
|
|
|
|
case BRW_REGISTER_TYPE_F:
|
|
|
|
return f == 1.0f;
|
|
|
|
case BRW_REGISTER_TYPE_DF:
|
|
|
|
return df == 1.0;
|
|
|
|
case BRW_REGISTER_TYPE_D:
|
|
|
|
case BRW_REGISTER_TYPE_UD:
|
|
|
|
return d == 1;
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
2014-06-29 23:35:58 +01:00
|
|
|
}
|
|
|
|
|
2015-02-05 02:08:21 +00:00
|
|
|
bool
|
|
|
|
backend_reg::is_negative_one() const
|
|
|
|
{
|
|
|
|
if (file != IMM)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
switch (type) {
|
|
|
|
case BRW_REGISTER_TYPE_F:
|
2015-10-24 22:55:57 +01:00
|
|
|
return f == -1.0;
|
2015-11-18 11:38:31 +00:00
|
|
|
case BRW_REGISTER_TYPE_DF:
|
|
|
|
return df == -1.0;
|
2015-02-05 02:08:21 +00:00
|
|
|
case BRW_REGISTER_TYPE_D:
|
2015-10-24 22:55:57 +01:00
|
|
|
return d == -1;
|
2015-02-05 02:08:21 +00:00
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-06-29 23:35:58 +01:00
|
|
|
bool
|
|
|
|
backend_reg::is_null() const
|
|
|
|
{
|
2015-10-27 00:52:57 +00:00
|
|
|
return file == ARF && nr == BRW_ARF_NULL;
|
2014-06-29 23:35:58 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
bool
|
|
|
|
backend_reg::is_accumulator() const
|
|
|
|
{
|
2015-10-27 00:52:57 +00:00
|
|
|
return file == ARF && nr == BRW_ARF_ACCUMULATOR;
|
2014-06-29 23:35:58 +01:00
|
|
|
}
|
|
|
|
|
2015-03-18 17:35:31 +00:00
|
|
|
bool
|
|
|
|
backend_reg::in_range(const backend_reg &r, unsigned n) const
|
|
|
|
{
|
|
|
|
return (file == r.file &&
|
2015-10-26 11:35:14 +00:00
|
|
|
nr == r.nr &&
|
2015-03-18 17:35:31 +00:00
|
|
|
reg_offset >= r.reg_offset &&
|
|
|
|
reg_offset < r.reg_offset + n);
|
|
|
|
}
|
|
|
|
|
2015-03-13 21:34:06 +00:00
|
|
|
bool
|
|
|
|
backend_instruction::is_commutative() const
|
|
|
|
{
|
|
|
|
switch (opcode) {
|
|
|
|
case BRW_OPCODE_AND:
|
|
|
|
case BRW_OPCODE_OR:
|
|
|
|
case BRW_OPCODE_XOR:
|
|
|
|
case BRW_OPCODE_ADD:
|
|
|
|
case BRW_OPCODE_MUL:
|
2015-08-04 17:04:55 +01:00
|
|
|
case SHADER_OPCODE_MULH:
|
2015-03-13 21:34:06 +00:00
|
|
|
return true;
|
|
|
|
case BRW_OPCODE_SEL:
|
|
|
|
/* MIN and MAX are commutative. */
|
|
|
|
if (conditional_mod == BRW_CONDITIONAL_GE ||
|
|
|
|
conditional_mod == BRW_CONDITIONAL_L) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
/* fallthrough */
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-12-30 03:29:21 +00:00
|
|
|
bool
|
2016-08-22 23:01:08 +01:00
|
|
|
backend_instruction::is_3src(const struct gen_device_info *devinfo) const
|
2014-12-30 03:29:21 +00:00
|
|
|
{
|
2016-04-28 08:19:13 +01:00
|
|
|
return ::is_3src(devinfo, opcode);
|
2014-12-30 03:29:21 +00:00
|
|
|
}
|
|
|
|
|
2013-04-28 09:35:57 +01:00
|
|
|
bool
|
2014-02-27 23:44:45 +00:00
|
|
|
backend_instruction::is_tex() const
|
2013-04-28 09:35:57 +01:00
|
|
|
{
|
|
|
|
return (opcode == SHADER_OPCODE_TEX ||
|
|
|
|
opcode == FS_OPCODE_TXB ||
|
|
|
|
opcode == SHADER_OPCODE_TXD ||
|
|
|
|
opcode == SHADER_OPCODE_TXF ||
|
2016-05-04 23:46:45 +01:00
|
|
|
opcode == SHADER_OPCODE_TXF_LZ ||
|
2013-12-10 14:36:31 +00:00
|
|
|
opcode == SHADER_OPCODE_TXF_CMS ||
|
2015-09-08 15:52:09 +01:00
|
|
|
opcode == SHADER_OPCODE_TXF_CMS_W ||
|
2013-12-10 14:38:15 +00:00
|
|
|
opcode == SHADER_OPCODE_TXF_UMS ||
|
2013-11-29 21:32:16 +00:00
|
|
|
opcode == SHADER_OPCODE_TXF_MCS ||
|
2013-04-28 09:35:57 +01:00
|
|
|
opcode == SHADER_OPCODE_TXL ||
|
2016-05-04 23:46:45 +01:00
|
|
|
opcode == SHADER_OPCODE_TXL_LZ ||
|
2013-04-28 09:35:57 +01:00
|
|
|
opcode == SHADER_OPCODE_TXS ||
|
2013-03-31 09:31:12 +01:00
|
|
|
opcode == SHADER_OPCODE_LOD ||
|
2013-10-08 09:42:10 +01:00
|
|
|
opcode == SHADER_OPCODE_TG4 ||
|
2015-10-10 02:07:23 +01:00
|
|
|
opcode == SHADER_OPCODE_TG4_OFFSET ||
|
|
|
|
opcode == SHADER_OPCODE_SAMPLEINFO);
|
2013-04-28 09:35:57 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
bool
|
2014-02-27 23:44:45 +00:00
|
|
|
backend_instruction::is_math() const
|
2013-04-28 09:35:57 +01:00
|
|
|
{
|
|
|
|
return (opcode == SHADER_OPCODE_RCP ||
|
|
|
|
opcode == SHADER_OPCODE_RSQ ||
|
|
|
|
opcode == SHADER_OPCODE_SQRT ||
|
|
|
|
opcode == SHADER_OPCODE_EXP2 ||
|
|
|
|
opcode == SHADER_OPCODE_LOG2 ||
|
|
|
|
opcode == SHADER_OPCODE_SIN ||
|
|
|
|
opcode == SHADER_OPCODE_COS ||
|
|
|
|
opcode == SHADER_OPCODE_INT_QUOTIENT ||
|
|
|
|
opcode == SHADER_OPCODE_INT_REMAINDER ||
|
|
|
|
opcode == SHADER_OPCODE_POW);
|
|
|
|
}
|
|
|
|
|
|
|
|
bool
|
2014-02-27 23:44:45 +00:00
|
|
|
backend_instruction::is_control_flow() const
|
2013-04-28 09:35:57 +01:00
|
|
|
{
|
|
|
|
switch (opcode) {
|
|
|
|
case BRW_OPCODE_DO:
|
|
|
|
case BRW_OPCODE_WHILE:
|
|
|
|
case BRW_OPCODE_IF:
|
|
|
|
case BRW_OPCODE_ELSE:
|
|
|
|
case BRW_OPCODE_ENDIF:
|
|
|
|
case BRW_OPCODE_BREAK:
|
|
|
|
case BRW_OPCODE_CONTINUE:
|
|
|
|
return true;
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
2013-04-29 22:21:14 +01:00
|
|
|
|
2013-09-20 03:48:22 +01:00
|
|
|
bool
|
2014-02-27 23:44:45 +00:00
|
|
|
backend_instruction::can_do_source_mods() const
|
2013-09-20 03:48:22 +01:00
|
|
|
{
|
|
|
|
switch (opcode) {
|
|
|
|
case BRW_OPCODE_ADDC:
|
|
|
|
case BRW_OPCODE_BFE:
|
|
|
|
case BRW_OPCODE_BFI1:
|
|
|
|
case BRW_OPCODE_BFI2:
|
|
|
|
case BRW_OPCODE_BFREV:
|
|
|
|
case BRW_OPCODE_CBIT:
|
|
|
|
case BRW_OPCODE_FBH:
|
|
|
|
case BRW_OPCODE_FBL:
|
|
|
|
case BRW_OPCODE_SUBB:
|
|
|
|
return false;
|
|
|
|
default:
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-12-12 07:07:49 +00:00
|
|
|
bool
|
2014-02-27 23:44:45 +00:00
|
|
|
backend_instruction::can_do_saturate() const
|
2013-12-12 07:07:49 +00:00
|
|
|
{
|
|
|
|
switch (opcode) {
|
|
|
|
case BRW_OPCODE_ADD:
|
|
|
|
case BRW_OPCODE_ASR:
|
|
|
|
case BRW_OPCODE_AVG:
|
|
|
|
case BRW_OPCODE_DP2:
|
|
|
|
case BRW_OPCODE_DP3:
|
|
|
|
case BRW_OPCODE_DP4:
|
|
|
|
case BRW_OPCODE_DPH:
|
|
|
|
case BRW_OPCODE_F16TO32:
|
|
|
|
case BRW_OPCODE_F32TO16:
|
|
|
|
case BRW_OPCODE_LINE:
|
|
|
|
case BRW_OPCODE_LRP:
|
|
|
|
case BRW_OPCODE_MAC:
|
|
|
|
case BRW_OPCODE_MAD:
|
|
|
|
case BRW_OPCODE_MATH:
|
|
|
|
case BRW_OPCODE_MOV:
|
|
|
|
case BRW_OPCODE_MUL:
|
2015-08-04 17:04:55 +01:00
|
|
|
case SHADER_OPCODE_MULH:
|
2013-12-12 07:07:49 +00:00
|
|
|
case BRW_OPCODE_PLN:
|
|
|
|
case BRW_OPCODE_RNDD:
|
|
|
|
case BRW_OPCODE_RNDE:
|
|
|
|
case BRW_OPCODE_RNDU:
|
|
|
|
case BRW_OPCODE_RNDZ:
|
|
|
|
case BRW_OPCODE_SEL:
|
|
|
|
case BRW_OPCODE_SHL:
|
|
|
|
case BRW_OPCODE_SHR:
|
|
|
|
case FS_OPCODE_LINTERP:
|
|
|
|
case SHADER_OPCODE_COS:
|
|
|
|
case SHADER_OPCODE_EXP2:
|
|
|
|
case SHADER_OPCODE_LOG2:
|
|
|
|
case SHADER_OPCODE_POW:
|
|
|
|
case SHADER_OPCODE_RCP:
|
|
|
|
case SHADER_OPCODE_RSQ:
|
|
|
|
case SHADER_OPCODE_SIN:
|
|
|
|
case SHADER_OPCODE_SQRT:
|
|
|
|
return true;
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-08-24 22:01:48 +01:00
|
|
|
bool
|
|
|
|
backend_instruction::can_do_cmod() const
|
|
|
|
{
|
|
|
|
switch (opcode) {
|
|
|
|
case BRW_OPCODE_ADD:
|
|
|
|
case BRW_OPCODE_ADDC:
|
|
|
|
case BRW_OPCODE_AND:
|
|
|
|
case BRW_OPCODE_ASR:
|
|
|
|
case BRW_OPCODE_AVG:
|
|
|
|
case BRW_OPCODE_CMP:
|
|
|
|
case BRW_OPCODE_CMPN:
|
|
|
|
case BRW_OPCODE_DP2:
|
|
|
|
case BRW_OPCODE_DP3:
|
|
|
|
case BRW_OPCODE_DP4:
|
|
|
|
case BRW_OPCODE_DPH:
|
|
|
|
case BRW_OPCODE_F16TO32:
|
|
|
|
case BRW_OPCODE_F32TO16:
|
|
|
|
case BRW_OPCODE_FRC:
|
|
|
|
case BRW_OPCODE_LINE:
|
|
|
|
case BRW_OPCODE_LRP:
|
|
|
|
case BRW_OPCODE_LZD:
|
|
|
|
case BRW_OPCODE_MAC:
|
|
|
|
case BRW_OPCODE_MACH:
|
|
|
|
case BRW_OPCODE_MAD:
|
|
|
|
case BRW_OPCODE_MOV:
|
|
|
|
case BRW_OPCODE_MUL:
|
|
|
|
case BRW_OPCODE_NOT:
|
|
|
|
case BRW_OPCODE_OR:
|
|
|
|
case BRW_OPCODE_PLN:
|
|
|
|
case BRW_OPCODE_RNDD:
|
|
|
|
case BRW_OPCODE_RNDE:
|
|
|
|
case BRW_OPCODE_RNDU:
|
|
|
|
case BRW_OPCODE_RNDZ:
|
|
|
|
case BRW_OPCODE_SAD2:
|
|
|
|
case BRW_OPCODE_SADA2:
|
|
|
|
case BRW_OPCODE_SHL:
|
|
|
|
case BRW_OPCODE_SHR:
|
|
|
|
case BRW_OPCODE_SUBB:
|
|
|
|
case BRW_OPCODE_XOR:
|
2015-01-24 05:58:51 +00:00
|
|
|
case FS_OPCODE_CINTERP:
|
|
|
|
case FS_OPCODE_LINTERP:
|
2014-08-24 22:01:48 +01:00
|
|
|
return true;
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-04-09 20:01:49 +01:00
|
|
|
bool
|
|
|
|
backend_instruction::reads_accumulator_implicitly() const
|
|
|
|
{
|
|
|
|
switch (opcode) {
|
|
|
|
case BRW_OPCODE_MAC:
|
|
|
|
case BRW_OPCODE_MACH:
|
|
|
|
case BRW_OPCODE_SADA2:
|
|
|
|
return true;
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-05-07 08:58:43 +01:00
|
|
|
bool
|
2016-08-22 23:01:08 +01:00
|
|
|
backend_instruction::writes_accumulator_implicitly(const struct gen_device_info *devinfo) const
|
2014-05-07 08:58:43 +01:00
|
|
|
{
|
|
|
|
return writes_accumulator ||
|
2015-04-17 20:15:58 +01:00
|
|
|
(devinfo->gen < 6 &&
|
2014-05-07 08:58:43 +01:00
|
|
|
((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
|
2014-11-08 09:39:14 +00:00
|
|
|
(opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
|
2014-05-07 08:58:43 +01:00
|
|
|
opcode != FS_OPCODE_CINTERP)));
|
|
|
|
}
|
|
|
|
|
2013-10-20 22:02:08 +01:00
|
|
|
bool
|
|
|
|
backend_instruction::has_side_effects() const
|
|
|
|
{
|
|
|
|
switch (opcode) {
|
|
|
|
case SHADER_OPCODE_UNTYPED_ATOMIC:
|
2015-07-21 16:45:32 +01:00
|
|
|
case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
|
2015-02-28 21:36:21 +00:00
|
|
|
case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
|
2015-04-23 12:24:14 +01:00
|
|
|
case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
|
2015-07-21 16:45:32 +01:00
|
|
|
case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
|
2015-04-23 12:28:25 +01:00
|
|
|
case SHADER_OPCODE_TYPED_ATOMIC:
|
2015-07-21 16:45:32 +01:00
|
|
|
case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
|
2015-04-23 12:28:25 +01:00
|
|
|
case SHADER_OPCODE_TYPED_SURFACE_WRITE:
|
2015-07-21 16:45:32 +01:00
|
|
|
case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
|
2015-04-23 12:30:28 +01:00
|
|
|
case SHADER_OPCODE_MEMORY_FENCE:
|
2014-10-21 07:00:50 +01:00
|
|
|
case SHADER_OPCODE_URB_WRITE_SIMD8:
|
2015-05-06 08:04:10 +01:00
|
|
|
case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
|
|
|
|
case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
|
|
|
|
case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
|
2014-09-13 00:17:37 +01:00
|
|
|
case FS_OPCODE_FB_WRITE:
|
2016-04-30 22:57:59 +01:00
|
|
|
case FS_OPCODE_FB_WRITE_LOGICAL:
|
2014-08-27 19:32:08 +01:00
|
|
|
case SHADER_OPCODE_BARRIER:
|
2016-01-11 20:25:12 +00:00
|
|
|
case TCS_OPCODE_URB_WRITE:
|
2015-11-26 01:54:22 +00:00
|
|
|
case TCS_OPCODE_RELEASE_INPUT:
|
2013-10-20 22:02:08 +01:00
|
|
|
return true;
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-10-20 07:13:09 +01:00
|
|
|
bool
|
|
|
|
backend_instruction::is_volatile() const
|
|
|
|
{
|
|
|
|
switch (opcode) {
|
|
|
|
case SHADER_OPCODE_UNTYPED_SURFACE_READ:
|
|
|
|
case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
|
|
|
|
case SHADER_OPCODE_TYPED_SURFACE_READ:
|
|
|
|
case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
|
2016-04-09 02:49:22 +01:00
|
|
|
case SHADER_OPCODE_URB_READ_SIMD8:
|
|
|
|
case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
|
|
|
|
case VEC4_OPCODE_URB_READ:
|
2015-10-20 07:13:09 +01:00
|
|
|
return true;
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-07-13 05:16:34 +01:00
|
|
|
#ifndef NDEBUG
|
|
|
|
static bool
|
|
|
|
inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
|
|
|
|
{
|
|
|
|
bool found = false;
|
|
|
|
foreach_inst_in_block (backend_instruction, i, block) {
|
|
|
|
if (inst == i) {
|
|
|
|
found = true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return found;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
static void
|
|
|
|
adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
|
|
|
|
{
|
2014-09-03 05:07:51 +01:00
|
|
|
for (bblock_t *block_iter = start_block->next();
|
2016-03-30 20:00:02 +01:00
|
|
|
block_iter;
|
2014-09-03 05:07:51 +01:00
|
|
|
block_iter = block_iter->next()) {
|
2014-07-13 05:16:34 +01:00
|
|
|
block_iter->start_ip += ip_adjustment;
|
|
|
|
block_iter->end_ip += ip_adjustment;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-07-13 05:18:08 +01:00
|
|
|
void
|
|
|
|
backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
|
|
|
|
{
|
2016-02-15 18:42:14 +00:00
|
|
|
assert(this != inst);
|
|
|
|
|
2015-02-18 02:01:41 +00:00
|
|
|
if (!this->is_head_sentinel())
|
|
|
|
assert(inst_is_in_block(block, this) || !"Instruction not in block");
|
2014-07-13 05:18:08 +01:00
|
|
|
|
|
|
|
block->end_ip++;
|
|
|
|
|
|
|
|
adjust_later_block_ips(block, 1);
|
|
|
|
|
|
|
|
exec_node::insert_after(inst);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
|
|
|
|
{
|
2016-02-15 18:42:14 +00:00
|
|
|
assert(this != inst);
|
|
|
|
|
2015-02-18 02:01:41 +00:00
|
|
|
if (!this->is_tail_sentinel())
|
|
|
|
assert(inst_is_in_block(block, this) || !"Instruction not in block");
|
2014-07-13 05:18:08 +01:00
|
|
|
|
|
|
|
block->end_ip++;
|
|
|
|
|
|
|
|
adjust_later_block_ips(block, 1);
|
|
|
|
|
|
|
|
exec_node::insert_before(inst);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
backend_instruction::insert_before(bblock_t *block, exec_list *list)
|
|
|
|
{
|
|
|
|
assert(inst_is_in_block(block, this) || !"Instruction not in block");
|
|
|
|
|
|
|
|
unsigned num_inst = list->length();
|
|
|
|
|
|
|
|
block->end_ip += num_inst;
|
|
|
|
|
|
|
|
adjust_later_block_ips(block, num_inst);
|
|
|
|
|
|
|
|
exec_node::insert_before(list);
|
|
|
|
}
|
|
|
|
|
2014-07-13 05:16:34 +01:00
|
|
|
void
|
|
|
|
backend_instruction::remove(bblock_t *block)
|
|
|
|
{
|
|
|
|
assert(inst_is_in_block(block, this) || !"Instruction not in block");
|
|
|
|
|
|
|
|
adjust_later_block_ips(block, -1);
|
|
|
|
|
|
|
|
if (block->start_ip == block->end_ip) {
|
|
|
|
block->cfg->remove_block(block);
|
|
|
|
} else {
|
|
|
|
block->end_ip--;
|
|
|
|
}
|
|
|
|
|
|
|
|
exec_node::remove();
|
|
|
|
}
|
|
|
|
|
2013-04-29 22:21:14 +01:00
|
|
|
void
|
2015-05-20 17:44:01 +01:00
|
|
|
backend_shader::dump_instructions()
|
2013-04-29 22:21:14 +01:00
|
|
|
{
|
2014-05-29 21:08:59 +01:00
|
|
|
dump_instructions(NULL);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
2015-05-20 17:44:01 +01:00
|
|
|
backend_shader::dump_instructions(const char *name)
|
2014-05-29 21:08:59 +01:00
|
|
|
{
|
|
|
|
FILE *file = stderr;
|
|
|
|
if (name && geteuid() != 0) {
|
|
|
|
file = fopen(name, "w");
|
|
|
|
if (!file)
|
|
|
|
file = stderr;
|
|
|
|
}
|
|
|
|
|
2015-02-13 18:46:32 +00:00
|
|
|
if (cfg) {
|
|
|
|
int ip = 0;
|
|
|
|
foreach_block_and_inst(block, backend_instruction, inst, cfg) {
|
2015-09-26 22:40:09 +01:00
|
|
|
if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
|
|
|
|
fprintf(file, "%4d: ", ip++);
|
2015-02-13 18:46:32 +00:00
|
|
|
dump_instruction(inst, file);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
int ip = 0;
|
|
|
|
foreach_in_list(backend_instruction, inst, &instructions) {
|
2015-09-26 22:40:09 +01:00
|
|
|
if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
|
|
|
|
fprintf(file, "%4d: ", ip++);
|
2015-02-13 18:46:32 +00:00
|
|
|
dump_instruction(inst, file);
|
|
|
|
}
|
2014-05-29 21:08:59 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
if (file != stderr) {
|
|
|
|
fclose(file);
|
2013-04-29 22:21:14 +01:00
|
|
|
}
|
|
|
|
}
|
2013-10-03 17:58:43 +01:00
|
|
|
|
2014-07-12 04:54:52 +01:00
|
|
|
void
|
2015-05-20 17:44:01 +01:00
|
|
|
backend_shader::calculate_cfg()
|
2014-07-12 04:54:52 +01:00
|
|
|
{
|
|
|
|
if (this->cfg)
|
|
|
|
return;
|
|
|
|
cfg = new(mem_ctx) cfg_t(&this->instructions);
|
|
|
|
}
|
|
|
|
|
2013-10-03 17:58:43 +01:00
|
|
|
/**
|
|
|
|
* Sets up the starting offsets for the groups of binding table entries
|
|
|
|
* commong to all pipeline stages.
|
|
|
|
*
|
|
|
|
* Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
|
|
|
|
* unused but also make sure that addition of small offsets to them will
|
|
|
|
* trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
|
|
|
|
*/
|
2016-07-01 21:46:40 +01:00
|
|
|
uint32_t
|
2015-10-01 16:30:56 +01:00
|
|
|
brw_assign_common_binding_table_offsets(gl_shader_stage stage,
|
2016-08-22 23:01:08 +01:00
|
|
|
const struct gen_device_info *devinfo,
|
2015-10-01 16:30:56 +01:00
|
|
|
const struct gl_shader_program *shader_prog,
|
|
|
|
const struct gl_program *prog,
|
|
|
|
struct brw_stage_prog_data *stage_prog_data,
|
|
|
|
uint32_t next_binding_table_offset)
|
2013-10-03 17:58:43 +01:00
|
|
|
{
|
2016-06-30 05:55:40 +01:00
|
|
|
const struct gl_linked_shader *shader = NULL;
|
2016-08-02 07:46:04 +01:00
|
|
|
int num_textures = util_last_bit(prog->SamplersUsed);
|
2013-10-03 17:58:43 +01:00
|
|
|
|
2015-10-01 16:30:56 +01:00
|
|
|
if (shader_prog)
|
|
|
|
shader = shader_prog->_LinkedShaders[stage];
|
|
|
|
|
2013-10-03 17:58:43 +01:00
|
|
|
stage_prog_data->binding_table.texture_start = next_binding_table_offset;
|
|
|
|
next_binding_table_offset += num_textures;
|
|
|
|
|
|
|
|
if (shader) {
|
2015-10-09 13:41:21 +01:00
|
|
|
assert(shader->NumUniformBlocks <= BRW_MAX_UBO);
|
2013-10-03 17:58:43 +01:00
|
|
|
stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
|
2015-10-09 13:41:21 +01:00
|
|
|
next_binding_table_offset += shader->NumUniformBlocks;
|
|
|
|
|
|
|
|
assert(shader->NumShaderStorageBlocks <= BRW_MAX_SSBO);
|
|
|
|
stage_prog_data->binding_table.ssbo_start = next_binding_table_offset;
|
|
|
|
next_binding_table_offset += shader->NumShaderStorageBlocks;
|
2013-10-03 17:58:43 +01:00
|
|
|
} else {
|
|
|
|
stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
|
2015-10-09 13:41:21 +01:00
|
|
|
stage_prog_data->binding_table.ssbo_start = 0xd0d0d0d0;
|
2013-10-03 17:58:43 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
|
|
|
|
stage_prog_data->binding_table.shader_time_start = next_binding_table_offset;
|
|
|
|
next_binding_table_offset++;
|
|
|
|
} else {
|
|
|
|
stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (prog->UsesGather) {
|
2015-04-16 02:00:05 +01:00
|
|
|
if (devinfo->gen >= 8) {
|
2014-05-29 08:06:08 +01:00
|
|
|
stage_prog_data->binding_table.gather_texture_start =
|
|
|
|
stage_prog_data->binding_table.texture_start;
|
|
|
|
} else {
|
|
|
|
stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
|
|
|
|
next_binding_table_offset += num_textures;
|
|
|
|
}
|
2013-10-03 17:58:43 +01:00
|
|
|
} else {
|
|
|
|
stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
|
|
|
|
}
|
|
|
|
|
2015-10-26 19:58:15 +00:00
|
|
|
if (shader && shader->NumAtomicBuffers) {
|
2013-10-20 21:09:57 +01:00
|
|
|
stage_prog_data->binding_table.abo_start = next_binding_table_offset;
|
2015-10-26 19:58:15 +00:00
|
|
|
next_binding_table_offset += shader->NumAtomicBuffers;
|
2013-10-20 21:09:57 +01:00
|
|
|
} else {
|
|
|
|
stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
|
|
|
|
}
|
|
|
|
|
2015-10-01 16:30:56 +01:00
|
|
|
if (shader && shader->NumImages) {
|
2013-11-23 00:08:12 +00:00
|
|
|
stage_prog_data->binding_table.image_start = next_binding_table_offset;
|
2015-10-01 16:30:56 +01:00
|
|
|
next_binding_table_offset += shader->NumImages;
|
2013-11-23 00:08:12 +00:00
|
|
|
} else {
|
|
|
|
stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
|
|
|
|
}
|
|
|
|
|
2013-10-03 17:58:43 +01:00
|
|
|
/* This may or may not be used depending on how the compile goes. */
|
|
|
|
stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
|
|
|
|
next_binding_table_offset++;
|
|
|
|
|
2016-05-02 05:20:02 +01:00
|
|
|
/* Plane 0 is just the regular texture section */
|
|
|
|
stage_prog_data->binding_table.plane_start[0] = stage_prog_data->binding_table.texture_start;
|
|
|
|
|
|
|
|
stage_prog_data->binding_table.plane_start[1] = next_binding_table_offset;
|
|
|
|
next_binding_table_offset += num_textures;
|
|
|
|
|
|
|
|
stage_prog_data->binding_table.plane_start[2] = next_binding_table_offset;
|
|
|
|
next_binding_table_offset += num_textures;
|
|
|
|
|
2013-11-27 03:56:07 +00:00
|
|
|
/* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
|
2016-07-01 21:46:40 +01:00
|
|
|
|
|
|
|
assert(next_binding_table_offset <= BRW_MAX_SURFACES);
|
|
|
|
return next_binding_table_offset;
|
2013-10-03 17:58:43 +01:00
|
|
|
}
|
2015-05-05 19:07:15 +01:00
|
|
|
|
2015-09-30 19:46:36 +01:00
|
|
|
static void
|
|
|
|
setup_vec4_uniform_value(const gl_constant_value **params,
|
|
|
|
const gl_constant_value *values,
|
|
|
|
unsigned n)
|
|
|
|
{
|
|
|
|
static const gl_constant_value zero = { 0 };
|
|
|
|
|
|
|
|
for (unsigned i = 0; i < n; ++i)
|
|
|
|
params[i] = &values[i];
|
|
|
|
|
|
|
|
for (unsigned i = n; i < 4; ++i)
|
|
|
|
params[i] = &zero;
|
|
|
|
}
|
|
|
|
|
2015-05-05 19:07:15 +01:00
|
|
|
void
|
2015-09-30 19:46:36 +01:00
|
|
|
brw_setup_image_uniform_values(gl_shader_stage stage,
|
|
|
|
struct brw_stage_prog_data *stage_prog_data,
|
|
|
|
unsigned param_start_index,
|
|
|
|
const gl_uniform_storage *storage)
|
2015-05-05 19:07:15 +01:00
|
|
|
{
|
2015-09-30 19:46:36 +01:00
|
|
|
const gl_constant_value **param =
|
|
|
|
&stage_prog_data->param[param_start_index];
|
2015-05-05 19:07:15 +01:00
|
|
|
|
|
|
|
for (unsigned i = 0; i < MAX2(storage->array_elements, 1); i++) {
|
2015-09-30 02:00:02 +01:00
|
|
|
const unsigned image_idx = storage->opaque[stage].index + i;
|
2015-09-30 19:46:36 +01:00
|
|
|
const brw_image_param *image_param =
|
|
|
|
&stage_prog_data->image_param[image_idx];
|
2015-05-05 19:07:15 +01:00
|
|
|
|
|
|
|
/* Upload the brw_image_param structure. The order is expected to match
|
|
|
|
* the BRW_IMAGE_PARAM_*_OFFSET defines.
|
|
|
|
*/
|
2015-09-30 19:46:36 +01:00
|
|
|
setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET,
|
|
|
|
(const gl_constant_value *)&image_param->surface_idx, 1);
|
|
|
|
setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_OFFSET_OFFSET,
|
|
|
|
(const gl_constant_value *)image_param->offset, 2);
|
|
|
|
setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SIZE_OFFSET,
|
|
|
|
(const gl_constant_value *)image_param->size, 3);
|
|
|
|
setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_STRIDE_OFFSET,
|
|
|
|
(const gl_constant_value *)image_param->stride, 4);
|
|
|
|
setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_TILING_OFFSET,
|
|
|
|
(const gl_constant_value *)image_param->tiling, 3);
|
|
|
|
setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SWIZZLING_OFFSET,
|
|
|
|
(const gl_constant_value *)image_param->swizzling, 2);
|
|
|
|
param += BRW_IMAGE_PARAM_SIZE;
|
2015-05-05 19:07:15 +01:00
|
|
|
|
|
|
|
brw_mark_surface_used(
|
|
|
|
stage_prog_data,
|
|
|
|
stage_prog_data->binding_table.image_start + image_idx);
|
|
|
|
}
|
|
|
|
}
|
2015-10-07 12:19:39 +01:00
|
|
|
|
|
|
|
/**
|
|
|
|
* Decide which set of clip planes should be used when clipping via
|
|
|
|
* gl_Position or gl_ClipVertex.
|
|
|
|
*/
|
|
|
|
gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx)
|
|
|
|
{
|
|
|
|
if (ctx->_Shader->CurrentProgram[MESA_SHADER_VERTEX]) {
|
|
|
|
/* There is currently a GLSL vertex shader, so clip according to GLSL
|
|
|
|
* rules, which means compare gl_ClipVertex (or gl_Position, if
|
|
|
|
* gl_ClipVertex wasn't assigned) against the eye-coordinate clip planes
|
|
|
|
* that were stored in EyeUserPlane at the time the clip planes were
|
|
|
|
* specified.
|
|
|
|
*/
|
|
|
|
return ctx->Transform.EyeUserPlane;
|
|
|
|
} else {
|
|
|
|
/* Either we are using fixed function or an ARB vertex program. In
|
|
|
|
* either case the clip planes are going to be compared against
|
|
|
|
* gl_Position (which is in clip coordinates) so we have to clip using
|
|
|
|
* _ClipUserPlane, which was transformed into clip coordinates by Mesa
|
|
|
|
* core.
|
|
|
|
*/
|
|
|
|
return ctx->Transform._ClipUserPlane;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-11-10 22:35:27 +00:00
|
|
|
extern "C" const unsigned *
|
|
|
|
brw_compile_tes(const struct brw_compiler *compiler,
|
|
|
|
void *log_data,
|
|
|
|
void *mem_ctx,
|
|
|
|
const struct brw_tes_prog_key *key,
|
|
|
|
struct brw_tes_prog_data *prog_data,
|
|
|
|
const nir_shader *src_shader,
|
|
|
|
struct gl_shader_program *shader_prog,
|
|
|
|
int shader_time_index,
|
|
|
|
unsigned *final_assembly_size,
|
|
|
|
char **error_str)
|
|
|
|
{
|
2016-08-22 23:01:08 +01:00
|
|
|
const struct gen_device_info *devinfo = compiler->devinfo;
|
2016-06-30 05:55:40 +01:00
|
|
|
struct gl_linked_shader *shader =
|
2015-11-10 22:35:27 +00:00
|
|
|
shader_prog->_LinkedShaders[MESA_SHADER_TESS_EVAL];
|
|
|
|
const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
|
|
|
|
|
|
|
|
nir_shader *nir = nir_shader_clone(mem_ctx, src_shader);
|
i965: Handle mix-and-match TCS/TES with separate shader objects.
GL_ARB_separate_shader_objects allows the application to mix-and-match
TCS and TES programs separately. This means that the interface between
the two stages isn't known until the final SSO pipeline is in place.
This isn't a great match for our hardware: the TCS and TES have to agree
on the Patch URB entry layout. Since we store data as per-patch slots
followed by per-vertex slots, changing the number of per-patch slots can
significantly alter the layout. This can easily happen with SSO.
To handle this, we store the [Patch]OutputsWritten and [Patch]InputsRead
bitfields in the TCS/TES program keys, introducing program recompiles.
brw_upload_programs() decides the layout for both TCS and TES, and
passes it to brw_upload_tcs/tes(), which store it in the key.
When creating the NIR for a shader specialization, we override
nir->info.inputs_read (and friends) to the program key's values.
Since everything uses those, no further compiler changes are needed.
This also replaces the hack in brw_create_nir().
To avoid recompiles, brw_precompile_tes() looks to see if there's a
TCS in the linked shader. If so, it accounts for the TCS outputs,
just as brw_upload_programs() would. This eliminates all recompiles
in the non-SSO case. In the SSO case, there should only be recompiles
when using a TCS and TES that have different input/output interfaces.
Fixes Piglit's mix-and-match-tcs-tes test.
v2: Pull the brw_upload_programs code into a brw_upload_tess_programs()
helper function (requested by Jordan Justen).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2015-12-08 04:18:42 +00:00
|
|
|
nir->info.inputs_read = key->inputs_read;
|
|
|
|
nir->info.patch_inputs_read = key->patch_inputs_read;
|
2016-02-25 06:34:51 +00:00
|
|
|
|
|
|
|
struct brw_vue_map input_vue_map;
|
|
|
|
brw_compute_tess_vue_map(&input_vue_map,
|
|
|
|
nir->info.inputs_read & ~VARYING_BIT_PRIMITIVE_ID,
|
|
|
|
nir->info.patch_inputs_read);
|
|
|
|
|
|
|
|
nir = brw_nir_apply_sampler_key(nir, devinfo, &key->tex, is_scalar);
|
|
|
|
brw_nir_lower_tes_inputs(nir, &input_vue_map);
|
2016-02-25 06:11:35 +00:00
|
|
|
brw_nir_lower_vue_outputs(nir, is_scalar);
|
2015-11-10 22:35:27 +00:00
|
|
|
nir = brw_postprocess_nir(nir, compiler->devinfo, is_scalar);
|
|
|
|
|
|
|
|
brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
|
|
|
|
nir->info.outputs_written,
|
|
|
|
nir->info.separate_shader);
|
|
|
|
|
|
|
|
unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
|
|
|
|
|
|
|
|
assert(output_size_bytes >= 1);
|
|
|
|
if (output_size_bytes > GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
|
|
|
|
if (error_str)
|
|
|
|
*error_str = ralloc_strdup(mem_ctx, "DS outputs exceed maximum size");
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* URB entry sizes are stored as a multiple of 64 bytes. */
|
|
|
|
prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
|
|
|
|
|
|
|
|
bool need_patch_header = nir->info.system_values_read &
|
|
|
|
(BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_OUTER) |
|
|
|
|
BITFIELD64_BIT(SYSTEM_VALUE_TESS_LEVEL_INNER));
|
|
|
|
|
|
|
|
/* The TES will pull most inputs using URB read messages.
|
|
|
|
*
|
|
|
|
* However, we push the patch header for TessLevel factors when required,
|
|
|
|
* as it's a tiny amount of extra data.
|
|
|
|
*/
|
|
|
|
prog_data->base.urb_read_length = need_patch_header ? 1 : 0;
|
|
|
|
|
|
|
|
if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
|
|
|
|
fprintf(stderr, "TES Input ");
|
|
|
|
brw_print_vue_map(stderr, &input_vue_map);
|
|
|
|
fprintf(stderr, "TES Output ");
|
|
|
|
brw_print_vue_map(stderr, &prog_data->base.vue_map);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (is_scalar) {
|
|
|
|
fs_visitor v(compiler, log_data, mem_ctx, (void *) key,
|
|
|
|
&prog_data->base.base, shader->Program, nir, 8,
|
|
|
|
shader_time_index, &input_vue_map);
|
|
|
|
if (!v.run_tes()) {
|
|
|
|
if (error_str)
|
|
|
|
*error_str = ralloc_strdup(mem_ctx, v.fail_msg);
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2016-04-28 22:20:36 +01:00
|
|
|
prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs;
|
2015-11-10 22:35:27 +00:00
|
|
|
prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
|
|
|
|
|
|
|
|
fs_generator g(compiler, log_data, mem_ctx, (void *) key,
|
|
|
|
&prog_data->base.base, v.promoted_constants, false,
|
2016-01-15 04:27:51 +00:00
|
|
|
MESA_SHADER_TESS_EVAL);
|
2015-11-10 22:35:27 +00:00
|
|
|
if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
|
|
|
|
g.enable_debug(ralloc_asprintf(mem_ctx,
|
|
|
|
"%s tessellation evaluation shader %s",
|
|
|
|
nir->info.label ? nir->info.label
|
|
|
|
: "unnamed",
|
|
|
|
nir->info.name));
|
|
|
|
}
|
|
|
|
|
|
|
|
g.generate_code(v.cfg, 8);
|
|
|
|
|
|
|
|
return g.get_assembly(final_assembly_size);
|
|
|
|
} else {
|
2015-11-17 09:30:35 +00:00
|
|
|
brw::vec4_tes_visitor v(compiler, log_data, key, prog_data,
|
|
|
|
nir, mem_ctx, shader_time_index);
|
|
|
|
if (!v.run()) {
|
|
|
|
if (error_str)
|
|
|
|
*error_str = ralloc_strdup(mem_ctx, v.fail_msg);
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (unlikely(INTEL_DEBUG & DEBUG_TES))
|
|
|
|
v.dump_instructions();
|
|
|
|
|
|
|
|
return brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
|
|
|
|
&prog_data->base, v.cfg,
|
|
|
|
final_assembly_size);
|
2015-11-10 22:35:27 +00:00
|
|
|
}
|
|
|
|
}
|