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i965: Add untyped surface write opcode. 

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Francisco Jerez 2015-04-23 14:24:14 +03:00
parent c97a7705ea
commit 0775d8835a
9 changed files with 81 additions and 0 deletions
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1
src/mesa/drivers/dri/i965/brw_defines.h
View File

@ -904,6 +904,7 @@ enum opcode {
SHADER_OPCODE_UNTYPED_ATOMIC,
SHADER_OPCODE_UNTYPED_SURFACE_READ,
SHADER_OPCODE_UNTYPED_SURFACE_WRITE,
SHADER_OPCODE_GEN4_SCRATCH_READ,
SHADER_OPCODE_GEN4_SCRATCH_WRITE,

7
src/mesa/drivers/dri/i965/brw_eu.h
View File

@ -416,6 +416,13 @@ brw_untyped_surface_read(struct brw_codegen *p,
unsigned msg_length,
unsigned num_channels);
void
brw_untyped_surface_write(struct brw_codegen *p,
struct brw_reg payload,
struct brw_reg surface,
unsigned msg_length,
unsigned num_channels);
void
brw_pixel_interpolator_query(struct brw_codegen *p,
struct brw_reg dest,

51
src/mesa/drivers/dri/i965/brw_eu_emit.c
View File

@ -2894,6 +2894,57 @@ brw_untyped_surface_read(struct brw_codegen *p,
p, insn, num_channels);
}
static void
brw_set_dp_untyped_surface_write_message(struct brw_codegen *p,
struct brw_inst *insn,
unsigned num_channels)
{
const struct brw_device_info *devinfo = p->devinfo;
/* Set mask of 32-bit channels to drop. */
unsigned msg_control = 0xf & (0xf << num_channels);
if (brw_inst_access_mode(devinfo, p->current) == BRW_ALIGN_1) {
if (p->compressed)
msg_control |= 1 << 4; /* SIMD16 mode */
else
msg_control |= 2 << 4; /* SIMD8 mode */
} else {
if (devinfo->gen >= 8 || devinfo->is_haswell)
msg_control |= 0 << 4; /* SIMD4x2 mode */
else
msg_control |= 2 << 4; /* SIMD8 mode */
}
brw_inst_set_dp_msg_type(devinfo, insn,
devinfo->gen >= 8 || devinfo->is_haswell ?
HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE :
GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE);
brw_inst_set_dp_msg_control(devinfo, insn, msg_control);
}
void
brw_untyped_surface_write(struct brw_codegen *p,
struct brw_reg payload,
struct brw_reg surface,
unsigned msg_length,
unsigned num_channels)
{
const struct brw_device_info *devinfo = p->devinfo;
const unsigned sfid = (devinfo->gen >= 8 || devinfo->is_haswell ?
HSW_SFID_DATAPORT_DATA_CACHE_1 :
GEN7_SFID_DATAPORT_DATA_CACHE);
const bool align1 = brw_inst_access_mode(devinfo, p->current) == BRW_ALIGN_1;
/* Mask out unused components -- See comment in brw_untyped_atomic(). */
const unsigned mask = devinfo->gen == 7 && !devinfo->is_haswell && !align1 ?
WRITEMASK_X : WRITEMASK_XYZW;
struct brw_inst *insn = brw_send_indirect_surface_message(
p, sfid, brw_writemask(brw_null_reg(), mask),
payload, surface, msg_length, 0, align1);
brw_set_dp_untyped_surface_write_message(
p, insn, num_channels);
}
void
brw_pixel_interpolator_query(struct brw_codegen *p,
struct brw_reg dest,

4
src/mesa/drivers/dri/i965/brw_fs.cpp
View File

@ -502,6 +502,7 @@ fs_inst::is_send_from_grf() const
case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
case SHADER_OPCODE_UNTYPED_ATOMIC:
case SHADER_OPCODE_UNTYPED_SURFACE_READ:
case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
case SHADER_OPCODE_URB_WRITE_SIMD8:
return true;
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
@ -956,6 +957,8 @@ fs_inst::regs_read(int arg) const
return mlen;
} else if (opcode == SHADER_OPCODE_UNTYPED_SURFACE_READ && arg == 0) {
return mlen;
} else if (opcode == SHADER_OPCODE_UNTYPED_SURFACE_WRITE && arg == 0) {
return mlen;
} else if (opcode == FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET && arg == 0) {
return mlen;
} else if (opcode == FS_OPCODE_LINTERP && arg == 0) {
@ -1048,6 +1051,7 @@ fs_visitor::implied_mrf_writes(fs_inst *inst)
return 2;
case SHADER_OPCODE_UNTYPED_ATOMIC:
case SHADER_OPCODE_UNTYPED_SURFACE_READ:
case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
case SHADER_OPCODE_URB_WRITE_SIMD8:
case FS_OPCODE_INTERPOLATE_AT_CENTROID:
case FS_OPCODE_INTERPOLATE_AT_SAMPLE:

6
src/mesa/drivers/dri/i965/brw_fs_generator.cpp
View File

@ -2030,6 +2030,12 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
brw_mark_surface_used(prog_data, src[1].dw1.ud);
break;
case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
assert(src[2].file == BRW_IMMEDIATE_VALUE);
brw_untyped_surface_write(p, src[0], src[1],
inst->mlen, src[2].dw1.ud);
break;
case FS_OPCODE_SET_SIMD4X2_OFFSET:
generate_set_simd4x2_offset(inst, dst, src[0]);
break;

1
src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
View File

@ -358,6 +358,7 @@ schedule_node::set_latency_gen7(bool is_haswell)
break;
case SHADER_OPCODE_UNTYPED_SURFACE_READ:
case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
/* Test code:
* mov(8) g112<1>UD 0x00000000UD { align1 WE_all 1Q };
* mov(1) g112.7<1>UD g1.7<0,1,0>UD { align1 WE_all };

3
src/mesa/drivers/dri/i965/brw_shader.cpp
View File

@ -494,6 +494,8 @@ brw_instruction_name(enum opcode op)
return "untyped_atomic";
case SHADER_OPCODE_UNTYPED_SURFACE_READ:
return "untyped_surface_read";
case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
return "untyped_surface_write";
case SHADER_OPCODE_LOAD_PAYLOAD:
return "load_payload";
@ -1038,6 +1040,7 @@ backend_instruction::has_side_effects() const
switch (opcode) {
case SHADER_OPCODE_UNTYPED_ATOMIC:
case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
case SHADER_OPCODE_URB_WRITE_SIMD8:
case FS_OPCODE_FB_WRITE:
return true;

2
src/mesa/drivers/dri/i965/brw_vec4.cpp
View File

@ -216,6 +216,7 @@ vec4_instruction::is_send_from_grf()
case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
case SHADER_OPCODE_UNTYPED_ATOMIC:
case SHADER_OPCODE_UNTYPED_SURFACE_READ:
case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
return true;
default:
return false;
@ -232,6 +233,7 @@ vec4_instruction::regs_read(unsigned arg) const
case SHADER_OPCODE_SHADER_TIME_ADD:
case SHADER_OPCODE_UNTYPED_ATOMIC:
case SHADER_OPCODE_UNTYPED_SURFACE_READ:
case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
return arg == 0 ? mlen : 1;
case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:

6
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
View File

@ -1484,6 +1484,12 @@ vec4_generator::generate_code(const cfg_t *cfg)
brw_mark_surface_used(&prog_data->base, src[1].dw1.ud);
break;
case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
assert(src[2].file == BRW_IMMEDIATE_VALUE);
brw_untyped_surface_write(p, src[0], src[1], inst->mlen,
src[2].dw1.ud);
break;
case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
generate_unpack_flags(dst);
break;