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i965/gen6/gs: implement GS_OPCODE_SVB_SET_DST_INDEX opcode 

This opcode generates code to copy the specified destination index
into subregister 5 of the MRF message header.

Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
This commit is contained in:
Samuel Iglesias Gonsalvez 2014-07-18 10:47:15 +02:00 committed by Iago Toral Quiroga
parent e86ae1b0a3
commit 5933a08bd9
4 changed files with 33 additions and 0 deletions
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9
src/mesa/drivers/dri/i965/brw_defines.h
View File

@ -1055,6 +1055,15 @@ enum opcode {
* - src1 is the destination register when write commit occurs.
*/
GS_OPCODE_SVB_WRITE,
/**
* Set destination index in the SVB write message payload (M0.5). Used
* in gen6 for transform feedback.
*
* - dst is the header to save the destination indices for SVB WRITE.
* - src is the register that holds the destination indices value.
*/
GS_OPCODE_SVB_SET_DST_INDEX,
};
enum brw_derivative_quality {

2
src/mesa/drivers/dri/i965/brw_shader.cpp
View File

@ -530,6 +530,8 @@ brw_instruction_name(enum opcode op)
return "set_primitive_id";
case GS_OPCODE_SVB_WRITE:
return "gs_svb_write";
case GS_OPCODE_SVB_SET_DST_INDEX:
return "gs_svb_set_dst_index";
default:
/* Yes, this leaks. It's in debug code, it should never occur, and if

4
src/mesa/drivers/dri/i965/brw_vec4.h
View File

@ -222,6 +222,7 @@ public:
unsigned sol_binding; /**< gen6: SOL binding table index */
bool sol_final_write; /**< gen6: send commit message */
unsigned sol_vertex; /**< gen6: used for setting dst index in SVB header */
bool is_send_from_grf();
bool can_reswizzle(int dst_writemask, int swizzle, int swizzle_mask);
@ -661,6 +662,9 @@ private:
struct brw_reg dst,
struct brw_reg src0,
struct brw_reg src1);
void generate_gs_svb_set_destination_index(vec4_instruction *inst,
struct brw_reg dst,
struct brw_reg src);
void generate_gs_set_dword_2(struct brw_reg dst, struct brw_reg src);
void generate_gs_prepare_channel_masks(struct brw_reg dst);
void generate_gs_set_channel_masks(struct brw_reg dst, struct brw_reg src);

18
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
View File

@ -611,6 +611,20 @@ vec4_generator::generate_gs_svb_write(vec4_instruction *inst,
brw_pop_insn_state(p);
}
void
vec4_generator::generate_gs_svb_set_destination_index(vec4_instruction *inst,
struct brw_reg dst,
struct brw_reg src)
{
int vertex = inst->sol_vertex;
brw_push_insn_state(p);
brw_set_default_access_mode(p, BRW_ALIGN_1);
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
brw_MOV(p, get_element_ud(dst, 5), get_element_ud(src, vertex));
brw_pop_insn_state(p);
}
void
vec4_generator::generate_gs_set_dword_2(struct brw_reg dst, struct brw_reg src)
{
@ -1389,6 +1403,10 @@ vec4_generator::generate_code(const cfg_t *cfg)
generate_gs_svb_write(inst, dst, src[0], src[1]);
break;
case GS_OPCODE_SVB_SET_DST_INDEX:
generate_gs_svb_set_destination_index(inst, dst, src[0]);
break;
case GS_OPCODE_THREAD_END:
generate_gs_thread_end(inst);
break;