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i965: Fill out instruction list. 

Add some instructions: illegal, movi, sends, sendsc.

Remove some instructions with reused opcodes: msave, mrestore, push,
pop, goto. I did have some gross code for disassembling opcodes
per-generation, but there's very little meaningful overlap so it's
probably not needed.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Matt Turner 2015-06-29 14:03:55 -07:00
parent 238877207e
commit 0865e743c1
3 changed files with 42 additions and 14 deletions
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38
src/mesa/drivers/dri/i965/brw_defines.h
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@ -840,43 +840,62 @@ enum PACKED brw_horizontal_stride {
enum opcode {
/* These are the actual hardware opcodes. */
BRW_OPCODE_ILLEGAL = 0,
BRW_OPCODE_MOV = 1,
BRW_OPCODE_SEL = 2,
BRW_OPCODE_MOVI = 3, /**< G45+ */
BRW_OPCODE_NOT = 4,
BRW_OPCODE_AND = 5,
BRW_OPCODE_OR = 6,
BRW_OPCODE_XOR = 7,
BRW_OPCODE_SHR = 8,
BRW_OPCODE_SHL = 9,
// BRW_OPCODE_DIM = 10, /**< Gen7.5 only */ /* Reused */
// BRW_OPCODE_SMOV = 10, /**< Gen8+ */ /* Reused */
/* Reserved - 11 */
BRW_OPCODE_ASR = 12,
/* Reserved - 13-15 */
BRW_OPCODE_CMP = 16,
BRW_OPCODE_CMPN = 17,
BRW_OPCODE_CSEL = 18, /**< Gen8+ */
BRW_OPCODE_F32TO16 = 19, /**< Gen7 only */
BRW_OPCODE_F16TO32 = 20, /**< Gen7 only */
/* Reserved - 21-22 */
BRW_OPCODE_BFREV = 23, /**< Gen7+ */
BRW_OPCODE_BFE = 24, /**< Gen7+ */
BRW_OPCODE_BFI1 = 25, /**< Gen7+ */
BRW_OPCODE_BFI2 = 26, /**< Gen7+ */
/* Reserved - 27-31 */
BRW_OPCODE_JMPI = 32,
// BRW_OPCODE_BRD = 33, /**< Gen7+ */
BRW_OPCODE_IF = 34,
BRW_OPCODE_IFF = 35, /**< Pre-Gen6 */
BRW_OPCODE_IFF = 35, /**< Pre-Gen6 */ /* Reused */
// BRW_OPCODE_BRC = 35, /**< Gen7+ */ /* Reused */
BRW_OPCODE_ELSE = 36,
BRW_OPCODE_ENDIF = 37,
BRW_OPCODE_DO = 38,
BRW_OPCODE_DO = 38, /**< Pre-Gen6 */ /* Reused */
// BRW_OPCODE_CASE = 38, /**< Gen6 only */ /* Reused */
BRW_OPCODE_WHILE = 39,
BRW_OPCODE_BREAK = 40,
BRW_OPCODE_CONTINUE = 41,
BRW_OPCODE_HALT = 42,
BRW_OPCODE_MSAVE = 44, /**< Pre-Gen6 */
BRW_OPCODE_MRESTORE = 45, /**< Pre-Gen6 */
BRW_OPCODE_PUSH = 46, /**< Pre-Gen6 */
BRW_OPCODE_GOTO = 46, /**< Gen8+ */
BRW_OPCODE_POP = 47, /**< Pre-Gen6 */
// BRW_OPCODE_CALLA = 43, /**< Gen7.5+ */
// BRW_OPCODE_MSAVE = 44, /**< Pre-Gen6 */ /* Reused */
// BRW_OPCODE_CALL = 44, /**< Gen6+ */ /* Reused */
// BRW_OPCODE_MREST = 45, /**< Pre-Gen6 */ /* Reused */
// BRW_OPCODE_RET = 45, /**< Gen6+ */ /* Reused */
// BRW_OPCODE_PUSH = 46, /**< Pre-Gen6 */ /* Reused */
// BRW_OPCODE_FORK = 46, /**< Gen6 only */ /* Reused */
// BRW_OPCODE_GOTO = 46, /**< Gen8+ */ /* Reused */
// BRW_OPCODE_POP = 47, /**< Pre-Gen6 */
BRW_OPCODE_WAIT = 48,
BRW_OPCODE_SEND = 49,
BRW_OPCODE_SENDC = 50,
BRW_OPCODE_SENDS = 51, /**< Gen9+ */
BRW_OPCODE_SENDSC = 52, /**< Gen9+ */
/* Reserved 53-55 */
BRW_OPCODE_MATH = 56, /**< Gen6+ */
/* Reserved 57-63 */
BRW_OPCODE_ADD = 64,
BRW_OPCODE_MUL = 65,
BRW_OPCODE_AVG = 66,
@ -895,16 +914,21 @@ enum opcode {
BRW_OPCODE_SUBB = 79, /**< Gen7+ */
BRW_OPCODE_SAD2 = 80,
BRW_OPCODE_SADA2 = 81,
/* Reserved 82-83 */
BRW_OPCODE_DP4 = 84,
BRW_OPCODE_DPH = 85,
BRW_OPCODE_DP3 = 86,
BRW_OPCODE_DP2 = 87,
/* Reserved 88 */
BRW_OPCODE_LINE = 89,
BRW_OPCODE_PLN = 90, /**< G45+ */
BRW_OPCODE_MAD = 91, /**< Gen6+ */
BRW_OPCODE_LRP = 92, /**< Gen6+ */
// BRW_OPCODE_MADM = 93, /**< Gen8+ */
/* Reserved 94-124 */
BRW_OPCODE_NENOP = 125, /**< G45 only */
BRW_OPCODE_NOP = 126,
/* Reserved 127 */
/* These are compiler backend opcodes that get translated into other
* instructions.

16
src/mesa/drivers/dri/i965/brw_disasm.c
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@ -34,6 +34,7 @@
const struct opcode_desc opcode_descs[128] = {
[BRW_OPCODE_MOV] = { .name = "mov", .nsrc = 1, .ndst = 1 },
[BRW_OPCODE_MOVI] = { .name = "movi", .nsrc = 2, .ndst = 1 },
[BRW_OPCODE_FRC] = { .name = "frc", .nsrc = 1, .ndst = 1 },
[BRW_OPCODE_RNDU] = { .name = "rndu", .nsrc = 1, .ndst = 1 },
[BRW_OPCODE_RNDD] = { .name = "rndd", .nsrc = 1, .ndst = 1 },
@ -83,6 +84,9 @@ const struct opcode_desc opcode_descs[128] = {
[BRW_OPCODE_SEND] = { .name = "send", .nsrc = 1, .ndst = 1 },
[BRW_OPCODE_SENDC] = { .name = "sendc", .nsrc = 1, .ndst = 1 },
[BRW_OPCODE_SENDS] = { .name = "sends", .nsrc = 2, .ndst = 1 },
[BRW_OPCODE_SENDSC] = { .name = "sendsc", .nsrc = 2, .ndst = 1 },
[BRW_OPCODE_ILLEGAL] = { .name = "illegal", .nsrc = 0, .ndst = 0 },
[BRW_OPCODE_NOP] = { .name = "nop", .nsrc = 0, .ndst = 0 },
[BRW_OPCODE_NENOP] = { .name = "nenop", .nsrc = 0, .ndst = 0 },
[BRW_OPCODE_JMPI] = { .name = "jmpi", .nsrc = 0, .ndst = 0 },
@ -93,10 +97,10 @@ const struct opcode_desc opcode_descs[128] = {
[BRW_OPCODE_BREAK] = { .name = "break", .nsrc = 2, .ndst = 0 },
[BRW_OPCODE_CONTINUE] = { .name = "cont", .nsrc = 1, .ndst = 0 },
[BRW_OPCODE_HALT] = { .name = "halt", .nsrc = 1, .ndst = 0 },
[BRW_OPCODE_MSAVE] = { .name = "msave", .nsrc = 1, .ndst = 1 },
[BRW_OPCODE_PUSH] = { .name = "push", .nsrc = 1, .ndst = 1 },
[BRW_OPCODE_MRESTORE] = { .name = "mrest", .nsrc = 1, .ndst = 1 },
[BRW_OPCODE_POP] = { .name = "pop", .nsrc = 2, .ndst = 0 },
// [BRW_OPCODE_MSAVE] = { .name = "msave", .nsrc = 1, .ndst = 1 },
// [BRW_OPCODE_PUSH] = { .name = "push", .nsrc = 1, .ndst = 1 },
// [BRW_OPCODE_MREST] = { .name = "mrest", .nsrc = 1, .ndst = 1 },
// [BRW_OPCODE_POP] = { .name = "pop", .nsrc = 2, .ndst = 0 },
[BRW_OPCODE_WAIT] = { .name = "wait", .nsrc = 1, .ndst = 0 },
[BRW_OPCODE_DO] = { .name = "do", .nsrc = 0, .ndst = 0 },
[BRW_OPCODE_ENDIF] = { .name = "endif", .nsrc = 2, .ndst = 0 },
@ -137,8 +141,8 @@ has_branch_ctrl(const struct brw_device_info *devinfo, enum opcode opcode)
return false;
return opcode == BRW_OPCODE_IF ||
opcode == BRW_OPCODE_ELSE ||
opcode == BRW_OPCODE_GOTO;
opcode == BRW_OPCODE_ELSE;
/* opcode == BRW_OPCODE_GOTO; */
}
static bool

2
src/mesa/drivers/dri/i965/brw_shader.cpp
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@ -290,7 +290,7 @@ const char *
brw_instruction_name(enum opcode op)
{
switch (op) {
case BRW_OPCODE_MOV ... BRW_OPCODE_NOP:
case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
assert(opcode_descs[op].name);
return opcode_descs[op].name;
case FS_OPCODE_FB_WRITE: