KonstantinSeurer
/
mesa
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

i965: Make 'dw1' and 'bits' unnamed structures in brw_reg. 

Generated by

   sed -i -e 's/\.bits\././g' *.c *.h *.cpp
   sed -i -e 's/dw1\.//g' *.c *.h *.cpp

and then reverting changes to comments in gen7_blorp.cpp and
brw_fs_generator.cpp.

There wasn't any utility offered by forcing the programmer to list these
to access their fields. Removing them will reduce churn in future
commits.

This is C11 (and gcc has apparently supported it for sometime
"compatibility with other compilers")

See https://gcc.gnu.org/onlinedocs/gcc/Unnamed-Fields.html

Reviewed-by: Emil Velikov <emil.velikov@collabora.co.uk>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Matt Turner 2015-10-22 19:41:30 -07:00
parent 182f137521
commit e42fb0c2a6
14 changed files with 185 additions and 178 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

52
src/mesa/drivers/dri/i965/brw_eu_emit.c
View File

@ -169,10 +169,10 @@ brw_set_dest(struct brw_codegen *p, brw_inst *inst, struct brw_reg dest)
brw_inst_set_dst_hstride(devinfo, inst, dest.hstride);
} else {
brw_inst_set_dst_da16_subreg_nr(devinfo, inst, dest.subnr / 16);
brw_inst_set_da16_writemask(devinfo, inst, dest.dw1.bits.writemask);
brw_inst_set_da16_writemask(devinfo, inst, dest.writemask);
if (dest.file == BRW_GENERAL_REGISTER_FILE ||
dest.file == BRW_MESSAGE_REGISTER_FILE) {
assert(dest.dw1.bits.writemask != 0);
assert(dest.writemask != 0);
}
/* From the Ivybridge PRM, Vol 4, Part 3, Section 5.2.4.1:
* Although Dst.HorzStride is a don't care for Align16, HW needs
@ -187,13 +187,13 @@ brw_set_dest(struct brw_codegen *p, brw_inst *inst, struct brw_reg dest)
*/
if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
brw_inst_set_dst_ia1_addr_imm(devinfo, inst,
dest.dw1.bits.indirect_offset);
dest.indirect_offset);
if (dest.hstride == BRW_HORIZONTAL_STRIDE_0)
dest.hstride = BRW_HORIZONTAL_STRIDE_1;
brw_inst_set_dst_hstride(devinfo, inst, dest.hstride);
} else {
brw_inst_set_dst_ia16_addr_imm(devinfo, inst,
dest.dw1.bits.indirect_offset);
dest.indirect_offset);
/* even ignored in da16, still need to set as '01' */
brw_inst_set_dst_hstride(devinfo, inst, 1);
}
@ -243,7 +243,7 @@ validate_reg(const struct brw_device_info *devinfo,
*/
if (reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
reg.nr == BRW_ARF_ACCUMULATOR)
assert(reg.dw1.bits.swizzle == BRW_SWIZZLE_XYZW);
assert(reg.swizzle == BRW_SWIZZLE_XYZW);
assert(reg.hstride >= 0 && reg.hstride < ARRAY_SIZE(hstride_for_reg));
hstride = hstride_for_reg[reg.hstride];
@ -338,7 +338,7 @@ brw_set_src0(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg)
brw_inst_set_src0_address_mode(devinfo, inst, reg.address_mode);
if (reg.file == BRW_IMMEDIATE_VALUE) {
brw_inst_set_imm_ud(devinfo, inst, reg.dw1.ud);
brw_inst_set_imm_ud(devinfo, inst, reg.ud);
/* The Bspec's section titled "Non-present Operands" claims that if src0
* is an immediate that src1's type must be the same as that of src0.
@ -408,9 +408,9 @@ brw_set_src0(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg)
brw_inst_set_src0_ia_subreg_nr(devinfo, inst, reg.subnr);
if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
brw_inst_set_src0_ia1_addr_imm(devinfo, inst, reg.dw1.bits.indirect_offset);
brw_inst_set_src0_ia1_addr_imm(devinfo, inst, reg.indirect_offset);
} else {
brw_inst_set_src0_ia16_addr_imm(devinfo, inst, reg.dw1.bits.indirect_offset);
brw_inst_set_src0_ia16_addr_imm(devinfo, inst, reg.indirect_offset);
}
}
@ -427,13 +427,13 @@ brw_set_src0(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg)
}
} else {
brw_inst_set_src0_da16_swiz_x(devinfo, inst,
BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_X));
BRW_GET_SWZ(reg.swizzle, BRW_CHANNEL_X));
brw_inst_set_src0_da16_swiz_y(devinfo, inst,
BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_Y));
BRW_GET_SWZ(reg.swizzle, BRW_CHANNEL_Y));
brw_inst_set_src0_da16_swiz_z(devinfo, inst,
BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_Z));
BRW_GET_SWZ(reg.swizzle, BRW_CHANNEL_Z));
brw_inst_set_src0_da16_swiz_w(devinfo, inst,
BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_W));
BRW_GET_SWZ(reg.swizzle, BRW_CHANNEL_W));
/* This is an oddity of the fact we're using the same
* descriptions for registers in align_16 as align_1:
@ -479,7 +479,7 @@ brw_set_src1(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg)
assert(brw_inst_src0_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE);
if (reg.file == BRW_IMMEDIATE_VALUE) {
brw_inst_set_imm_ud(devinfo, inst, reg.dw1.ud);
brw_inst_set_imm_ud(devinfo, inst, reg.ud);
} else {
/* This is a hardware restriction, which may or may not be lifted
* in the future:
@ -507,13 +507,13 @@ brw_set_src1(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg)
}
} else {
brw_inst_set_src1_da16_swiz_x(devinfo, inst,
BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_X));
BRW_GET_SWZ(reg.swizzle, BRW_CHANNEL_X));
brw_inst_set_src1_da16_swiz_y(devinfo, inst,
BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_Y));
BRW_GET_SWZ(reg.swizzle, BRW_CHANNEL_Y));
brw_inst_set_src1_da16_swiz_z(devinfo, inst,
BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_Z));
BRW_GET_SWZ(reg.swizzle, BRW_CHANNEL_Z));
brw_inst_set_src1_da16_swiz_w(devinfo, inst,
BRW_GET_SWZ(reg.dw1.bits.swizzle, BRW_CHANNEL_W));
BRW_GET_SWZ(reg.swizzle, BRW_CHANNEL_W));
/* This is an oddity of the fact we're using the same
* descriptions for registers in align_16 as align_1:
@ -848,8 +848,8 @@ static int
get_3src_subreg_nr(struct brw_reg reg)
{
if (reg.vstride == BRW_VERTICAL_STRIDE_0) {
assert(brw_is_single_value_swizzle(reg.dw1.bits.swizzle));
return reg.subnr / 4 + BRW_GET_SWZ(reg.dw1.bits.swizzle, 0);
assert(brw_is_single_value_swizzle(reg.swizzle));
return reg.subnr / 4 + BRW_GET_SWZ(reg.swizzle, 0);
} else {
return reg.subnr / 4;
}
@ -879,12 +879,12 @@ brw_alu3(struct brw_codegen *p, unsigned opcode, struct brw_reg dest,
}
brw_inst_set_3src_dst_reg_nr(devinfo, inst, dest.nr);
brw_inst_set_3src_dst_subreg_nr(devinfo, inst, dest.subnr / 16);
brw_inst_set_3src_dst_writemask(devinfo, inst, dest.dw1.bits.writemask);
brw_inst_set_3src_dst_writemask(devinfo, inst, dest.writemask);
assert(src0.file == BRW_GENERAL_REGISTER_FILE);
assert(src0.address_mode == BRW_ADDRESS_DIRECT);
assert(src0.nr < 128);
brw_inst_set_3src_src0_swizzle(devinfo, inst, src0.dw1.bits.swizzle);
brw_inst_set_3src_src0_swizzle(devinfo, inst, src0.swizzle);
brw_inst_set_3src_src0_subreg_nr(devinfo, inst, get_3src_subreg_nr(src0));
brw_inst_set_3src_src0_reg_nr(devinfo, inst, src0.nr);
brw_inst_set_3src_src0_abs(devinfo, inst, src0.abs);
@ -895,7 +895,7 @@ brw_alu3(struct brw_codegen *p, unsigned opcode, struct brw_reg dest,
assert(src1.file == BRW_GENERAL_REGISTER_FILE);
assert(src1.address_mode == BRW_ADDRESS_DIRECT);
assert(src1.nr < 128);
brw_inst_set_3src_src1_swizzle(devinfo, inst, src1.dw1.bits.swizzle);
brw_inst_set_3src_src1_swizzle(devinfo, inst, src1.swizzle);
brw_inst_set_3src_src1_subreg_nr(devinfo, inst, get_3src_subreg_nr(src1));
brw_inst_set_3src_src1_reg_nr(devinfo, inst, src1.nr);
brw_inst_set_3src_src1_abs(devinfo, inst, src1.abs);
@ -906,7 +906,7 @@ brw_alu3(struct brw_codegen *p, unsigned opcode, struct brw_reg dest,
assert(src2.file == BRW_GENERAL_REGISTER_FILE);
assert(src2.address_mode == BRW_ADDRESS_DIRECT);
assert(src2.nr < 128);
brw_inst_set_3src_src2_swizzle(devinfo, inst, src2.dw1.bits.swizzle);
brw_inst_set_3src_src2_swizzle(devinfo, inst, src2.swizzle);
brw_inst_set_3src_src2_subreg_nr(devinfo, inst, get_3src_subreg_nr(src2));
brw_inst_set_3src_src2_reg_nr(devinfo, inst, src2.nr);
brw_inst_set_3src_src2_abs(devinfo, inst, src2.abs);
@ -2426,7 +2426,7 @@ void brw_adjust_sampler_state_pointer(struct brw_codegen *p,
if (sampler_index.file == BRW_IMMEDIATE_VALUE) {
const int sampler_state_size = 16; /* 16 bytes */
uint32_t sampler = sampler_index.dw1.ud;
uint32_t sampler = sampler_index.ud;
if (sampler >= 16) {
assert(devinfo->is_haswell || devinfo->gen >= 8);
@ -2581,7 +2581,7 @@ brw_send_indirect_surface_message(struct brw_codegen *p,
*/
insn = brw_AND(p, addr,
suboffset(vec1(retype(surface, BRW_REGISTER_TYPE_UD)),
BRW_GET_SWZ(surface.dw1.bits.swizzle, 0)),
BRW_GET_SWZ(surface.swizzle, 0)),
brw_imm_ud(0xff));
brw_pop_insn_state(p);
@ -3336,7 +3336,7 @@ brw_broadcast(struct brw_codegen *p,
* We will typically not get here if the optimizer is doing its job, but
* asserting would be mean.
*/
const unsigned i = idx.file == BRW_IMMEDIATE_VALUE ? idx.dw1.ud : 0;
const unsigned i = idx.file == BRW_IMMEDIATE_VALUE ? idx.ud : 0;
brw_MOV(p, dst,
(align1 ? stride(suboffset(src, i), 0, 1, 0) :
stride(suboffset(src, 4 * i), 0, 4, 1)));

2
src/mesa/drivers/dri/i965/brw_ff_gs_emit.c
View File

@ -436,7 +436,7 @@ gen6_sol_program(struct brw_ff_gs_compile *c, struct brw_ff_gs_prog_key *key,
vertex_slot.nr += slot / 2;
vertex_slot.subnr = (slot % 2) * 16;
/* gl_PointSize is stored in VARYING_SLOT_PSIZ.w. */
vertex_slot.dw1.bits.swizzle = varying == VARYING_SLOT_PSIZ
vertex_slot.swizzle = varying == VARYING_SLOT_PSIZ
? BRW_SWIZZLE_WWWW : key->transform_feedback_swizzles[binding];
brw_set_default_access_mode(p, BRW_ALIGN_16);
brw_MOV(p, stride(c->reg.header, 4, 4, 1),

74
src/mesa/drivers/dri/i965/brw_fs.cpp
View File

@ -379,7 +379,7 @@ fs_reg::fs_reg(float f)
this->file = IMM;
this->type = BRW_REGISTER_TYPE_F;
this->stride = 0;
this->fixed_hw_reg.dw1.f = f;
this->fixed_hw_reg.f = f;
}
/** Immediate value constructor. */
@ -389,7 +389,7 @@ fs_reg::fs_reg(int32_t i)
this->file = IMM;
this->type = BRW_REGISTER_TYPE_D;
this->stride = 0;
this->fixed_hw_reg.dw1.d = i;
this->fixed_hw_reg.d = i;
}
/** Immediate value constructor. */
@ -399,7 +399,7 @@ fs_reg::fs_reg(uint32_t u)
this->file = IMM;
this->type = BRW_REGISTER_TYPE_UD;
this->stride = 0;
this->fixed_hw_reg.dw1.ud = u;
this->fixed_hw_reg.ud = u;
}
/** Vector float immediate value constructor. */
@ -408,7 +408,7 @@ fs_reg::fs_reg(uint8_t vf[4])
init();
this->file = IMM;
this->type = BRW_REGISTER_TYPE_VF;
memcpy(&this->fixed_hw_reg.dw1.ud, vf, sizeof(unsigned));
memcpy(&this->fixed_hw_reg.ud, vf, sizeof(unsigned));
}
/** Vector float immediate value constructor. */
@ -417,7 +417,7 @@ fs_reg::fs_reg(uint8_t vf0, uint8_t vf1, uint8_t vf2, uint8_t vf3)
init();
this->file = IMM;
this->type = BRW_REGISTER_TYPE_VF;
this->fixed_hw_reg.dw1.ud = (vf0 << 0) |
this->fixed_hw_reg.ud = (vf0 << 0) |
(vf1 << 8) |
(vf2 << 16) |
(vf3 << 24);
@ -719,7 +719,7 @@ fs_inst::components_read(unsigned i) const
assert(src[FB_WRITE_LOGICAL_SRC_COMPONENTS].file == IMM);
/* First/second FB write color. */
if (i < 2)
return src[FB_WRITE_LOGICAL_SRC_COMPONENTS].fixed_hw_reg.dw1.ud;
return src[FB_WRITE_LOGICAL_SRC_COMPONENTS].fixed_hw_reg.ud;
else
return 1;
@ -739,10 +739,10 @@ fs_inst::components_read(unsigned i) const
assert(src[8].file == IMM && src[9].file == IMM);
/* Texture coordinates. */
if (i == 0)
return src[8].fixed_hw_reg.dw1.ud;
return src[8].fixed_hw_reg.ud;
/* Texture derivatives. */
else if ((i == 2 || i == 3) && opcode == SHADER_OPCODE_TXD_LOGICAL)
return src[9].fixed_hw_reg.dw1.ud;
return src[9].fixed_hw_reg.ud;
/* Texture offset. */
else if (i == 7)
return 2;
@ -757,7 +757,7 @@ fs_inst::components_read(unsigned i) const
assert(src[3].file == IMM);
/* Surface coordinates. */
if (i == 0)
return src[3].fixed_hw_reg.dw1.ud;
return src[3].fixed_hw_reg.ud;
/* Surface operation source (ignored for reads). */
else if (i == 1)
return 0;
@ -770,10 +770,10 @@ fs_inst::components_read(unsigned i) const
src[4].file == IMM);
/* Surface coordinates. */
if (i == 0)
return src[3].fixed_hw_reg.dw1.ud;
return src[3].fixed_hw_reg.ud;
/* Surface operation source. */
else if (i == 1)
return src[4].fixed_hw_reg.dw1.ud;
return src[4].fixed_hw_reg.ud;
else
return 1;
@ -781,10 +781,10 @@ fs_inst::components_read(unsigned i) const
case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL: {
assert(src[3].file == IMM &&
src[4].file == IMM);
const unsigned op = src[4].fixed_hw_reg.dw1.ud;
const unsigned op = src[4].fixed_hw_reg.ud;
/* Surface coordinates. */
if (i == 0)
return src[3].fixed_hw_reg.dw1.ud;
return src[3].fixed_hw_reg.ud;
/* Surface operation source. */
else if (i == 1 && op == BRW_AOP_CMPWR)
return 2;
@ -1666,11 +1666,11 @@ fs_visitor::assign_gs_urb_setup()
if (inst->opcode == SHADER_OPCODE_URB_READ_SIMD8) {
assert(inst->src[0].file == IMM);
inst->src[0] = retype(brw_vec8_grf(first_icp_handle +
inst->src[0].fixed_hw_reg.dw1.ud,
inst->src[0].fixed_hw_reg.ud,
0), BRW_REGISTER_TYPE_UD);
/* for now, assume constant - we can do per-slot offsets later */
assert(inst->src[1].file == IMM);
inst->offset = inst->src[1].fixed_hw_reg.dw1.ud;
inst->offset = inst->src[1].fixed_hw_reg.ud;
inst->src[1] = fs_reg();
inst->mlen = 1;
inst->base_mrf = -1;
@ -2112,7 +2112,7 @@ fs_visitor::opt_algebraic()
if (inst->src[0].file == IMM) {
assert(inst->src[0].type == BRW_REGISTER_TYPE_F);
inst->opcode = BRW_OPCODE_MOV;
inst->src[0].fixed_hw_reg.dw1.f *= inst->src[1].fixed_hw_reg.dw1.f;
inst->src[0].fixed_hw_reg.f *= inst->src[1].fixed_hw_reg.f;
inst->src[1] = reg_undef;
progress = true;
break;
@ -2133,7 +2133,7 @@ fs_visitor::opt_algebraic()
if (inst->src[0].file == IMM) {
assert(inst->src[0].type == BRW_REGISTER_TYPE_F);
inst->opcode = BRW_OPCODE_MOV;
inst->src[0].fixed_hw_reg.dw1.f += inst->src[1].fixed_hw_reg.dw1.f;
inst->src[0].fixed_hw_reg.f += inst->src[1].fixed_hw_reg.f;
inst->src[1] = reg_undef;
progress = true;
break;
@ -2182,7 +2182,7 @@ fs_visitor::opt_algebraic()
case BRW_CONDITIONAL_L:
switch (inst->src[1].type) {
case BRW_REGISTER_TYPE_F:
if (inst->src[1].fixed_hw_reg.dw1.f >= 1.0f) {
if (inst->src[1].fixed_hw_reg.f >= 1.0f) {
inst->opcode = BRW_OPCODE_MOV;
inst->src[1] = reg_undef;
inst->conditional_mod = BRW_CONDITIONAL_NONE;
@ -2197,7 +2197,7 @@ fs_visitor::opt_algebraic()
case BRW_CONDITIONAL_G:
switch (inst->src[1].type) {
case BRW_REGISTER_TYPE_F:
if (inst->src[1].fixed_hw_reg.dw1.f <= 0.0f) {
if (inst->src[1].fixed_hw_reg.f <= 0.0f) {
inst->opcode = BRW_OPCODE_MOV;
inst->src[1] = reg_undef;
inst->conditional_mod = BRW_CONDITIONAL_NONE;
@ -2234,7 +2234,7 @@ fs_visitor::opt_algebraic()
progress = true;
} else if (inst->src[1].file == IMM && inst->src[2].file == IMM) {
inst->opcode = BRW_OPCODE_ADD;
inst->src[1].fixed_hw_reg.dw1.f *= inst->src[2].fixed_hw_reg.dw1.f;
inst->src[1].fixed_hw_reg.f *= inst->src[2].fixed_hw_reg.f;
inst->src[2] = reg_undef;
progress = true;
}
@ -2259,7 +2259,7 @@ fs_visitor::opt_algebraic()
} else if (inst->src[1].file == IMM) {
inst->opcode = BRW_OPCODE_MOV;
inst->src[0] = component(inst->src[0],
inst->src[1].fixed_hw_reg.dw1.ud);
inst->src[1].fixed_hw_reg.ud);
inst->sources = 1;
inst->force_writemask_all = true;
progress = true;
@ -3081,7 +3081,7 @@ fs_visitor::lower_uniform_pull_constant_loads()
fs_reg const_offset_reg = inst->src[1];
assert(const_offset_reg.file == IMM &&
const_offset_reg.type == BRW_REGISTER_TYPE_UD);
const_offset_reg.fixed_hw_reg.dw1.ud /= 4;
const_offset_reg.fixed_hw_reg.ud /= 4;
fs_reg payload, offset;
if (devinfo->gen >= 9) {
@ -3250,7 +3250,7 @@ fs_visitor::lower_integer_multiplication()
continue;
if (inst->src[1].file == IMM &&
inst->src[1].fixed_hw_reg.dw1.ud < (1 << 16)) {
inst->src[1].fixed_hw_reg.ud < (1 << 16)) {
/* The MUL instruction isn't commutative. On Gen <= 6, only the low
* 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
* src1 are used.
@ -3326,8 +3326,8 @@ fs_visitor::lower_integer_multiplication()
fs_reg src1_1_w = inst->src[1];
if (inst->src[1].file == IMM) {
src1_0_w.fixed_hw_reg.dw1.ud &= 0xffff;
src1_1_w.fixed_hw_reg.dw1.ud >>= 16;
src1_0_w.fixed_hw_reg.ud &= 0xffff;
src1_1_w.fixed_hw_reg.ud >>= 16;
} else {
src1_0_w.type = BRW_REGISTER_TYPE_UW;
if (src1_0_w.stride != 0) {
@ -3482,7 +3482,7 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst,
const fs_reg &src_stencil = inst->src[FB_WRITE_LOGICAL_SRC_SRC_STENCIL];
fs_reg sample_mask = inst->src[FB_WRITE_LOGICAL_SRC_OMASK];
const unsigned components =
inst->src[FB_WRITE_LOGICAL_SRC_COMPONENTS].fixed_hw_reg.dw1.ud;
inst->src[FB_WRITE_LOGICAL_SRC_COMPONENTS].fixed_hw_reg.ud;
/* We can potentially have a message length of up to 15, so we have to set
* base_mrf to either 0 or 1 in order to fit in m0..m15.
@ -3822,7 +3822,7 @@ is_high_sampler(const struct brw_device_info *devinfo, const fs_reg &sampler)
if (devinfo->gen < 8 && !devinfo->is_haswell)
return false;
return sampler.file != IMM || sampler.fixed_hw_reg.dw1.ud >= 16;
return sampler.file != IMM || sampler.fixed_hw_reg.ud >= 16;
}
static void
@ -4057,8 +4057,8 @@ lower_sampler_logical_send(const fs_builder &bld, fs_inst *inst, opcode op)
const fs_reg &sampler = inst->src[6];
const fs_reg &offset_value = inst->src[7];
assert(inst->src[8].file == IMM && inst->src[9].file == IMM);
const unsigned coord_components = inst->src[8].fixed_hw_reg.dw1.ud;
const unsigned grad_components = inst->src[9].fixed_hw_reg.dw1.ud;
const unsigned coord_components = inst->src[8].fixed_hw_reg.ud;
const unsigned grad_components = inst->src[9].fixed_hw_reg.ud;
if (devinfo->gen >= 7) {
lower_sampler_logical_send_gen7(bld, inst, op, coordinate,
@ -4384,7 +4384,7 @@ get_lowered_simd_width(const struct brw_device_info *devinfo,
* circumstances it can end up with a message that is too long in SIMD16
* mode.
*/
const unsigned coord_components = inst->src[8].fixed_hw_reg.dw1.ud;
const unsigned coord_components = inst->src[8].fixed_hw_reg.ud;
/* First three arguments are the sample index and the two arguments for
* the MCS data.
*/
@ -4692,22 +4692,22 @@ fs_visitor::dump_instruction(backend_instruction *be_inst, FILE *file)
case IMM:
switch (inst->src[i].type) {
case BRW_REGISTER_TYPE_F:
fprintf(file, "%ff", inst->src[i].fixed_hw_reg.dw1.f);
fprintf(file, "%ff", inst->src[i].fixed_hw_reg.f);
break;
case BRW_REGISTER_TYPE_W:
case BRW_REGISTER_TYPE_D:
fprintf(file, "%dd", inst->src[i].fixed_hw_reg.dw1.d);
fprintf(file, "%dd", inst->src[i].fixed_hw_reg.d);
break;
case BRW_REGISTER_TYPE_UW:
case BRW_REGISTER_TYPE_UD:
fprintf(file, "%uu", inst->src[i].fixed_hw_reg.dw1.ud);
fprintf(file, "%uu", inst->src[i].fixed_hw_reg.ud);
break;
case BRW_REGISTER_TYPE_VF:
fprintf(file, "[%-gF, %-gF, %-gF, %-gF]",
brw_vf_to_float((inst->src[i].fixed_hw_reg.dw1.ud >> 0) & 0xff),
brw_vf_to_float((inst->src[i].fixed_hw_reg.dw1.ud >> 8) & 0xff),
brw_vf_to_float((inst->src[i].fixed_hw_reg.dw1.ud >> 16) & 0xff),
brw_vf_to_float((inst->src[i].fixed_hw_reg.dw1.ud >> 24) & 0xff));
brw_vf_to_float((inst->src[i].fixed_hw_reg.ud >> 0) & 0xff),
brw_vf_to_float((inst->src[i].fixed_hw_reg.ud >> 8) & 0xff),
brw_vf_to_float((inst->src[i].fixed_hw_reg.ud >> 16) & 0xff),
brw_vf_to_float((inst->src[i].fixed_hw_reg.ud >> 24) & 0xff));
break;
default:
fprintf(file, "???");

6
src/mesa/drivers/dri/i965/brw_fs_combine_constants.cpp
View File

@ -219,7 +219,7 @@ fs_visitor::opt_combine_constants()
inst->src[i].type != BRW_REGISTER_TYPE_F)
continue;
float val = fabsf(inst->src[i].fixed_hw_reg.dw1.f);
float val = fabsf(inst->src[i].fixed_hw_reg.f);
struct imm *imm = find_imm(&table, val);
if (imm) {
@ -299,9 +299,9 @@ fs_visitor::opt_combine_constants()
reg->reg = table.imm[i].reg;
reg->subreg_offset = table.imm[i].subreg_offset;
reg->stride = 0;
reg->negate = signbit(reg->fixed_hw_reg.dw1.f) !=
reg->negate = signbit(reg->fixed_hw_reg.f) !=
signbit(table.imm[i].val);
assert(fabsf(reg->fixed_hw_reg.dw1.f) == table.imm[i].val);
assert(fabsf(reg->fixed_hw_reg.f) == table.imm[i].val);
}
}

8
src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp
View File

@ -369,8 +369,8 @@ fs_visitor::try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry)
switch(inst->opcode) {
case BRW_OPCODE_SEL:
if (inst->src[1].file != IMM ||
inst->src[1].fixed_hw_reg.dw1.f < 0.0 ||
inst->src[1].fixed_hw_reg.dw1.f > 1.0) {
inst->src[1].fixed_hw_reg.f < 0.0 ||
inst->src[1].fixed_hw_reg.f > 1.0) {
return false;
}
break;
@ -605,10 +605,10 @@ fs_visitor::try_constant_propagate(fs_inst *inst, acp_entry *entry)
* anyway.
*/
assert(i == 0);
if (inst->src[0].fixed_hw_reg.dw1.f != 0.0f) {
if (inst->src[0].fixed_hw_reg.f != 0.0f) {
inst->opcode = BRW_OPCODE_MOV;
inst->src[0] = val;
inst->src[0].fixed_hw_reg.dw1.f = 1.0f / inst->src[0].fixed_hw_reg.dw1.f;
inst->src[0].fixed_hw_reg.f = 1.0f / inst->src[0].fixed_hw_reg.f;
progress = true;
}
break;

16
src/mesa/drivers/dri/i965/brw_fs_cse.cpp
View File

@ -110,20 +110,20 @@ operands_match(const fs_inst *a, const fs_inst *b, bool *negate)
(xs[2].equals(ys[1]) && xs[1].equals(ys[2])));
} else if (a->opcode == BRW_OPCODE_MUL && a->dst.type == BRW_REGISTER_TYPE_F) {
bool xs0_negate = xs[0].negate;
bool xs1_negate = xs[1].file == IMM ? xs[1].fixed_hw_reg.dw1.f < 0.0f
bool xs1_negate = xs[1].file == IMM ? xs[1].fixed_hw_reg.f < 0.0f
: xs[1].negate;
bool ys0_negate = ys[0].negate;
bool ys1_negate = ys[1].file == IMM ? ys[1].fixed_hw_reg.dw1.f < 0.0f
bool ys1_negate = ys[1].file == IMM ? ys[1].fixed_hw_reg.f < 0.0f
: ys[1].negate;
float xs1_imm = xs[1].fixed_hw_reg.dw1.f;
float ys1_imm = ys[1].fixed_hw_reg.dw1.f;
float xs1_imm = xs[1].fixed_hw_reg.f;
float ys1_imm = ys[1].fixed_hw_reg.f;
xs[0].negate = false;
xs[1].negate = false;
ys[0].negate = false;
ys[1].negate = false;
xs[1].fixed_hw_reg.dw1.f = fabsf(xs[1].fixed_hw_reg.dw1.f);
ys[1].fixed_hw_reg.dw1.f = fabsf(ys[1].fixed_hw_reg.dw1.f);
xs[1].fixed_hw_reg.f = fabsf(xs[1].fixed_hw_reg.f);
ys[1].fixed_hw_reg.f = fabsf(ys[1].fixed_hw_reg.f);
bool ret = (xs[0].equals(ys[0]) && xs[1].equals(ys[1])) ||
(xs[1].equals(ys[0]) && xs[0].equals(ys[1]));
@ -132,8 +132,8 @@ operands_match(const fs_inst *a, const fs_inst *b, bool *negate)
xs[1].negate = xs[1].file == IMM ? false : xs1_negate;
ys[0].negate = ys0_negate;
ys[1].negate = ys[1].file == IMM ? false : ys1_negate;
xs[1].fixed_hw_reg.dw1.f = xs1_imm;
ys[1].fixed_hw_reg.dw1.f = ys1_imm;
xs[1].fixed_hw_reg.f = xs1_imm;
ys[1].fixed_hw_reg.f = ys1_imm;
*negate = (xs0_negate != xs1_negate) != (ys0_negate != ys1_negate);
return ret;

42
src/mesa/drivers/dri/i965/brw_fs_generator.cpp
View File

@ -91,22 +91,22 @@ brw_reg_from_fs_reg(fs_inst *inst, fs_reg *reg, unsigned gen)
switch (reg->type) {
case BRW_REGISTER_TYPE_F:
brw_reg = brw_imm_f(reg->fixed_hw_reg.dw1.f);
brw_reg = brw_imm_f(reg->fixed_hw_reg.f);
break;
case BRW_REGISTER_TYPE_D:
brw_reg = brw_imm_d(reg->fixed_hw_reg.dw1.d);
brw_reg = brw_imm_d(reg->fixed_hw_reg.d);
break;
case BRW_REGISTER_TYPE_UD:
brw_reg = brw_imm_ud(reg->fixed_hw_reg.dw1.ud);
brw_reg = brw_imm_ud(reg->fixed_hw_reg.ud);
break;
case BRW_REGISTER_TYPE_W:
brw_reg = brw_imm_w(reg->fixed_hw_reg.dw1.d);
brw_reg = brw_imm_w(reg->fixed_hw_reg.d);
break;
case BRW_REGISTER_TYPE_UW:
brw_reg = brw_imm_uw(reg->fixed_hw_reg.dw1.ud);
brw_reg = brw_imm_uw(reg->fixed_hw_reg.ud);
break;
case BRW_REGISTER_TYPE_VF:
brw_reg = brw_imm_vf(reg->fixed_hw_reg.dw1.ud);
brw_reg = brw_imm_vf(reg->fixed_hw_reg.ud);
break;
default:
unreachable("not reached");
@ -658,7 +658,7 @@ fs_generator::generate_get_buffer_size(fs_inst *inst,
retype(dst, BRW_REGISTER_TYPE_UW),
inst->base_mrf,
src,
surf_index.dw1.ud,
surf_index.ud,
0,
GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO,
rlen, /* response length */
@ -666,6 +666,8 @@ fs_generator::generate_get_buffer_size(fs_inst *inst,
inst->header_size > 0,
simd_mode,
BRW_SAMPLER_RETURN_FORMAT_SINT32);
brw_mark_surface_used(prog_data, surf_index.ud);
}
void
@ -907,7 +909,7 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src
: prog_data->binding_table.texture_start;
if (sampler_index.file == BRW_IMMEDIATE_VALUE) {
uint32_t sampler = sampler_index.dw1.ud;
uint32_t sampler = sampler_index.ud;
brw_SAMPLE(p,
retype(dst, BRW_REGISTER_TYPE_UW),
@ -1174,11 +1176,11 @@ fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
assert(index.file == BRW_IMMEDIATE_VALUE &&
index.type == BRW_REGISTER_TYPE_UD);
uint32_t surf_index = index.dw1.ud;
uint32_t surf_index = index.ud;
assert(offset.file == BRW_IMMEDIATE_VALUE &&
offset.type == BRW_REGISTER_TYPE_UD);
uint32_t read_offset = offset.dw1.ud;
uint32_t read_offset = offset.ud;
brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
read_offset, surf_index);
@ -1223,7 +1225,7 @@ fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
if (index.file == BRW_IMMEDIATE_VALUE) {
uint32_t surf_index = index.dw1.ud;
uint32_t surf_index = index.ud;
brw_push_insn_state(p);
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
@ -1286,7 +1288,7 @@ fs_generator::generate_varying_pull_constant_load(fs_inst *inst,
assert(index.file == BRW_IMMEDIATE_VALUE &&
index.type == BRW_REGISTER_TYPE_UD);
uint32_t surf_index = index.dw1.ud;
uint32_t surf_index = index.ud;
uint32_t simd_mode, rlen, msg_type;
if (dispatch_width == 16) {
@ -1366,7 +1368,7 @@ fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
if (index.file == BRW_IMMEDIATE_VALUE) {
uint32_t surf_index = index.dw1.ud;
uint32_t surf_index = index.ud;
brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
@ -2052,7 +2054,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
case FS_OPCODE_DDY_COARSE:
case FS_OPCODE_DDY_FINE:
assert(src[1].file == BRW_IMMEDIATE_VALUE);
generate_ddy(inst->opcode, dst, src[0], src[1].dw1.ud);
generate_ddy(inst->opcode, dst, src[0], src[1].ud);
break;
case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
@ -2120,37 +2122,37 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
case SHADER_OPCODE_UNTYPED_ATOMIC:
assert(src[2].file == BRW_IMMEDIATE_VALUE);
brw_untyped_atomic(p, dst, src[0], src[1], src[2].dw1.ud,
brw_untyped_atomic(p, dst, src[0], src[1], src[2].ud,
inst->mlen, !inst->dst.is_null());
break;
case SHADER_OPCODE_UNTYPED_SURFACE_READ:
assert(src[2].file == BRW_IMMEDIATE_VALUE);
brw_untyped_surface_read(p, dst, src[0], src[1],
inst->mlen, src[2].dw1.ud);
inst->mlen, src[2].ud);
break;
case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
assert(src[2].file == BRW_IMMEDIATE_VALUE);
brw_untyped_surface_write(p, src[0], src[1],
inst->mlen, src[2].dw1.ud);
inst->mlen, src[2].ud);
break;
case SHADER_OPCODE_TYPED_ATOMIC:
assert(src[2].file == BRW_IMMEDIATE_VALUE);
brw_typed_atomic(p, dst, src[0], src[1],
src[2].dw1.ud, inst->mlen, !inst->dst.is_null());
src[2].ud, inst->mlen, !inst->dst.is_null());
break;
case SHADER_OPCODE_TYPED_SURFACE_READ:
assert(src[2].file == BRW_IMMEDIATE_VALUE);
brw_typed_surface_read(p, dst, src[0], src[1],
inst->mlen, src[2].dw1.ud);
inst->mlen, src[2].ud);
break;
case SHADER_OPCODE_TYPED_SURFACE_WRITE:
assert(src[2].file == BRW_IMMEDIATE_VALUE);
brw_typed_surface_write(p, src[0], src[1], inst->mlen, src[2].dw1.ud);
brw_typed_surface_write(p, src[0], src[1], inst->mlen, src[2].ud);
break;
case SHADER_OPCODE_MEMORY_FENCE:

4
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
View File

@ -322,7 +322,7 @@ fs_visitor::emit_texture(ir_texture_opcode op,
inst->shadow_compare = true;
if (offset_value.file == IMM)
inst->offset = offset_value.fixed_hw_reg.dw1.ud;
inst->offset = offset_value.fixed_hw_reg.ud;
if (op == ir_tg4) {
inst->offset |=
@ -949,7 +949,7 @@ fs_visitor::emit_urb_writes(const fs_reg &gs_vertex_count)
fs_reg offset;
if (gs_vertex_count.file == IMM) {
per_slot_offsets = fs_reg(output_vertex_size_owords *
gs_vertex_count.fixed_hw_reg.dw1.ud);
gs_vertex_count.fixed_hw_reg.ud);
} else {
per_slot_offsets = vgrf(glsl_type::int_type);
bld.MUL(per_slot_offsets, gs_vertex_count,

40
src/mesa/drivers/dri/i965/brw_reg.h
View File

@ -249,12 +249,12 @@ struct brw_reg {
unsigned writemask:4; /* dest only, align16 only */
int indirect_offset:10; /* relative addressing offset */
unsigned pad1:10; /* two dwords total */
} bits;
};
float f;
int d;
unsigned ud;
} dw1;
};
};
@ -369,10 +369,10 @@ brw_reg(unsigned file,
* keep track of as you'd want it adjusted by suboffset(), etc.
* Perhaps fix up when converting to align16?
*/
reg.dw1.bits.swizzle = swizzle;
reg.dw1.bits.writemask = writemask;
reg.dw1.bits.indirect_offset = 0;
reg.dw1.bits.pad1 = 0;
reg.swizzle = swizzle;
reg.writemask = writemask;
reg.indirect_offset = 0;
reg.pad1 = 0;
return reg;
}
@ -569,7 +569,7 @@ static inline struct brw_reg
brw_imm_f(float f)
{
struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_F);
imm.dw1.f = f;
imm.f = f;
return imm;
}
@ -578,7 +578,7 @@ static inline struct brw_reg
brw_imm_d(int d)
{
struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_D);
imm.dw1.d = d;
imm.d = d;
return imm;
}
@ -587,7 +587,7 @@ static inline struct brw_reg
brw_imm_ud(unsigned ud)
{
struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UD);
imm.dw1.ud = ud;
imm.ud = ud;
return imm;
}
@ -596,7 +596,7 @@ static inline struct brw_reg
brw_imm_uw(uint16_t uw)
{
struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_UW);
imm.dw1.ud = uw | (uw << 16);
imm.ud = uw | (uw << 16);
return imm;
}
@ -605,7 +605,7 @@ static inline struct brw_reg
brw_imm_w(int16_t w)
{
struct brw_reg imm = brw_imm_reg(BRW_REGISTER_TYPE_W);
imm.dw1.d = w | (w << 16);
imm.d = w | (w << 16);
return imm;
}
@ -621,7 +621,7 @@ brw_imm_v(unsigned v)
imm.vstride = BRW_VERTICAL_STRIDE_0;
imm.width = BRW_WIDTH_8;
imm.hstride = BRW_HORIZONTAL_STRIDE_1;
imm.dw1.ud = v;
imm.ud = v;
return imm;
}
@ -633,7 +633,7 @@ brw_imm_vf(unsigned v)
imm.vstride = BRW_VERTICAL_STRIDE_0;
imm.width = BRW_WIDTH_4;
imm.hstride = BRW_HORIZONTAL_STRIDE_1;
imm.dw1.ud = v;
imm.ud = v;
return imm;
}
@ -923,8 +923,8 @@ brw_swizzle(struct brw_reg reg, unsigned x, unsigned y, unsigned z, unsigned w)
{
assert(reg.file != BRW_IMMEDIATE_VALUE);
reg.dw1.bits.swizzle = brw_compose_swizzle(BRW_SWIZZLE4(x, y, z, w),
reg.dw1.bits.swizzle);
reg.swizzle = brw_compose_swizzle(BRW_SWIZZLE4(x, y, z, w),
reg.swizzle);
return reg;
}
@ -939,7 +939,7 @@ static inline struct brw_reg
brw_writemask(struct brw_reg reg, unsigned mask)
{
assert(reg.file != BRW_IMMEDIATE_VALUE);
reg.dw1.bits.writemask &= mask;
reg.writemask &= mask;
return reg;
}
@ -947,7 +947,7 @@ static inline struct brw_reg
brw_set_writemask(struct brw_reg reg, unsigned mask)
{
assert(reg.file != BRW_IMMEDIATE_VALUE);
reg.dw1.bits.writemask = mask;
reg.writemask = mask;
return reg;
}
@ -980,7 +980,7 @@ brw_vec4_indirect(unsigned subnr, int offset)
struct brw_reg reg = brw_vec4_grf(0, 0);
reg.subnr = subnr;
reg.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
reg.dw1.bits.indirect_offset = offset;
reg.indirect_offset = offset;
return reg;
}
@ -990,7 +990,7 @@ brw_vec1_indirect(unsigned subnr, int offset)
struct brw_reg reg = brw_vec1_grf(0, 0);
reg.subnr = subnr;
reg.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
reg.dw1.bits.indirect_offset = offset;
reg.indirect_offset = offset;
return reg;
}
@ -1001,7 +1001,7 @@ brw_VxH_indirect(unsigned subnr, int offset)
reg.vstride = BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL;
reg.subnr = subnr;
reg.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
reg.dw1.bits.indirect_offset = offset;
reg.indirect_offset = offset;
return reg;
}

30
src/mesa/drivers/dri/i965/brw_shader.cpp
View File

@ -564,7 +564,7 @@ brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
unsigned ud;
int d;
float f;
} imm = { reg->dw1.ud }, sat_imm = { 0 };
} imm = { reg->ud }, sat_imm = { 0 };
switch (type) {
case BRW_REGISTER_TYPE_UD:
@ -595,7 +595,7 @@ brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
}
if (imm.ud != sat_imm.ud) {
reg->dw1.ud = sat_imm.ud;
reg->ud = sat_imm.ud;
return true;
}
return false;
@ -607,17 +607,17 @@ brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
switch (type) {
case BRW_REGISTER_TYPE_D:
case BRW_REGISTER_TYPE_UD:
reg->dw1.d = -reg->dw1.d;
reg->d = -reg->d;
return true;
case BRW_REGISTER_TYPE_W:
case BRW_REGISTER_TYPE_UW:
reg->dw1.d = -(int16_t)reg->dw1.ud;
reg->d = -(int16_t)reg->ud;
return true;
case BRW_REGISTER_TYPE_F:
reg->dw1.f = -reg->dw1.f;
reg->f = -reg->f;
return true;
case BRW_REGISTER_TYPE_VF:
reg->dw1.ud ^= 0x80808080;
reg->ud ^= 0x80808080;
return true;
case BRW_REGISTER_TYPE_UB:
case BRW_REGISTER_TYPE_B:
@ -641,16 +641,16 @@ brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
{
switch (type) {
case BRW_REGISTER_TYPE_D:
reg->dw1.d = abs(reg->dw1.d);
reg->d = abs(reg->d);
return true;
case BRW_REGISTER_TYPE_W:
reg->dw1.d = abs((int16_t)reg->dw1.ud);
reg->d = abs((int16_t)reg->ud);
return true;
case BRW_REGISTER_TYPE_F:
reg->dw1.f = fabsf(reg->dw1.f);
reg->f = fabsf(reg->f);
return true;
case BRW_REGISTER_TYPE_VF:
reg->dw1.ud &= ~0x80808080;
reg->ud &= ~0x80808080;
return true;
case BRW_REGISTER_TYPE_UB:
case BRW_REGISTER_TYPE_B:
@ -700,7 +700,7 @@ backend_reg::is_zero() const
if (file != IMM)
return false;
return fixed_hw_reg.dw1.d == 0;
return fixed_hw_reg.d == 0;
}
bool
@ -710,8 +710,8 @@ backend_reg::is_one() const
return false;
return type == BRW_REGISTER_TYPE_F
? fixed_hw_reg.dw1.f == 1.0
: fixed_hw_reg.dw1.d == 1;
? fixed_hw_reg.f == 1.0
: fixed_hw_reg.d == 1;
}
bool
@ -722,9 +722,9 @@ backend_reg::is_negative_one() const
switch (type) {
case BRW_REGISTER_TYPE_F:
return fixed_hw_reg.dw1.f == -1.0;
return fixed_hw_reg.f == -1.0;
case BRW_REGISTER_TYPE_D:
return fixed_hw_reg.dw1.d == -1;
return fixed_hw_reg.d == -1;
default:
return false;
}

40
src/mesa/drivers/dri/i965/brw_vec4.cpp
View File

@ -77,7 +77,7 @@ src_reg::src_reg(float f)
this->file = IMM;
this->type = BRW_REGISTER_TYPE_F;
this->fixed_hw_reg.dw1.f = f;
this->fixed_hw_reg.f = f;
}
src_reg::src_reg(uint32_t u)
@ -86,7 +86,7 @@ src_reg::src_reg(uint32_t u)
this->file = IMM;
this->type = BRW_REGISTER_TYPE_UD;
this->fixed_hw_reg.dw1.ud = u;
this->fixed_hw_reg.ud = u;
}
src_reg::src_reg(int32_t i)
@ -95,7 +95,7 @@ src_reg::src_reg(int32_t i)
this->file = IMM;
this->type = BRW_REGISTER_TYPE_D;
this->fixed_hw_reg.dw1.d = i;
this->fixed_hw_reg.d = i;
}
src_reg::src_reg(uint8_t vf[4])
@ -104,7 +104,7 @@ src_reg::src_reg(uint8_t vf[4])
this->file = IMM;
this->type = BRW_REGISTER_TYPE_VF;
memcpy(&this->fixed_hw_reg.dw1.ud, vf, sizeof(unsigned));
memcpy(&this->fixed_hw_reg.ud, vf, sizeof(unsigned));
}
src_reg::src_reg(uint8_t vf0, uint8_t vf1, uint8_t vf2, uint8_t vf3)
@ -113,7 +113,7 @@ src_reg::src_reg(uint8_t vf0, uint8_t vf1, uint8_t vf2, uint8_t vf3)
this->file = IMM;
this->type = BRW_REGISTER_TYPE_VF;
this->fixed_hw_reg.dw1.ud = (vf0 << 0) |
this->fixed_hw_reg.ud = (vf0 << 0) |
(vf1 << 8) |
(vf2 << 16) |
(vf3 << 24);
@ -397,7 +397,7 @@ vec4_visitor::opt_vector_float()
inst->src[0].file != IMM)
continue;
int vf = brw_float_to_vf(inst->src[0].fixed_hw_reg.dw1.f);
int vf = brw_float_to_vf(inst->src[0].fixed_hw_reg.f);
if (vf == -1)
continue;
@ -1467,20 +1467,20 @@ vec4_visitor::dump_instruction(backend_instruction *be_inst, FILE *file)
case IMM:
switch (inst->src[i].type) {
case BRW_REGISTER_TYPE_F:
fprintf(file, "%fF", inst->src[i].fixed_hw_reg.dw1.f);
fprintf(file, "%fF", inst->src[i].fixed_hw_reg.f);
break;
case BRW_REGISTER_TYPE_D:
fprintf(file, "%dD", inst->src[i].fixed_hw_reg.dw1.d);
fprintf(file, "%dD", inst->src[i].fixed_hw_reg.d);
break;
case BRW_REGISTER_TYPE_UD:
fprintf(file, "%uU", inst->src[i].fixed_hw_reg.dw1.ud);
fprintf(file, "%uU", inst->src[i].fixed_hw_reg.ud);
break;
case BRW_REGISTER_TYPE_VF:
fprintf(file, "[%-gF, %-gF, %-gF, %-gF]",
brw_vf_to_float((inst->src[i].fixed_hw_reg.dw1.ud >> 0) & 0xff),
brw_vf_to_float((inst->src[i].fixed_hw_reg.dw1.ud >> 8) & 0xff),
brw_vf_to_float((inst->src[i].fixed_hw_reg.dw1.ud >> 16) & 0xff),
brw_vf_to_float((inst->src[i].fixed_hw_reg.dw1.ud >> 24) & 0xff));
brw_vf_to_float((inst->src[i].fixed_hw_reg.ud >> 0) & 0xff),
brw_vf_to_float((inst->src[i].fixed_hw_reg.ud >> 8) & 0xff),
brw_vf_to_float((inst->src[i].fixed_hw_reg.ud >> 16) & 0xff),
brw_vf_to_float((inst->src[i].fixed_hw_reg.ud >> 24) & 0xff));
break;
default:
fprintf(file, "???");
@ -1597,7 +1597,7 @@ vec4_visitor::lower_attributes_to_hw_regs(const int *attribute_map,
struct brw_reg reg = attribute_to_hw_reg(grf, interleaved);
reg.type = inst->dst.type;
reg.dw1.bits.writemask = inst->dst.writemask;
reg.writemask = inst->dst.writemask;
inst->dst.file = HW_REG;
inst->dst.fixed_hw_reg = reg;
@ -1615,7 +1615,7 @@ vec4_visitor::lower_attributes_to_hw_regs(const int *attribute_map,
assert(grf != 0);
struct brw_reg reg = attribute_to_hw_reg(grf, interleaved);
reg.dw1.bits.swizzle = inst->src[i].swizzle;
reg.swizzle = inst->src[i].swizzle;
reg.type = inst->src[i].type;
if (inst->src[i].abs)
reg = brw_abs(reg);
@ -1810,14 +1810,14 @@ vec4_visitor::convert_to_hw_regs()
case GRF:
reg = brw_vec8_grf(src.reg + src.reg_offset, 0);
reg.type = src.type;
reg.dw1.bits.swizzle = src.swizzle;
reg.swizzle = src.swizzle;
reg.abs = src.abs;
reg.negate = src.negate;
break;
case IMM:
reg = brw_imm_reg(src.type);
reg.dw1.ud = src.fixed_hw_reg.dw1.ud;
reg.ud = src.fixed_hw_reg.ud;
break;
case UNIFORM:
@ -1826,7 +1826,7 @@ vec4_visitor::convert_to_hw_regs()
((src.reg + src.reg_offset) % 2) * 4),
0, 4, 1);
reg.type = src.type;
reg.dw1.bits.swizzle = src.swizzle;
reg.swizzle = src.swizzle;
reg.abs = src.abs;
reg.negate = src.negate;
@ -1857,14 +1857,14 @@ vec4_visitor::convert_to_hw_regs()
case GRF:
reg = brw_vec8_grf(dst.reg + dst.reg_offset, 0);
reg.type = dst.type;
reg.dw1.bits.writemask = dst.writemask;
reg.writemask = dst.writemask;
break;
case MRF:
assert(((dst.reg + dst.reg_offset) & ~(1 << 7)) < BRW_MAX_MRF(devinfo->gen));
reg = brw_message_reg(dst.reg + dst.reg_offset);
reg.type = dst.type;
reg.dw1.bits.writemask = dst.writemask;
reg.writemask = dst.writemask;
break;
case HW_REG:

6
src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp
View File

@ -147,7 +147,7 @@ try_constant_propagate(const struct brw_device_info *devinfo,
}
if (value.type == BRW_REGISTER_TYPE_VF)
value.fixed_hw_reg.dw1.ud = swizzle_vf_imm(value.fixed_hw_reg.dw1.ud,
value.fixed_hw_reg.ud = swizzle_vf_imm(value.fixed_hw_reg.ud,
inst->src[arg].swizzle);
switch (inst->opcode) {
@ -359,8 +359,8 @@ try_copy_propagate(const struct brw_device_info *devinfo,
inst->src[0].type != BRW_REGISTER_TYPE_F ||
inst->src[1].file != IMM ||
inst->src[1].type != BRW_REGISTER_TYPE_F ||
inst->src[1].fixed_hw_reg.dw1.f < 0.0 ||
inst->src[1].fixed_hw_reg.dw1.f > 1.0) {
inst->src[1].fixed_hw_reg.f < 0.0 ||
inst->src[1].fixed_hw_reg.f > 1.0) {
return false;
}
if (!inst->saturate)

41
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
View File

@ -46,7 +46,7 @@ check_gen6_math_src_arg(struct brw_reg src)
/* Source swizzles are ignored. */
assert(!src.abs);
assert(!src.negate);
assert(src.dw1.bits.swizzle == BRW_SWIZZLE_XYZW);
assert(src.swizzle == BRW_SWIZZLE_XYZW);
}
static void
@ -57,7 +57,7 @@ generate_math_gen6(struct brw_codegen *p,
struct brw_reg src1)
{
/* Can't do writemask because math can't be align16. */
assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
assert(dst.writemask == WRITEMASK_XYZW);
/* Source swizzles are ignored. */
check_gen6_math_src_arg(src0);
if (src1.file == BRW_GENERAL_REGISTER_FILE)
@ -264,7 +264,7 @@ generate_tex(struct brw_codegen *p,
: prog_data->base.binding_table.texture_start;
if (sampler_index.file == BRW_IMMEDIATE_VALUE) {
uint32_t sampler = sampler_index.dw1.ud;
uint32_t sampler = sampler_index.ud;
brw_SAMPLE(p,
dst,
@ -419,10 +419,10 @@ generate_gs_set_write_offset(struct brw_codegen *p,
assert(p->devinfo->gen >= 7 &&
src1.file == BRW_IMMEDIATE_VALUE &&
src1.type == BRW_REGISTER_TYPE_UD &&
src1.dw1.ud <= USHRT_MAX);
src1.ud <= USHRT_MAX);
if (src0.file == BRW_IMMEDIATE_VALUE) {
brw_MOV(p, suboffset(stride(dst, 2, 2, 1), 3),
brw_imm_ud(src0.dw1.ud * src1.dw1.ud));
brw_imm_ud(src0.ud * src1.ud));
} else {
brw_MUL(p, suboffset(stride(dst, 2, 2, 1), 3), stride(src0, 8, 2, 4),
retype(src1, BRW_REGISTER_TYPE_UW));
@ -740,7 +740,7 @@ generate_oword_dual_block_offsets(struct brw_codegen *p,
brw_MOV(p, m1_0, index_0);
if (index.file == BRW_IMMEDIATE_VALUE) {
index_4.dw1.ud += second_vertex_offset;
index_4.ud += second_vertex_offset;
brw_MOV(p, m1_4, index_4);
} else {
brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset));
@ -895,7 +895,7 @@ generate_pull_constant_load(struct brw_codegen *p,
const struct brw_device_info *devinfo = p->devinfo;
assert(index.file == BRW_IMMEDIATE_VALUE &&
index.type == BRW_REGISTER_TYPE_UD);
uint32_t surf_index = index.dw1.ud;
uint32_t surf_index = index.ud;
struct brw_reg header = brw_vec8_grf(0, 0);
@ -947,7 +947,7 @@ generate_get_buffer_size(struct brw_codegen *p,
dst,
inst->base_mrf,
src,
surf_index.dw1.ud,
surf_index.ud,
0,
GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO,
1, /* response length */
@ -955,6 +955,8 @@ generate_get_buffer_size(struct brw_codegen *p,
inst->header_size > 0,
BRW_SAMPLER_SIMD_MODE_SIMD4X2,
BRW_SAMPLER_RETURN_FORMAT_SINT32);
brw_mark_surface_used(&prog_data->base, surf_index.ud);
}
static void
@ -973,7 +975,7 @@ generate_pull_constant_load_gen7(struct brw_codegen *p,
brw_set_dest(p, insn, dst);
brw_set_src0(p, insn, offset);
brw_set_sampler_message(p, insn,
surf_index.dw1.ud,
surf_index.ud,
0, /* LD message ignores sampler unit */
GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1, /* rlen */
@ -981,6 +983,9 @@ generate_pull_constant_load_gen7(struct brw_codegen *p,
inst->header_size != 0,
BRW_SAMPLER_SIMD_MODE_SIMD4X2,
0);
brw_mark_surface_used(&prog_data->base, surf_index.ud);
} else {
struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
@ -1410,38 +1415,38 @@ generate_code(struct brw_codegen *p,
case SHADER_OPCODE_UNTYPED_ATOMIC:
assert(src[2].file == BRW_IMMEDIATE_VALUE);
brw_untyped_atomic(p, dst, src[0], src[1], src[2].dw1.ud, inst->mlen,
brw_untyped_atomic(p, dst, src[0], src[1], src[2].ud, inst->mlen,
!inst->dst.is_null());
break;
case SHADER_OPCODE_UNTYPED_SURFACE_READ:
assert(src[2].file == BRW_IMMEDIATE_VALUE);
brw_untyped_surface_read(p, dst, src[0], src[1], inst->mlen,
src[2].dw1.ud);
src[2].ud);
break;
case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
assert(src[2].file == BRW_IMMEDIATE_VALUE);
brw_untyped_surface_write(p, src[0], src[1], inst->mlen,
src[2].dw1.ud);
src[2].ud);
break;
case SHADER_OPCODE_TYPED_ATOMIC:
assert(src[2].file == BRW_IMMEDIATE_VALUE);
brw_typed_atomic(p, dst, src[0], src[1], src[2].dw1.ud, inst->mlen,
brw_typed_atomic(p, dst, src[0], src[1], src[2].ud, inst->mlen,
!inst->dst.is_null());
break;
case SHADER_OPCODE_TYPED_SURFACE_READ:
assert(src[2].file == BRW_IMMEDIATE_VALUE);
brw_typed_surface_read(p, dst, src[0], src[1], inst->mlen,
src[2].dw1.ud);
src[2].ud);
break;
case SHADER_OPCODE_TYPED_SURFACE_WRITE:
assert(src[2].file == BRW_IMMEDIATE_VALUE);
brw_typed_surface_write(p, src[0], src[1], inst->mlen,
src[2].dw1.ud);
src[2].ud);
break;
case SHADER_OPCODE_MEMORY_FENCE:
@ -1489,9 +1494,9 @@ generate_code(struct brw_codegen *p,
*
* where they pack the four bytes from the low and high four DW.
*/
assert(_mesa_is_pow_two(dst.dw1.bits.writemask) &&
dst.dw1.bits.writemask != 0);
unsigned offset = __builtin_ctz(dst.dw1.bits.writemask);
assert(_mesa_is_pow_two(dst.writemask) &&
dst.writemask != 0);
unsigned offset = __builtin_ctz(dst.writemask);
dst.type = BRW_REGISTER_TYPE_UB;

2
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
View File

@ -863,7 +863,7 @@ vec4_visitor::is_high_sampler(src_reg sampler)
if (devinfo->gen < 8 && !devinfo->is_haswell)
return false;
return sampler.file != IMM || sampler.fixed_hw_reg.dw1.ud >= 16;
return sampler.file != IMM || sampler.fixed_hw_reg.ud >= 16;
}
void