2011-05-26 17:57:36 +01:00
|
|
|
/*
|
|
|
|
* Copyright © 2010 Intel Corporation
|
|
|
|
*
|
|
|
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
|
|
|
* copy of this software and associated documentation files (the "Software"),
|
|
|
|
* to deal in the Software without restriction, including without limitation
|
|
|
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
|
|
|
* and/or sell copies of the Software, and to permit persons to whom the
|
|
|
|
* Software is furnished to do so, subject to the following conditions:
|
|
|
|
*
|
|
|
|
* The above copyright notice and this permission notice (including the next
|
|
|
|
* paragraph) shall be included in all copies or substantial portions of the
|
|
|
|
* Software.
|
|
|
|
*
|
|
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
|
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
|
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
|
|
|
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
|
|
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
|
|
|
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
|
|
|
|
* IN THE SOFTWARE.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include "main/macros.h"
|
|
|
|
#include "brw_context.h"
|
2013-03-20 18:35:34 +00:00
|
|
|
#include "brw_vs.h"
|
2014-10-29 00:27:39 +00:00
|
|
|
#include "brw_gs.h"
|
2011-05-26 17:57:36 +01:00
|
|
|
#include "brw_fs.h"
|
2014-05-19 18:20:37 +01:00
|
|
|
#include "brw_cfg.h"
|
2015-04-07 23:15:09 +01:00
|
|
|
#include "brw_nir.h"
|
2011-08-26 21:58:41 +01:00
|
|
|
#include "glsl/ir_optimization.h"
|
2013-06-13 00:57:11 +01:00
|
|
|
#include "glsl/glsl_parser_extras.h"
|
2013-03-23 17:51:53 +00:00
|
|
|
#include "main/shaderapi.h"
|
2011-05-26 17:57:36 +01:00
|
|
|
|
2015-04-16 20:01:09 +01:00
|
|
|
struct brw_compiler *
|
|
|
|
brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo)
|
|
|
|
{
|
|
|
|
struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
|
|
|
|
|
|
|
|
compiler->devinfo = devinfo;
|
|
|
|
|
|
|
|
brw_fs_alloc_reg_sets(compiler);
|
|
|
|
brw_vec4_alloc_reg_set(compiler);
|
|
|
|
|
|
|
|
return compiler;
|
|
|
|
}
|
|
|
|
|
2011-05-26 17:57:36 +01:00
|
|
|
struct gl_shader *
|
|
|
|
brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
|
|
|
|
{
|
|
|
|
struct brw_shader *shader;
|
|
|
|
|
|
|
|
shader = rzalloc(NULL, struct brw_shader);
|
|
|
|
if (shader) {
|
|
|
|
shader->base.Type = type;
|
2014-01-07 18:58:56 +00:00
|
|
|
shader->base.Stage = _mesa_shader_enum_to_shader_stage(type);
|
2011-05-26 17:57:36 +01:00
|
|
|
shader->base.Name = name;
|
|
|
|
_mesa_init_shader(ctx, &shader->base);
|
|
|
|
}
|
|
|
|
|
|
|
|
return &shader->base;
|
|
|
|
}
|
|
|
|
|
2011-05-16 23:10:26 +01:00
|
|
|
/**
|
|
|
|
* Performs a compile of the shader stages even when we don't know
|
|
|
|
* what non-orthogonal state will be set, in the hope that it reflects
|
|
|
|
* the eventual NOS used, and thus allows us to produce link failures.
|
|
|
|
*/
|
2012-09-21 09:36:22 +01:00
|
|
|
static bool
|
2014-11-24 07:26:00 +00:00
|
|
|
brw_shader_precompile(struct gl_context *ctx,
|
|
|
|
struct gl_shader_program *sh_prog)
|
2011-05-16 23:10:26 +01:00
|
|
|
{
|
2014-11-24 07:26:00 +00:00
|
|
|
struct gl_shader *vs = sh_prog->_LinkedShaders[MESA_SHADER_VERTEX];
|
|
|
|
struct gl_shader *gs = sh_prog->_LinkedShaders[MESA_SHADER_GEOMETRY];
|
|
|
|
struct gl_shader *fs = sh_prog->_LinkedShaders[MESA_SHADER_FRAGMENT];
|
2015-03-14 19:55:54 +00:00
|
|
|
struct gl_shader *cs = sh_prog->_LinkedShaders[MESA_SHADER_COMPUTE];
|
2011-11-23 18:01:39 +00:00
|
|
|
|
2014-11-24 07:26:00 +00:00
|
|
|
if (fs && !brw_fs_precompile(ctx, sh_prog, fs->Program))
|
2011-05-16 23:10:26 +01:00
|
|
|
return false;
|
|
|
|
|
2014-11-24 07:26:00 +00:00
|
|
|
if (gs && !brw_gs_precompile(ctx, sh_prog, gs->Program))
|
2013-10-23 18:19:39 +01:00
|
|
|
return false;
|
|
|
|
|
2014-11-24 07:26:00 +00:00
|
|
|
if (vs && !brw_vs_precompile(ctx, sh_prog, vs->Program))
|
2011-08-11 17:52:08 +01:00
|
|
|
return false;
|
|
|
|
|
2015-03-14 19:55:54 +00:00
|
|
|
if (cs && !brw_cs_precompile(ctx, sh_prog, cs->Program))
|
|
|
|
return false;
|
|
|
|
|
2011-05-16 23:10:26 +01:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2014-10-21 07:29:41 +01:00
|
|
|
static inline bool
|
|
|
|
is_scalar_shader_stage(struct brw_context *brw, int stage)
|
|
|
|
{
|
|
|
|
switch (stage) {
|
|
|
|
case MESA_SHADER_FRAGMENT:
|
|
|
|
return true;
|
|
|
|
case MESA_SHADER_VERTEX:
|
|
|
|
return brw->scalar_vs;
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-12-01 00:49:21 +00:00
|
|
|
static void
|
|
|
|
brw_lower_packing_builtins(struct brw_context *brw,
|
2014-01-07 18:11:39 +00:00
|
|
|
gl_shader_stage shader_type,
|
2012-12-01 00:49:21 +00:00
|
|
|
exec_list *ir)
|
|
|
|
{
|
|
|
|
int ops = LOWER_PACK_SNORM_2x16
|
|
|
|
| LOWER_UNPACK_SNORM_2x16
|
|
|
|
| LOWER_PACK_UNORM_2x16
|
2014-03-10 21:11:05 +00:00
|
|
|
| LOWER_UNPACK_UNORM_2x16;
|
2014-03-09 01:29:33 +00:00
|
|
|
|
2014-10-21 07:29:41 +01:00
|
|
|
if (is_scalar_shader_stage(brw, shader_type)) {
|
2014-03-10 03:22:23 +00:00
|
|
|
ops |= LOWER_UNPACK_UNORM_4x8
|
2014-03-10 20:27:46 +00:00
|
|
|
| LOWER_UNPACK_SNORM_4x8
|
2014-03-10 21:11:05 +00:00
|
|
|
| LOWER_PACK_UNORM_4x8
|
|
|
|
| LOWER_PACK_SNORM_4x8;
|
2014-03-09 01:29:33 +00:00
|
|
|
}
|
2012-12-01 00:49:21 +00:00
|
|
|
|
2013-07-06 08:36:46 +01:00
|
|
|
if (brw->gen >= 7) {
|
2012-12-01 00:49:21 +00:00
|
|
|
/* Gen7 introduced the f32to16 and f16to32 instructions, which can be
|
|
|
|
* used to execute packHalf2x16 and unpackHalf2x16. For AOS code, no
|
|
|
|
* lowering is needed. For SOA code, the Half2x16 ops must be
|
|
|
|
* scalarized.
|
|
|
|
*/
|
2014-10-21 07:29:41 +01:00
|
|
|
if (is_scalar_shader_stage(brw, shader_type)) {
|
2012-12-01 00:49:21 +00:00
|
|
|
ops |= LOWER_PACK_HALF_2x16_TO_SPLIT
|
|
|
|
| LOWER_UNPACK_HALF_2x16_TO_SPLIT;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
ops |= LOWER_PACK_HALF_2x16
|
|
|
|
| LOWER_UNPACK_HALF_2x16;
|
|
|
|
}
|
|
|
|
|
|
|
|
lower_packing_builtins(ir, ops);
|
|
|
|
}
|
|
|
|
|
2015-04-08 00:28:10 +01:00
|
|
|
static void
|
|
|
|
process_glsl_ir(struct brw_context *brw,
|
|
|
|
struct gl_shader_program *shader_prog,
|
|
|
|
struct gl_shader *shader)
|
|
|
|
{
|
|
|
|
struct gl_context *ctx = &brw->ctx;
|
|
|
|
const struct gl_shader_compiler_options *options =
|
|
|
|
&ctx->Const.ShaderCompilerOptions[shader->Stage];
|
|
|
|
|
|
|
|
/* Temporary memory context for any new IR. */
|
|
|
|
void *mem_ctx = ralloc_context(NULL);
|
|
|
|
|
|
|
|
ralloc_adopt(mem_ctx, shader->ir);
|
|
|
|
|
|
|
|
/* lower_packing_builtins() inserts arithmetic instructions, so it
|
|
|
|
* must precede lower_instructions().
|
|
|
|
*/
|
|
|
|
brw_lower_packing_builtins(brw, shader->Stage, shader->ir);
|
|
|
|
do_mat_op_to_vec(shader->ir);
|
|
|
|
const int bitfield_insert = brw->gen >= 7 ? BITFIELD_INSERT_TO_BFM_BFI : 0;
|
|
|
|
lower_instructions(shader->ir,
|
|
|
|
MOD_TO_FLOOR |
|
|
|
|
DIV_TO_MUL_RCP |
|
|
|
|
SUB_TO_ADD_NEG |
|
|
|
|
EXP_TO_EXP2 |
|
|
|
|
LOG_TO_LOG2 |
|
|
|
|
bitfield_insert |
|
|
|
|
LDEXP_TO_ARITH);
|
|
|
|
|
|
|
|
/* Pre-gen6 HW can only nest if-statements 16 deep. Beyond this,
|
|
|
|
* if-statements need to be flattened.
|
|
|
|
*/
|
|
|
|
if (brw->gen < 6)
|
|
|
|
lower_if_to_cond_assign(shader->ir, 16);
|
|
|
|
|
|
|
|
do_lower_texture_projection(shader->ir);
|
|
|
|
brw_lower_texture_gradients(brw, shader->ir);
|
|
|
|
do_vec_index_to_cond_assign(shader->ir);
|
|
|
|
lower_vector_insert(shader->ir, true);
|
|
|
|
if (options->NirOptions == NULL)
|
|
|
|
brw_do_cubemap_normalize(shader->ir);
|
|
|
|
lower_offset_arrays(shader->ir);
|
|
|
|
brw_do_lower_unnormalized_offset(shader->ir);
|
|
|
|
lower_noise(shader->ir);
|
|
|
|
lower_quadop_vector(shader->ir, false);
|
|
|
|
|
|
|
|
bool lowered_variable_indexing =
|
|
|
|
lower_variable_index_to_cond_assign(shader->ir,
|
|
|
|
options->EmitNoIndirectInput,
|
|
|
|
options->EmitNoIndirectOutput,
|
|
|
|
options->EmitNoIndirectTemp,
|
|
|
|
options->EmitNoIndirectUniform);
|
|
|
|
|
|
|
|
if (unlikely(brw->perf_debug && lowered_variable_indexing)) {
|
|
|
|
perf_debug("Unsupported form of variable indexing in FS; falling "
|
|
|
|
"back to very inefficient code generation\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
lower_ubo_reference(shader, shader->ir);
|
|
|
|
|
|
|
|
bool progress;
|
|
|
|
do {
|
|
|
|
progress = false;
|
|
|
|
|
|
|
|
if (is_scalar_shader_stage(brw, shader->Stage)) {
|
|
|
|
brw_do_channel_expressions(shader->ir);
|
|
|
|
brw_do_vector_splitting(shader->ir);
|
|
|
|
}
|
|
|
|
|
|
|
|
progress = do_lower_jumps(shader->ir, true, true,
|
|
|
|
true, /* main return */
|
|
|
|
false, /* continue */
|
|
|
|
false /* loops */
|
|
|
|
) || progress;
|
|
|
|
|
|
|
|
progress = do_common_optimization(shader->ir, true, true,
|
|
|
|
options, ctx->Const.NativeIntegers) || progress;
|
|
|
|
} while (progress);
|
|
|
|
|
2015-04-07 23:05:12 +01:00
|
|
|
if (options->NirOptions != NULL)
|
|
|
|
lower_output_reads(shader->ir);
|
|
|
|
|
2015-04-08 00:28:10 +01:00
|
|
|
validate_ir_tree(shader->ir);
|
|
|
|
|
|
|
|
/* Now that we've finished altering the linked IR, reparent any live IR back
|
|
|
|
* to the permanent memory context, and free the temporary one (discarding any
|
|
|
|
* junk we optimized away).
|
|
|
|
*/
|
|
|
|
reparent_ir(shader->ir, shader->ir);
|
|
|
|
ralloc_free(mem_ctx);
|
|
|
|
|
|
|
|
if (ctx->_Shader->Flags & GLSL_DUMP) {
|
|
|
|
fprintf(stderr, "\n");
|
|
|
|
fprintf(stderr, "GLSL IR for linked %s program %d:\n",
|
|
|
|
_mesa_shader_stage_to_string(shader->Stage),
|
|
|
|
shader_prog->Name);
|
|
|
|
_mesa_print_ir(stderr, shader->ir, NULL);
|
|
|
|
fprintf(stderr, "\n");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-05-26 17:57:36 +01:00
|
|
|
GLboolean
|
2012-01-07 00:26:49 +00:00
|
|
|
brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
|
2011-05-26 17:57:36 +01:00
|
|
|
{
|
|
|
|
struct brw_context *brw = brw_context(ctx);
|
2011-05-03 23:27:38 +01:00
|
|
|
unsigned int stage;
|
|
|
|
|
2012-01-07 00:26:49 +00:00
|
|
|
for (stage = 0; stage < ARRAY_SIZE(shProg->_LinkedShaders); stage++) {
|
2015-04-08 00:29:32 +01:00
|
|
|
struct gl_shader *shader = shProg->_LinkedShaders[stage];
|
2015-04-07 23:15:09 +01:00
|
|
|
const struct gl_shader_compiler_options *options =
|
|
|
|
&ctx->Const.ShaderCompilerOptions[stage];
|
2011-05-03 23:27:38 +01:00
|
|
|
|
|
|
|
if (!shader)
|
|
|
|
continue;
|
2011-05-26 17:57:36 +01:00
|
|
|
|
2012-01-07 00:26:49 +00:00
|
|
|
struct gl_program *prog =
|
2014-01-09 21:42:05 +00:00
|
|
|
ctx->Driver.NewProgram(ctx, _mesa_shader_stage_to_program(stage),
|
2015-04-08 00:29:32 +01:00
|
|
|
shader->Name);
|
2012-01-07 00:26:49 +00:00
|
|
|
if (!prog)
|
2012-08-21 19:39:49 +01:00
|
|
|
return false;
|
2012-01-07 00:26:49 +00:00
|
|
|
prog->Parameters = _mesa_new_parameter_list();
|
|
|
|
|
2014-01-07 18:11:39 +00:00
|
|
|
_mesa_copy_linked_program_data((gl_shader_stage) stage, shProg, prog);
|
2012-01-07 00:26:49 +00:00
|
|
|
|
2015-04-08 00:28:10 +01:00
|
|
|
process_glsl_ir(brw, shProg, shader);
|
2011-05-26 17:57:36 +01:00
|
|
|
|
2012-01-07 00:26:49 +00:00
|
|
|
/* Make a pass over the IR to add state references for any built-in
|
|
|
|
* uniforms that are used. This has to be done now (during linking).
|
|
|
|
* Code generation doesn't happen until the first time this shader is
|
|
|
|
* used for rendering. Waiting until then to generate the parameters is
|
2012-11-21 21:57:58 +00:00
|
|
|
* too late. At that point, the values for the built-in uniforms won't
|
2012-01-07 00:26:49 +00:00
|
|
|
* get sent to the shader.
|
|
|
|
*/
|
2015-04-08 00:29:32 +01:00
|
|
|
foreach_in_list(ir_instruction, node, shader->ir) {
|
2014-06-24 23:53:19 +01:00
|
|
|
ir_variable *var = node->as_variable();
|
2012-01-07 00:26:49 +00:00
|
|
|
|
2013-12-12 11:51:01 +00:00
|
|
|
if ((var == NULL) || (var->data.mode != ir_var_uniform)
|
2012-01-07 00:26:49 +00:00
|
|
|
|| (strncmp(var->name, "gl_", 3) != 0))
|
|
|
|
continue;
|
|
|
|
|
2014-05-15 03:47:28 +01:00
|
|
|
const ir_state_slot *const slots = var->get_state_slots();
|
|
|
|
assert(slots != NULL);
|
2012-01-07 00:26:49 +00:00
|
|
|
|
2014-05-15 03:47:28 +01:00
|
|
|
for (unsigned int i = 0; i < var->get_num_state_slots(); i++) {
|
2012-01-07 00:26:49 +00:00
|
|
|
_mesa_add_state_reference(prog->Parameters,
|
|
|
|
(gl_state_index *) slots[i].tokens);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-04-08 00:29:32 +01:00
|
|
|
do_set_program_inouts(shader->ir, prog, shader->Stage);
|
2012-01-07 00:26:49 +00:00
|
|
|
|
2015-04-08 00:29:32 +01:00
|
|
|
prog->SamplersUsed = shader->active_samplers;
|
|
|
|
prog->ShadowSamplers = shader->shadow_samplers;
|
2012-01-07 00:26:49 +00:00
|
|
|
_mesa_update_shader_textures_used(shProg, prog);
|
|
|
|
|
2015-04-08 00:29:32 +01:00
|
|
|
_mesa_reference_program(ctx, &shader->Program, prog);
|
2012-01-07 00:26:49 +00:00
|
|
|
|
2012-11-21 21:23:36 +00:00
|
|
|
brw_add_texrect_params(prog);
|
|
|
|
|
2015-04-07 23:15:09 +01:00
|
|
|
if (options->NirOptions)
|
|
|
|
prog->nir = brw_create_nir(brw, shProg, prog, (gl_shader_stage) stage);
|
|
|
|
|
2012-01-12 20:55:06 +00:00
|
|
|
_mesa_reference_program(ctx, &prog, NULL);
|
2013-03-22 23:50:58 +00:00
|
|
|
}
|
|
|
|
|
2013-05-03 18:44:10 +01:00
|
|
|
if ((ctx->_Shader->Flags & GLSL_DUMP) && shProg->Name != 0) {
|
2013-03-22 23:50:58 +00:00
|
|
|
for (unsigned i = 0; i < shProg->NumShaders; i++) {
|
|
|
|
const struct gl_shader *sh = shProg->Shaders[i];
|
|
|
|
if (!sh)
|
|
|
|
continue;
|
|
|
|
|
2013-12-23 07:29:31 +00:00
|
|
|
fprintf(stderr, "GLSL %s shader %d source for linked program %d:\n",
|
|
|
|
_mesa_shader_stage_to_string(sh->Stage),
|
|
|
|
i, shProg->Name);
|
|
|
|
fprintf(stderr, "%s", sh->Source);
|
|
|
|
fprintf(stderr, "\n");
|
2012-09-19 21:27:58 +01:00
|
|
|
}
|
2011-05-26 17:57:36 +01:00
|
|
|
}
|
|
|
|
|
2014-11-24 07:08:10 +00:00
|
|
|
if (brw->precompile && !brw_shader_precompile(ctx, shProg))
|
2011-10-07 20:26:50 +01:00
|
|
|
return false;
|
2011-05-16 23:10:26 +01:00
|
|
|
|
2011-10-07 20:26:50 +01:00
|
|
|
return true;
|
2011-05-26 17:57:36 +01:00
|
|
|
}
|
2011-05-26 18:01:10 +01:00
|
|
|
|
|
|
|
|
2014-06-30 00:02:59 +01:00
|
|
|
enum brw_reg_type
|
2011-05-26 18:01:10 +01:00
|
|
|
brw_type_for_base_type(const struct glsl_type *type)
|
|
|
|
{
|
|
|
|
switch (type->base_type) {
|
|
|
|
case GLSL_TYPE_FLOAT:
|
|
|
|
return BRW_REGISTER_TYPE_F;
|
|
|
|
case GLSL_TYPE_INT:
|
2014-10-16 20:16:08 +01:00
|
|
|
case GLSL_TYPE_BOOL:
|
2014-12-02 20:30:27 +00:00
|
|
|
return BRW_REGISTER_TYPE_D;
|
2011-05-26 18:01:10 +01:00
|
|
|
case GLSL_TYPE_UINT:
|
|
|
|
return BRW_REGISTER_TYPE_UD;
|
|
|
|
case GLSL_TYPE_ARRAY:
|
2011-11-09 03:26:38 +00:00
|
|
|
return brw_type_for_base_type(type->fields.array);
|
2011-05-26 18:01:10 +01:00
|
|
|
case GLSL_TYPE_STRUCT:
|
|
|
|
case GLSL_TYPE_SAMPLER:
|
2013-10-20 20:35:47 +01:00
|
|
|
case GLSL_TYPE_ATOMIC_UINT:
|
2011-05-26 18:01:10 +01:00
|
|
|
/* These should be overridden with the type of the member when
|
|
|
|
* dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
|
|
|
|
* way to trip up if we don't.
|
|
|
|
*/
|
|
|
|
return BRW_REGISTER_TYPE_UD;
|
2013-11-25 21:50:47 +00:00
|
|
|
case GLSL_TYPE_IMAGE:
|
|
|
|
return BRW_REGISTER_TYPE_UD;
|
2012-12-11 20:56:03 +00:00
|
|
|
case GLSL_TYPE_VOID:
|
|
|
|
case GLSL_TYPE_ERROR:
|
2012-12-11 20:11:16 +00:00
|
|
|
case GLSL_TYPE_INTERFACE:
|
2014-08-14 09:49:20 +01:00
|
|
|
case GLSL_TYPE_DOUBLE:
|
2014-06-29 22:54:01 +01:00
|
|
|
unreachable("not reached");
|
2011-05-26 18:01:10 +01:00
|
|
|
}
|
2012-12-11 20:56:03 +00:00
|
|
|
|
|
|
|
return BRW_REGISTER_TYPE_F;
|
2011-05-26 18:01:10 +01:00
|
|
|
}
|
|
|
|
|
2014-06-30 01:50:20 +01:00
|
|
|
enum brw_conditional_mod
|
2011-05-26 18:01:10 +01:00
|
|
|
brw_conditional_for_comparison(unsigned int op)
|
|
|
|
{
|
|
|
|
switch (op) {
|
|
|
|
case ir_binop_less:
|
|
|
|
return BRW_CONDITIONAL_L;
|
|
|
|
case ir_binop_greater:
|
|
|
|
return BRW_CONDITIONAL_G;
|
|
|
|
case ir_binop_lequal:
|
|
|
|
return BRW_CONDITIONAL_LE;
|
|
|
|
case ir_binop_gequal:
|
|
|
|
return BRW_CONDITIONAL_GE;
|
|
|
|
case ir_binop_equal:
|
|
|
|
case ir_binop_all_equal: /* same as equal for scalars */
|
|
|
|
return BRW_CONDITIONAL_Z;
|
|
|
|
case ir_binop_nequal:
|
|
|
|
case ir_binop_any_nequal: /* same as nequal for scalars */
|
|
|
|
return BRW_CONDITIONAL_NZ;
|
|
|
|
default:
|
2014-06-29 22:54:01 +01:00
|
|
|
unreachable("not reached: bad operation for comparison");
|
2011-05-26 18:01:10 +01:00
|
|
|
}
|
|
|
|
}
|
2011-05-02 17:45:40 +01:00
|
|
|
|
|
|
|
uint32_t
|
|
|
|
brw_math_function(enum opcode op)
|
|
|
|
{
|
|
|
|
switch (op) {
|
|
|
|
case SHADER_OPCODE_RCP:
|
|
|
|
return BRW_MATH_FUNCTION_INV;
|
|
|
|
case SHADER_OPCODE_RSQ:
|
|
|
|
return BRW_MATH_FUNCTION_RSQ;
|
|
|
|
case SHADER_OPCODE_SQRT:
|
|
|
|
return BRW_MATH_FUNCTION_SQRT;
|
|
|
|
case SHADER_OPCODE_EXP2:
|
|
|
|
return BRW_MATH_FUNCTION_EXP;
|
|
|
|
case SHADER_OPCODE_LOG2:
|
|
|
|
return BRW_MATH_FUNCTION_LOG;
|
|
|
|
case SHADER_OPCODE_POW:
|
|
|
|
return BRW_MATH_FUNCTION_POW;
|
|
|
|
case SHADER_OPCODE_SIN:
|
|
|
|
return BRW_MATH_FUNCTION_SIN;
|
|
|
|
case SHADER_OPCODE_COS:
|
|
|
|
return BRW_MATH_FUNCTION_COS;
|
2011-09-29 01:37:54 +01:00
|
|
|
case SHADER_OPCODE_INT_QUOTIENT:
|
|
|
|
return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
|
|
|
|
case SHADER_OPCODE_INT_REMAINDER:
|
|
|
|
return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
|
2011-05-02 17:45:40 +01:00
|
|
|
default:
|
2014-06-29 22:54:01 +01:00
|
|
|
unreachable("not reached: unknown math function");
|
2011-05-02 17:45:40 +01:00
|
|
|
}
|
|
|
|
}
|
2011-10-26 21:51:28 +01:00
|
|
|
|
|
|
|
uint32_t
|
2015-04-14 22:23:40 +01:00
|
|
|
brw_texture_offset(int *offsets, unsigned num_components)
|
2011-10-26 21:51:28 +01:00
|
|
|
{
|
2014-08-04 23:20:38 +01:00
|
|
|
if (!offsets) return 0; /* nonconstant offset; caller will handle it. */
|
2011-10-26 21:51:28 +01:00
|
|
|
|
|
|
|
/* Combine all three offsets into a single unsigned dword:
|
|
|
|
*
|
|
|
|
* bits 11:8 - U Offset (X component)
|
|
|
|
* bits 7:4 - V Offset (Y component)
|
|
|
|
* bits 3:0 - R Offset (Z component)
|
|
|
|
*/
|
|
|
|
unsigned offset_bits = 0;
|
2014-08-04 23:20:38 +01:00
|
|
|
for (unsigned i = 0; i < num_components; i++) {
|
2011-10-26 21:51:28 +01:00
|
|
|
const unsigned shift = 4 * (2 - i);
|
|
|
|
offset_bits |= (offsets[i] << shift) & (0xF << shift);
|
|
|
|
}
|
|
|
|
return offset_bits;
|
|
|
|
}
|
2013-03-12 00:36:54 +00:00
|
|
|
|
|
|
|
const char *
|
|
|
|
brw_instruction_name(enum opcode op)
|
|
|
|
{
|
|
|
|
switch (op) {
|
2014-12-06 22:18:21 +00:00
|
|
|
case BRW_OPCODE_MOV ... BRW_OPCODE_NOP:
|
|
|
|
assert(opcode_descs[op].name);
|
|
|
|
return opcode_descs[op].name;
|
2013-03-12 00:36:54 +00:00
|
|
|
case FS_OPCODE_FB_WRITE:
|
|
|
|
return "fb_write";
|
2013-12-17 12:00:50 +00:00
|
|
|
case FS_OPCODE_BLORP_FB_WRITE:
|
|
|
|
return "blorp_fb_write";
|
2014-12-06 22:16:13 +00:00
|
|
|
case FS_OPCODE_REP_FB_WRITE:
|
|
|
|
return "rep_fb_write";
|
2013-03-12 00:36:54 +00:00
|
|
|
|
|
|
|
case SHADER_OPCODE_RCP:
|
|
|
|
return "rcp";
|
|
|
|
case SHADER_OPCODE_RSQ:
|
|
|
|
return "rsq";
|
|
|
|
case SHADER_OPCODE_SQRT:
|
|
|
|
return "sqrt";
|
|
|
|
case SHADER_OPCODE_EXP2:
|
|
|
|
return "exp2";
|
|
|
|
case SHADER_OPCODE_LOG2:
|
|
|
|
return "log2";
|
|
|
|
case SHADER_OPCODE_POW:
|
|
|
|
return "pow";
|
|
|
|
case SHADER_OPCODE_INT_QUOTIENT:
|
|
|
|
return "int_quot";
|
|
|
|
case SHADER_OPCODE_INT_REMAINDER:
|
|
|
|
return "int_rem";
|
|
|
|
case SHADER_OPCODE_SIN:
|
|
|
|
return "sin";
|
|
|
|
case SHADER_OPCODE_COS:
|
|
|
|
return "cos";
|
|
|
|
|
|
|
|
case SHADER_OPCODE_TEX:
|
|
|
|
return "tex";
|
|
|
|
case SHADER_OPCODE_TXD:
|
|
|
|
return "txd";
|
|
|
|
case SHADER_OPCODE_TXF:
|
|
|
|
return "txf";
|
|
|
|
case SHADER_OPCODE_TXL:
|
|
|
|
return "txl";
|
|
|
|
case SHADER_OPCODE_TXS:
|
|
|
|
return "txs";
|
|
|
|
case FS_OPCODE_TXB:
|
|
|
|
return "txb";
|
2013-12-10 14:36:31 +00:00
|
|
|
case SHADER_OPCODE_TXF_CMS:
|
|
|
|
return "txf_cms";
|
2013-12-10 14:38:15 +00:00
|
|
|
case SHADER_OPCODE_TXF_UMS:
|
|
|
|
return "txf_ums";
|
2013-11-29 21:32:16 +00:00
|
|
|
case SHADER_OPCODE_TXF_MCS:
|
|
|
|
return "txf_mcs";
|
2014-12-06 22:16:13 +00:00
|
|
|
case SHADER_OPCODE_LOD:
|
|
|
|
return "lod";
|
2013-10-08 09:34:22 +01:00
|
|
|
case SHADER_OPCODE_TG4:
|
|
|
|
return "tg4";
|
2013-10-08 09:42:10 +01:00
|
|
|
case SHADER_OPCODE_TG4_OFFSET:
|
|
|
|
return "tg4_offset";
|
2014-06-14 11:13:27 +01:00
|
|
|
case SHADER_OPCODE_SHADER_TIME_ADD:
|
|
|
|
return "shader_time_add";
|
2013-03-12 00:36:54 +00:00
|
|
|
|
2014-12-06 22:16:13 +00:00
|
|
|
case SHADER_OPCODE_UNTYPED_ATOMIC:
|
|
|
|
return "untyped_atomic";
|
|
|
|
case SHADER_OPCODE_UNTYPED_SURFACE_READ:
|
|
|
|
return "untyped_surface_read";
|
2015-04-23 12:24:14 +01:00
|
|
|
case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
|
|
|
|
return "untyped_surface_write";
|
2015-04-23 12:28:25 +01:00
|
|
|
case SHADER_OPCODE_TYPED_ATOMIC:
|
|
|
|
return "typed_atomic";
|
|
|
|
case SHADER_OPCODE_TYPED_SURFACE_READ:
|
|
|
|
return "typed_surface_read";
|
|
|
|
case SHADER_OPCODE_TYPED_SURFACE_WRITE:
|
|
|
|
return "typed_surface_write";
|
2015-04-23 12:30:28 +01:00
|
|
|
case SHADER_OPCODE_MEMORY_FENCE:
|
|
|
|
return "memory_fence";
|
2014-12-06 22:16:13 +00:00
|
|
|
|
2014-05-28 02:47:40 +01:00
|
|
|
case SHADER_OPCODE_LOAD_PAYLOAD:
|
|
|
|
return "load_payload";
|
|
|
|
|
2013-10-16 19:45:06 +01:00
|
|
|
case SHADER_OPCODE_GEN4_SCRATCH_READ:
|
|
|
|
return "gen4_scratch_read";
|
|
|
|
case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
|
|
|
|
return "gen4_scratch_write";
|
2013-10-16 19:51:22 +01:00
|
|
|
case SHADER_OPCODE_GEN7_SCRATCH_READ:
|
|
|
|
return "gen7_scratch_read";
|
2014-10-21 07:00:50 +01:00
|
|
|
case SHADER_OPCODE_URB_WRITE_SIMD8:
|
|
|
|
return "gen8_urb_write_simd8";
|
2013-10-16 19:45:06 +01:00
|
|
|
|
2015-02-20 18:14:24 +00:00
|
|
|
case SHADER_OPCODE_BROADCAST:
|
|
|
|
return "broadcast";
|
|
|
|
|
2015-02-12 01:42:43 +00:00
|
|
|
case VEC4_OPCODE_MOV_BYTES:
|
|
|
|
return "mov_bytes";
|
2014-03-10 20:26:30 +00:00
|
|
|
case VEC4_OPCODE_PACK_BYTES:
|
|
|
|
return "pack_bytes";
|
2014-10-24 07:22:09 +01:00
|
|
|
case VEC4_OPCODE_UNPACK_UNIFORM:
|
|
|
|
return "unpack_uniform";
|
2014-03-10 20:26:30 +00:00
|
|
|
|
2014-11-08 09:39:14 +00:00
|
|
|
case FS_OPCODE_DDX_COARSE:
|
|
|
|
return "ddx_coarse";
|
|
|
|
case FS_OPCODE_DDX_FINE:
|
|
|
|
return "ddx_fine";
|
|
|
|
case FS_OPCODE_DDY_COARSE:
|
|
|
|
return "ddy_coarse";
|
|
|
|
case FS_OPCODE_DDY_FINE:
|
|
|
|
return "ddy_fine";
|
2013-03-12 00:36:54 +00:00
|
|
|
|
|
|
|
case FS_OPCODE_CINTERP:
|
|
|
|
return "cinterp";
|
|
|
|
case FS_OPCODE_LINTERP:
|
|
|
|
return "linterp";
|
|
|
|
|
2015-04-25 00:23:46 +01:00
|
|
|
case FS_OPCODE_PIXEL_X:
|
|
|
|
return "pixel_x";
|
|
|
|
case FS_OPCODE_PIXEL_Y:
|
|
|
|
return "pixel_y";
|
|
|
|
|
2013-03-12 00:36:54 +00:00
|
|
|
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
|
|
|
|
return "uniform_pull_const";
|
|
|
|
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
|
|
|
|
return "uniform_pull_const_gen7";
|
|
|
|
case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
|
|
|
|
return "varying_pull_const";
|
|
|
|
case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
|
|
|
|
return "varying_pull_const_gen7";
|
|
|
|
|
|
|
|
case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
|
|
|
|
return "mov_dispatch_to_flags";
|
|
|
|
case FS_OPCODE_DISCARD_JUMP:
|
|
|
|
return "discard_jump";
|
|
|
|
|
2014-12-06 21:34:13 +00:00
|
|
|
case FS_OPCODE_SET_OMASK:
|
|
|
|
return "set_omask";
|
|
|
|
case FS_OPCODE_SET_SAMPLE_ID:
|
|
|
|
return "set_sample_id";
|
2013-03-12 00:36:54 +00:00
|
|
|
case FS_OPCODE_SET_SIMD4X2_OFFSET:
|
|
|
|
return "set_simd4x2_offset";
|
|
|
|
|
|
|
|
case FS_OPCODE_PACK_HALF_2x16_SPLIT:
|
|
|
|
return "pack_half_2x16_split";
|
|
|
|
case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
|
|
|
|
return "unpack_half_2x16_split_x";
|
|
|
|
case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
|
|
|
|
return "unpack_half_2x16_split_y";
|
|
|
|
|
2013-03-28 06:19:39 +00:00
|
|
|
case FS_OPCODE_PLACEHOLDER_HALT:
|
|
|
|
return "placeholder_halt";
|
|
|
|
|
2014-12-06 21:07:16 +00:00
|
|
|
case FS_OPCODE_INTERPOLATE_AT_CENTROID:
|
|
|
|
return "interp_centroid";
|
|
|
|
case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
|
|
|
|
return "interp_sample";
|
|
|
|
case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
|
|
|
|
return "interp_shared_offset";
|
|
|
|
case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
|
|
|
|
return "interp_per_slot_offset";
|
|
|
|
|
2013-03-12 00:36:54 +00:00
|
|
|
case VS_OPCODE_URB_WRITE:
|
2013-03-21 16:11:12 +00:00
|
|
|
return "vs_urb_write";
|
2013-03-12 00:36:54 +00:00
|
|
|
case VS_OPCODE_PULL_CONSTANT_LOAD:
|
|
|
|
return "pull_constant_load";
|
2013-04-04 22:10:18 +01:00
|
|
|
case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
|
|
|
|
return "pull_constant_load_gen7";
|
2015-03-24 15:52:20 +00:00
|
|
|
|
|
|
|
case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
|
|
|
|
return "set_simd4x2_header_gen9";
|
|
|
|
|
2013-08-07 19:31:33 +01:00
|
|
|
case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
|
|
|
|
return "unpack_flags_simd4x2";
|
2013-03-12 00:36:54 +00:00
|
|
|
|
2013-03-21 16:11:12 +00:00
|
|
|
case GS_OPCODE_URB_WRITE:
|
|
|
|
return "gs_urb_write";
|
2014-07-09 15:28:30 +01:00
|
|
|
case GS_OPCODE_URB_WRITE_ALLOCATE:
|
|
|
|
return "gs_urb_write_allocate";
|
2013-03-23 14:42:32 +00:00
|
|
|
case GS_OPCODE_THREAD_END:
|
|
|
|
return "gs_thread_end";
|
2013-03-23 14:59:13 +00:00
|
|
|
case GS_OPCODE_SET_WRITE_OFFSET:
|
|
|
|
return "set_write_offset";
|
2013-03-23 15:18:43 +00:00
|
|
|
case GS_OPCODE_SET_VERTEX_COUNT:
|
|
|
|
return "set_vertex_count";
|
2014-07-17 07:54:03 +01:00
|
|
|
case GS_OPCODE_SET_DWORD_2:
|
|
|
|
return "set_dword_2";
|
2013-04-21 16:51:33 +01:00
|
|
|
case GS_OPCODE_PREPARE_CHANNEL_MASKS:
|
|
|
|
return "prepare_channel_masks";
|
|
|
|
case GS_OPCODE_SET_CHANNEL_MASKS:
|
|
|
|
return "set_channel_masks";
|
2014-01-25 20:55:24 +00:00
|
|
|
case GS_OPCODE_GET_INSTANCE_ID:
|
|
|
|
return "get_instance_id";
|
2014-07-09 07:46:17 +01:00
|
|
|
case GS_OPCODE_FF_SYNC:
|
|
|
|
return "ff_sync";
|
2014-07-24 11:14:27 +01:00
|
|
|
case GS_OPCODE_SET_PRIMITIVE_ID:
|
|
|
|
return "set_primitive_id";
|
2014-07-18 09:36:10 +01:00
|
|
|
case GS_OPCODE_SVB_WRITE:
|
|
|
|
return "gs_svb_write";
|
2014-07-18 09:47:15 +01:00
|
|
|
case GS_OPCODE_SVB_SET_DST_INDEX:
|
|
|
|
return "gs_svb_set_dst_index";
|
2014-07-23 11:56:53 +01:00
|
|
|
case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
|
|
|
|
return "gs_ff_sync_set_primitives";
|
2014-08-27 19:32:08 +01:00
|
|
|
case CS_OPCODE_CS_TERMINATE:
|
|
|
|
return "cs_terminate";
|
2013-03-12 00:36:54 +00:00
|
|
|
}
|
2014-12-06 22:18:21 +00:00
|
|
|
|
|
|
|
unreachable("not reached");
|
2013-03-12 00:36:54 +00:00
|
|
|
}
|
2013-04-28 09:35:57 +01:00
|
|
|
|
2014-12-21 14:56:54 +00:00
|
|
|
bool
|
|
|
|
brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
|
|
|
|
{
|
|
|
|
union {
|
|
|
|
unsigned ud;
|
|
|
|
int d;
|
|
|
|
float f;
|
2015-03-07 06:08:00 +00:00
|
|
|
} imm = { reg->dw1.ud }, sat_imm = { 0 };
|
2014-12-21 14:56:54 +00:00
|
|
|
|
|
|
|
switch (type) {
|
|
|
|
case BRW_REGISTER_TYPE_UD:
|
|
|
|
case BRW_REGISTER_TYPE_D:
|
|
|
|
case BRW_REGISTER_TYPE_UQ:
|
|
|
|
case BRW_REGISTER_TYPE_Q:
|
|
|
|
/* Nothing to do. */
|
|
|
|
return false;
|
|
|
|
case BRW_REGISTER_TYPE_UW:
|
|
|
|
sat_imm.ud = CLAMP(imm.ud, 0, USHRT_MAX);
|
|
|
|
break;
|
|
|
|
case BRW_REGISTER_TYPE_W:
|
|
|
|
sat_imm.d = CLAMP(imm.d, SHRT_MIN, SHRT_MAX);
|
|
|
|
break;
|
|
|
|
case BRW_REGISTER_TYPE_F:
|
|
|
|
sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
|
|
|
|
break;
|
|
|
|
case BRW_REGISTER_TYPE_UB:
|
|
|
|
case BRW_REGISTER_TYPE_B:
|
2015-01-29 19:16:43 +00:00
|
|
|
unreachable("no UB/B immediates");
|
2014-12-21 14:56:54 +00:00
|
|
|
case BRW_REGISTER_TYPE_V:
|
|
|
|
case BRW_REGISTER_TYPE_UV:
|
|
|
|
case BRW_REGISTER_TYPE_VF:
|
2015-02-11 22:53:08 +00:00
|
|
|
unreachable("unimplemented: saturate vector immediate");
|
2014-12-21 14:56:54 +00:00
|
|
|
case BRW_REGISTER_TYPE_DF:
|
|
|
|
case BRW_REGISTER_TYPE_HF:
|
2015-02-11 22:53:08 +00:00
|
|
|
unreachable("unimplemented: saturate DF/HF immediate");
|
2014-12-21 14:56:54 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
if (imm.ud != sat_imm.ud) {
|
|
|
|
reg->dw1.ud = sat_imm.ud;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2015-01-29 19:15:10 +00:00
|
|
|
bool
|
|
|
|
brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
|
|
|
|
{
|
|
|
|
switch (type) {
|
|
|
|
case BRW_REGISTER_TYPE_D:
|
2015-02-06 12:38:20 +00:00
|
|
|
case BRW_REGISTER_TYPE_UD:
|
2015-01-29 19:15:10 +00:00
|
|
|
reg->dw1.d = -reg->dw1.d;
|
|
|
|
return true;
|
|
|
|
case BRW_REGISTER_TYPE_W:
|
2015-02-06 12:38:20 +00:00
|
|
|
case BRW_REGISTER_TYPE_UW:
|
2015-01-29 19:15:10 +00:00
|
|
|
reg->dw1.d = -(int16_t)reg->dw1.ud;
|
|
|
|
return true;
|
|
|
|
case BRW_REGISTER_TYPE_F:
|
|
|
|
reg->dw1.f = -reg->dw1.f;
|
|
|
|
return true;
|
|
|
|
case BRW_REGISTER_TYPE_VF:
|
|
|
|
reg->dw1.ud ^= 0x80808080;
|
|
|
|
return true;
|
|
|
|
case BRW_REGISTER_TYPE_UB:
|
|
|
|
case BRW_REGISTER_TYPE_B:
|
|
|
|
unreachable("no UB/B immediates");
|
|
|
|
case BRW_REGISTER_TYPE_UV:
|
|
|
|
case BRW_REGISTER_TYPE_V:
|
|
|
|
assert(!"unimplemented: negate UV/V immediate");
|
|
|
|
case BRW_REGISTER_TYPE_UQ:
|
|
|
|
case BRW_REGISTER_TYPE_Q:
|
|
|
|
assert(!"unimplemented: negate UQ/Q immediate");
|
|
|
|
case BRW_REGISTER_TYPE_DF:
|
|
|
|
case BRW_REGISTER_TYPE_HF:
|
|
|
|
assert(!"unimplemented: negate DF/HF immediate");
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2015-01-30 22:14:43 +00:00
|
|
|
bool
|
|
|
|
brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
|
|
|
|
{
|
|
|
|
switch (type) {
|
|
|
|
case BRW_REGISTER_TYPE_D:
|
|
|
|
reg->dw1.d = abs(reg->dw1.d);
|
|
|
|
return true;
|
|
|
|
case BRW_REGISTER_TYPE_W:
|
|
|
|
reg->dw1.d = abs((int16_t)reg->dw1.ud);
|
|
|
|
return true;
|
|
|
|
case BRW_REGISTER_TYPE_F:
|
|
|
|
reg->dw1.f = fabsf(reg->dw1.f);
|
|
|
|
return true;
|
|
|
|
case BRW_REGISTER_TYPE_VF:
|
|
|
|
reg->dw1.ud &= ~0x80808080;
|
|
|
|
return true;
|
|
|
|
case BRW_REGISTER_TYPE_UB:
|
|
|
|
case BRW_REGISTER_TYPE_B:
|
|
|
|
unreachable("no UB/B immediates");
|
|
|
|
case BRW_REGISTER_TYPE_UQ:
|
|
|
|
case BRW_REGISTER_TYPE_UD:
|
|
|
|
case BRW_REGISTER_TYPE_UW:
|
|
|
|
case BRW_REGISTER_TYPE_UV:
|
|
|
|
/* Presumably the absolute value modifier on an unsigned source is a
|
|
|
|
* nop, but it would be nice to confirm.
|
|
|
|
*/
|
|
|
|
assert(!"unimplemented: abs unsigned immediate");
|
|
|
|
case BRW_REGISTER_TYPE_V:
|
|
|
|
assert(!"unimplemented: abs V immediate");
|
|
|
|
case BRW_REGISTER_TYPE_Q:
|
|
|
|
assert(!"unimplemented: abs Q immediate");
|
|
|
|
case BRW_REGISTER_TYPE_DF:
|
|
|
|
case BRW_REGISTER_TYPE_HF:
|
|
|
|
assert(!"unimplemented: abs DF/HF immediate");
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2014-02-14 09:54:02 +00:00
|
|
|
backend_visitor::backend_visitor(struct brw_context *brw,
|
|
|
|
struct gl_shader_program *shader_prog,
|
|
|
|
struct gl_program *prog,
|
2014-02-18 20:50:13 +00:00
|
|
|
struct brw_stage_prog_data *stage_prog_data,
|
|
|
|
gl_shader_stage stage)
|
2014-02-14 09:54:02 +00:00
|
|
|
: brw(brw),
|
2015-04-16 02:00:05 +01:00
|
|
|
devinfo(brw->intelScreen->devinfo),
|
2014-02-14 09:54:02 +00:00
|
|
|
ctx(&brw->ctx),
|
2014-02-18 20:50:13 +00:00
|
|
|
shader(shader_prog ?
|
|
|
|
(struct brw_shader *)shader_prog->_LinkedShaders[stage] : NULL),
|
2014-02-14 09:54:02 +00:00
|
|
|
shader_prog(shader_prog),
|
|
|
|
prog(prog),
|
2014-07-12 04:54:52 +01:00
|
|
|
stage_prog_data(stage_prog_data),
|
2014-07-22 04:05:21 +01:00
|
|
|
cfg(NULL),
|
|
|
|
stage(stage)
|
2014-02-14 09:54:02 +00:00
|
|
|
{
|
2015-02-19 01:38:45 +00:00
|
|
|
debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
|
|
|
|
stage_name = _mesa_shader_stage_to_string(stage);
|
|
|
|
stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
|
2014-02-14 09:54:02 +00:00
|
|
|
}
|
|
|
|
|
2014-06-29 23:35:58 +01:00
|
|
|
bool
|
|
|
|
backend_reg::is_zero() const
|
|
|
|
{
|
|
|
|
if (file != IMM)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
return fixed_hw_reg.dw1.d == 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool
|
|
|
|
backend_reg::is_one() const
|
|
|
|
{
|
|
|
|
if (file != IMM)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
return type == BRW_REGISTER_TYPE_F
|
|
|
|
? fixed_hw_reg.dw1.f == 1.0
|
|
|
|
: fixed_hw_reg.dw1.d == 1;
|
|
|
|
}
|
|
|
|
|
2015-02-05 02:08:21 +00:00
|
|
|
bool
|
|
|
|
backend_reg::is_negative_one() const
|
|
|
|
{
|
|
|
|
if (file != IMM)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
switch (type) {
|
|
|
|
case BRW_REGISTER_TYPE_F:
|
|
|
|
return fixed_hw_reg.dw1.f == -1.0;
|
|
|
|
case BRW_REGISTER_TYPE_D:
|
|
|
|
return fixed_hw_reg.dw1.d == -1;
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-06-29 23:35:58 +01:00
|
|
|
bool
|
|
|
|
backend_reg::is_null() const
|
|
|
|
{
|
|
|
|
return file == HW_REG &&
|
|
|
|
fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
|
|
|
|
fixed_hw_reg.nr == BRW_ARF_NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
bool
|
|
|
|
backend_reg::is_accumulator() const
|
|
|
|
{
|
|
|
|
return file == HW_REG &&
|
|
|
|
fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
|
|
|
|
fixed_hw_reg.nr == BRW_ARF_ACCUMULATOR;
|
|
|
|
}
|
|
|
|
|
2015-03-18 17:35:31 +00:00
|
|
|
bool
|
|
|
|
backend_reg::in_range(const backend_reg &r, unsigned n) const
|
|
|
|
{
|
|
|
|
return (file == r.file &&
|
|
|
|
reg == r.reg &&
|
|
|
|
reg_offset >= r.reg_offset &&
|
|
|
|
reg_offset < r.reg_offset + n);
|
|
|
|
}
|
|
|
|
|
2015-03-13 21:34:06 +00:00
|
|
|
bool
|
|
|
|
backend_instruction::is_commutative() const
|
|
|
|
{
|
|
|
|
switch (opcode) {
|
|
|
|
case BRW_OPCODE_AND:
|
|
|
|
case BRW_OPCODE_OR:
|
|
|
|
case BRW_OPCODE_XOR:
|
|
|
|
case BRW_OPCODE_ADD:
|
|
|
|
case BRW_OPCODE_MUL:
|
|
|
|
return true;
|
|
|
|
case BRW_OPCODE_SEL:
|
|
|
|
/* MIN and MAX are commutative. */
|
|
|
|
if (conditional_mod == BRW_CONDITIONAL_GE ||
|
|
|
|
conditional_mod == BRW_CONDITIONAL_L) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
/* fallthrough */
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-12-30 03:29:21 +00:00
|
|
|
bool
|
|
|
|
backend_instruction::is_3src() const
|
|
|
|
{
|
|
|
|
return opcode < ARRAY_SIZE(opcode_descs) && opcode_descs[opcode].nsrc == 3;
|
|
|
|
}
|
|
|
|
|
2013-04-28 09:35:57 +01:00
|
|
|
bool
|
2014-02-27 23:44:45 +00:00
|
|
|
backend_instruction::is_tex() const
|
2013-04-28 09:35:57 +01:00
|
|
|
{
|
|
|
|
return (opcode == SHADER_OPCODE_TEX ||
|
|
|
|
opcode == FS_OPCODE_TXB ||
|
|
|
|
opcode == SHADER_OPCODE_TXD ||
|
|
|
|
opcode == SHADER_OPCODE_TXF ||
|
2013-12-10 14:36:31 +00:00
|
|
|
opcode == SHADER_OPCODE_TXF_CMS ||
|
2013-12-10 14:38:15 +00:00
|
|
|
opcode == SHADER_OPCODE_TXF_UMS ||
|
2013-11-29 21:32:16 +00:00
|
|
|
opcode == SHADER_OPCODE_TXF_MCS ||
|
2013-04-28 09:35:57 +01:00
|
|
|
opcode == SHADER_OPCODE_TXL ||
|
|
|
|
opcode == SHADER_OPCODE_TXS ||
|
2013-03-31 09:31:12 +01:00
|
|
|
opcode == SHADER_OPCODE_LOD ||
|
2013-10-08 09:42:10 +01:00
|
|
|
opcode == SHADER_OPCODE_TG4 ||
|
|
|
|
opcode == SHADER_OPCODE_TG4_OFFSET);
|
2013-04-28 09:35:57 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
bool
|
2014-02-27 23:44:45 +00:00
|
|
|
backend_instruction::is_math() const
|
2013-04-28 09:35:57 +01:00
|
|
|
{
|
|
|
|
return (opcode == SHADER_OPCODE_RCP ||
|
|
|
|
opcode == SHADER_OPCODE_RSQ ||
|
|
|
|
opcode == SHADER_OPCODE_SQRT ||
|
|
|
|
opcode == SHADER_OPCODE_EXP2 ||
|
|
|
|
opcode == SHADER_OPCODE_LOG2 ||
|
|
|
|
opcode == SHADER_OPCODE_SIN ||
|
|
|
|
opcode == SHADER_OPCODE_COS ||
|
|
|
|
opcode == SHADER_OPCODE_INT_QUOTIENT ||
|
|
|
|
opcode == SHADER_OPCODE_INT_REMAINDER ||
|
|
|
|
opcode == SHADER_OPCODE_POW);
|
|
|
|
}
|
|
|
|
|
|
|
|
bool
|
2014-02-27 23:44:45 +00:00
|
|
|
backend_instruction::is_control_flow() const
|
2013-04-28 09:35:57 +01:00
|
|
|
{
|
|
|
|
switch (opcode) {
|
|
|
|
case BRW_OPCODE_DO:
|
|
|
|
case BRW_OPCODE_WHILE:
|
|
|
|
case BRW_OPCODE_IF:
|
|
|
|
case BRW_OPCODE_ELSE:
|
|
|
|
case BRW_OPCODE_ENDIF:
|
|
|
|
case BRW_OPCODE_BREAK:
|
|
|
|
case BRW_OPCODE_CONTINUE:
|
|
|
|
return true;
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
2013-04-29 22:21:14 +01:00
|
|
|
|
2013-09-20 03:48:22 +01:00
|
|
|
bool
|
2014-02-27 23:44:45 +00:00
|
|
|
backend_instruction::can_do_source_mods() const
|
2013-09-20 03:48:22 +01:00
|
|
|
{
|
|
|
|
switch (opcode) {
|
|
|
|
case BRW_OPCODE_ADDC:
|
|
|
|
case BRW_OPCODE_BFE:
|
|
|
|
case BRW_OPCODE_BFI1:
|
|
|
|
case BRW_OPCODE_BFI2:
|
|
|
|
case BRW_OPCODE_BFREV:
|
|
|
|
case BRW_OPCODE_CBIT:
|
|
|
|
case BRW_OPCODE_FBH:
|
|
|
|
case BRW_OPCODE_FBL:
|
|
|
|
case BRW_OPCODE_SUBB:
|
|
|
|
return false;
|
|
|
|
default:
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-12-12 07:07:49 +00:00
|
|
|
bool
|
2014-02-27 23:44:45 +00:00
|
|
|
backend_instruction::can_do_saturate() const
|
2013-12-12 07:07:49 +00:00
|
|
|
{
|
|
|
|
switch (opcode) {
|
|
|
|
case BRW_OPCODE_ADD:
|
|
|
|
case BRW_OPCODE_ASR:
|
|
|
|
case BRW_OPCODE_AVG:
|
|
|
|
case BRW_OPCODE_DP2:
|
|
|
|
case BRW_OPCODE_DP3:
|
|
|
|
case BRW_OPCODE_DP4:
|
|
|
|
case BRW_OPCODE_DPH:
|
|
|
|
case BRW_OPCODE_F16TO32:
|
|
|
|
case BRW_OPCODE_F32TO16:
|
|
|
|
case BRW_OPCODE_LINE:
|
|
|
|
case BRW_OPCODE_LRP:
|
|
|
|
case BRW_OPCODE_MAC:
|
|
|
|
case BRW_OPCODE_MACH:
|
|
|
|
case BRW_OPCODE_MAD:
|
|
|
|
case BRW_OPCODE_MATH:
|
|
|
|
case BRW_OPCODE_MOV:
|
|
|
|
case BRW_OPCODE_MUL:
|
|
|
|
case BRW_OPCODE_PLN:
|
|
|
|
case BRW_OPCODE_RNDD:
|
|
|
|
case BRW_OPCODE_RNDE:
|
|
|
|
case BRW_OPCODE_RNDU:
|
|
|
|
case BRW_OPCODE_RNDZ:
|
|
|
|
case BRW_OPCODE_SEL:
|
|
|
|
case BRW_OPCODE_SHL:
|
|
|
|
case BRW_OPCODE_SHR:
|
|
|
|
case FS_OPCODE_LINTERP:
|
|
|
|
case SHADER_OPCODE_COS:
|
|
|
|
case SHADER_OPCODE_EXP2:
|
|
|
|
case SHADER_OPCODE_LOG2:
|
|
|
|
case SHADER_OPCODE_POW:
|
|
|
|
case SHADER_OPCODE_RCP:
|
|
|
|
case SHADER_OPCODE_RSQ:
|
|
|
|
case SHADER_OPCODE_SIN:
|
|
|
|
case SHADER_OPCODE_SQRT:
|
|
|
|
return true;
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-08-24 22:01:48 +01:00
|
|
|
bool
|
|
|
|
backend_instruction::can_do_cmod() const
|
|
|
|
{
|
|
|
|
switch (opcode) {
|
|
|
|
case BRW_OPCODE_ADD:
|
|
|
|
case BRW_OPCODE_ADDC:
|
|
|
|
case BRW_OPCODE_AND:
|
|
|
|
case BRW_OPCODE_ASR:
|
|
|
|
case BRW_OPCODE_AVG:
|
|
|
|
case BRW_OPCODE_CMP:
|
|
|
|
case BRW_OPCODE_CMPN:
|
|
|
|
case BRW_OPCODE_DP2:
|
|
|
|
case BRW_OPCODE_DP3:
|
|
|
|
case BRW_OPCODE_DP4:
|
|
|
|
case BRW_OPCODE_DPH:
|
|
|
|
case BRW_OPCODE_F16TO32:
|
|
|
|
case BRW_OPCODE_F32TO16:
|
|
|
|
case BRW_OPCODE_FRC:
|
|
|
|
case BRW_OPCODE_LINE:
|
|
|
|
case BRW_OPCODE_LRP:
|
|
|
|
case BRW_OPCODE_LZD:
|
|
|
|
case BRW_OPCODE_MAC:
|
|
|
|
case BRW_OPCODE_MACH:
|
|
|
|
case BRW_OPCODE_MAD:
|
|
|
|
case BRW_OPCODE_MOV:
|
|
|
|
case BRW_OPCODE_MUL:
|
|
|
|
case BRW_OPCODE_NOT:
|
|
|
|
case BRW_OPCODE_OR:
|
|
|
|
case BRW_OPCODE_PLN:
|
|
|
|
case BRW_OPCODE_RNDD:
|
|
|
|
case BRW_OPCODE_RNDE:
|
|
|
|
case BRW_OPCODE_RNDU:
|
|
|
|
case BRW_OPCODE_RNDZ:
|
|
|
|
case BRW_OPCODE_SAD2:
|
|
|
|
case BRW_OPCODE_SADA2:
|
|
|
|
case BRW_OPCODE_SHL:
|
|
|
|
case BRW_OPCODE_SHR:
|
|
|
|
case BRW_OPCODE_SUBB:
|
|
|
|
case BRW_OPCODE_XOR:
|
2015-01-24 05:58:51 +00:00
|
|
|
case FS_OPCODE_CINTERP:
|
|
|
|
case FS_OPCODE_LINTERP:
|
2014-08-24 22:01:48 +01:00
|
|
|
return true;
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-04-09 20:01:49 +01:00
|
|
|
bool
|
|
|
|
backend_instruction::reads_accumulator_implicitly() const
|
|
|
|
{
|
|
|
|
switch (opcode) {
|
|
|
|
case BRW_OPCODE_MAC:
|
|
|
|
case BRW_OPCODE_MACH:
|
|
|
|
case BRW_OPCODE_SADA2:
|
|
|
|
return true;
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-05-07 08:58:43 +01:00
|
|
|
bool
|
2015-04-17 20:15:58 +01:00
|
|
|
backend_instruction::writes_accumulator_implicitly(const struct brw_device_info *devinfo) const
|
2014-05-07 08:58:43 +01:00
|
|
|
{
|
|
|
|
return writes_accumulator ||
|
2015-04-17 20:15:58 +01:00
|
|
|
(devinfo->gen < 6 &&
|
2014-05-07 08:58:43 +01:00
|
|
|
((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
|
2014-11-08 09:39:14 +00:00
|
|
|
(opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
|
2014-05-07 08:58:43 +01:00
|
|
|
opcode != FS_OPCODE_CINTERP)));
|
|
|
|
}
|
|
|
|
|
2013-10-20 22:02:08 +01:00
|
|
|
bool
|
|
|
|
backend_instruction::has_side_effects() const
|
|
|
|
{
|
|
|
|
switch (opcode) {
|
|
|
|
case SHADER_OPCODE_UNTYPED_ATOMIC:
|
2015-02-28 21:36:21 +00:00
|
|
|
case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
|
2015-04-23 12:24:14 +01:00
|
|
|
case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
|
2015-04-23 12:28:25 +01:00
|
|
|
case SHADER_OPCODE_TYPED_ATOMIC:
|
|
|
|
case SHADER_OPCODE_TYPED_SURFACE_WRITE:
|
2015-04-23 12:30:28 +01:00
|
|
|
case SHADER_OPCODE_MEMORY_FENCE:
|
2014-10-21 07:00:50 +01:00
|
|
|
case SHADER_OPCODE_URB_WRITE_SIMD8:
|
2014-09-13 00:17:37 +01:00
|
|
|
case FS_OPCODE_FB_WRITE:
|
2013-10-20 22:02:08 +01:00
|
|
|
return true;
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-07-13 05:16:34 +01:00
|
|
|
#ifndef NDEBUG
|
|
|
|
static bool
|
|
|
|
inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
|
|
|
|
{
|
|
|
|
bool found = false;
|
|
|
|
foreach_inst_in_block (backend_instruction, i, block) {
|
|
|
|
if (inst == i) {
|
|
|
|
found = true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return found;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
static void
|
|
|
|
adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
|
|
|
|
{
|
2014-09-03 05:07:51 +01:00
|
|
|
for (bblock_t *block_iter = start_block->next();
|
2014-07-13 05:16:34 +01:00
|
|
|
!block_iter->link.is_tail_sentinel();
|
2014-09-03 05:07:51 +01:00
|
|
|
block_iter = block_iter->next()) {
|
2014-07-13 05:16:34 +01:00
|
|
|
block_iter->start_ip += ip_adjustment;
|
|
|
|
block_iter->end_ip += ip_adjustment;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-07-13 05:18:08 +01:00
|
|
|
void
|
|
|
|
backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
|
|
|
|
{
|
2015-02-18 02:01:41 +00:00
|
|
|
if (!this->is_head_sentinel())
|
|
|
|
assert(inst_is_in_block(block, this) || !"Instruction not in block");
|
2014-07-13 05:18:08 +01:00
|
|
|
|
|
|
|
block->end_ip++;
|
|
|
|
|
|
|
|
adjust_later_block_ips(block, 1);
|
|
|
|
|
|
|
|
exec_node::insert_after(inst);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
|
|
|
|
{
|
2015-02-18 02:01:41 +00:00
|
|
|
if (!this->is_tail_sentinel())
|
|
|
|
assert(inst_is_in_block(block, this) || !"Instruction not in block");
|
2014-07-13 05:18:08 +01:00
|
|
|
|
|
|
|
block->end_ip++;
|
|
|
|
|
|
|
|
adjust_later_block_ips(block, 1);
|
|
|
|
|
|
|
|
exec_node::insert_before(inst);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
backend_instruction::insert_before(bblock_t *block, exec_list *list)
|
|
|
|
{
|
|
|
|
assert(inst_is_in_block(block, this) || !"Instruction not in block");
|
|
|
|
|
|
|
|
unsigned num_inst = list->length();
|
|
|
|
|
|
|
|
block->end_ip += num_inst;
|
|
|
|
|
|
|
|
adjust_later_block_ips(block, num_inst);
|
|
|
|
|
|
|
|
exec_node::insert_before(list);
|
|
|
|
}
|
|
|
|
|
2014-07-13 05:16:34 +01:00
|
|
|
void
|
|
|
|
backend_instruction::remove(bblock_t *block)
|
|
|
|
{
|
|
|
|
assert(inst_is_in_block(block, this) || !"Instruction not in block");
|
|
|
|
|
|
|
|
adjust_later_block_ips(block, -1);
|
|
|
|
|
|
|
|
if (block->start_ip == block->end_ip) {
|
|
|
|
block->cfg->remove_block(block);
|
|
|
|
} else {
|
|
|
|
block->end_ip--;
|
|
|
|
}
|
|
|
|
|
|
|
|
exec_node::remove();
|
|
|
|
}
|
|
|
|
|
2013-04-29 22:21:14 +01:00
|
|
|
void
|
|
|
|
backend_visitor::dump_instructions()
|
|
|
|
{
|
2014-05-29 21:08:59 +01:00
|
|
|
dump_instructions(NULL);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
backend_visitor::dump_instructions(const char *name)
|
|
|
|
{
|
|
|
|
FILE *file = stderr;
|
|
|
|
if (name && geteuid() != 0) {
|
|
|
|
file = fopen(name, "w");
|
|
|
|
if (!file)
|
|
|
|
file = stderr;
|
|
|
|
}
|
|
|
|
|
2015-02-13 18:46:32 +00:00
|
|
|
if (cfg) {
|
|
|
|
int ip = 0;
|
|
|
|
foreach_block_and_inst(block, backend_instruction, inst, cfg) {
|
|
|
|
fprintf(file, "%4d: ", ip++);
|
|
|
|
dump_instruction(inst, file);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
int ip = 0;
|
|
|
|
foreach_in_list(backend_instruction, inst, &instructions) {
|
|
|
|
fprintf(file, "%4d: ", ip++);
|
|
|
|
dump_instruction(inst, file);
|
|
|
|
}
|
2014-05-29 21:08:59 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
if (file != stderr) {
|
|
|
|
fclose(file);
|
2013-04-29 22:21:14 +01:00
|
|
|
}
|
|
|
|
}
|
2013-10-03 17:58:43 +01:00
|
|
|
|
2014-07-12 04:54:52 +01:00
|
|
|
void
|
|
|
|
backend_visitor::calculate_cfg()
|
|
|
|
{
|
|
|
|
if (this->cfg)
|
|
|
|
return;
|
|
|
|
cfg = new(mem_ctx) cfg_t(&this->instructions);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
backend_visitor::invalidate_cfg()
|
|
|
|
{
|
|
|
|
ralloc_free(this->cfg);
|
|
|
|
this->cfg = NULL;
|
|
|
|
}
|
2013-10-03 17:58:43 +01:00
|
|
|
|
|
|
|
/**
|
|
|
|
* Sets up the starting offsets for the groups of binding table entries
|
|
|
|
* commong to all pipeline stages.
|
|
|
|
*
|
|
|
|
* Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
|
|
|
|
* unused but also make sure that addition of small offsets to them will
|
|
|
|
* trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
|
|
|
|
*/
|
|
|
|
void
|
|
|
|
backend_visitor::assign_common_binding_table_offsets(uint32_t next_binding_table_offset)
|
|
|
|
{
|
|
|
|
int num_textures = _mesa_fls(prog->SamplersUsed);
|
|
|
|
|
|
|
|
stage_prog_data->binding_table.texture_start = next_binding_table_offset;
|
|
|
|
next_binding_table_offset += num_textures;
|
|
|
|
|
|
|
|
if (shader) {
|
|
|
|
stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
|
|
|
|
next_binding_table_offset += shader->base.NumUniformBlocks;
|
|
|
|
} else {
|
|
|
|
stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
|
|
|
|
stage_prog_data->binding_table.shader_time_start = next_binding_table_offset;
|
|
|
|
next_binding_table_offset++;
|
|
|
|
} else {
|
|
|
|
stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (prog->UsesGather) {
|
2015-04-16 02:00:05 +01:00
|
|
|
if (devinfo->gen >= 8) {
|
2014-05-29 08:06:08 +01:00
|
|
|
stage_prog_data->binding_table.gather_texture_start =
|
|
|
|
stage_prog_data->binding_table.texture_start;
|
|
|
|
} else {
|
|
|
|
stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
|
|
|
|
next_binding_table_offset += num_textures;
|
|
|
|
}
|
2013-10-03 17:58:43 +01:00
|
|
|
} else {
|
|
|
|
stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
|
|
|
|
}
|
|
|
|
|
2013-10-20 21:09:57 +01:00
|
|
|
if (shader_prog && shader_prog->NumAtomicBuffers) {
|
|
|
|
stage_prog_data->binding_table.abo_start = next_binding_table_offset;
|
|
|
|
next_binding_table_offset += shader_prog->NumAtomicBuffers;
|
|
|
|
} else {
|
|
|
|
stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
|
|
|
|
}
|
|
|
|
|
2013-11-23 00:08:12 +00:00
|
|
|
if (shader && shader->base.NumImages) {
|
|
|
|
stage_prog_data->binding_table.image_start = next_binding_table_offset;
|
|
|
|
next_binding_table_offset += shader->base.NumImages;
|
|
|
|
} else {
|
|
|
|
stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
|
|
|
|
}
|
|
|
|
|
2013-10-03 17:58:43 +01:00
|
|
|
/* This may or may not be used depending on how the compile goes. */
|
|
|
|
stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
|
|
|
|
next_binding_table_offset++;
|
|
|
|
|
|
|
|
assert(next_binding_table_offset <= BRW_MAX_SURFACES);
|
|
|
|
|
2013-11-27 03:56:07 +00:00
|
|
|
/* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
|
2013-10-03 17:58:43 +01:00
|
|
|
}
|