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i965/vec4: Implement VS_OPCODE_GET_BUFFER_SIZE 

Notice that Skylake needs to include a header in the sampler message
so it will need some tweaks to work there.

Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
This commit is contained in:
Samuel Iglesias Gonsalvez 2015-08-28 09:39:49 +02:00
parent 003ce30e36
commit 6485880232
5 changed files with 44 additions and 0 deletions
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3
src/mesa/drivers/dri/i965/brw_defines.h
View File

@ -1084,6 +1084,9 @@ enum opcode {
VS_OPCODE_PULL_CONSTANT_LOAD,
VS_OPCODE_PULL_CONSTANT_LOAD_GEN7,
VS_OPCODE_SET_SIMD4X2_HEADER_GEN9,
VS_OPCODE_GET_BUFFER_SIZE,
VS_OPCODE_UNPACK_FLAGS_SIMD4X2,
/**

3
src/mesa/drivers/dri/i965/brw_shader.cpp
View File

@ -745,6 +745,9 @@ brw_instruction_name(enum opcode op)
case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
return "set_simd4x2_header_gen9";
case VS_OPCODE_GET_BUFFER_SIZE:
return "vs_get_buffer_size";
case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
return "unpack_flags_simd4x2";

1
src/mesa/drivers/dri/i965/brw_vec4.cpp
View File

@ -332,6 +332,7 @@ vec4_visitor::implied_mrf_writes(vec4_instruction *inst)
case SHADER_OPCODE_TG4:
case SHADER_OPCODE_TG4_OFFSET:
case SHADER_OPCODE_SAMPLEINFO:
case VS_OPCODE_GET_BUFFER_SIZE:
return inst->header_size;
default:
unreachable("not reached");

6
src/mesa/drivers/dri/i965/brw_vec4.h
View File

@ -560,6 +560,12 @@ private:
struct brw_reg offset);
void generate_set_simd4x2_header_gen9(vec4_instruction *inst,
struct brw_reg dst);
void generate_get_buffer_size(vec4_instruction *inst,
struct brw_reg dst,
struct brw_reg src,
struct brw_reg index);
void generate_unpack_flags(struct brw_reg dst);
const struct brw_compiler *compiler;

31
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
View File

@ -1032,6 +1032,32 @@ vec4_generator::generate_pull_constant_load(vec4_instruction *inst,
brw_mark_surface_used(&prog_data->base, surf_index);
}
void
vec4_generator::generate_get_buffer_size(vec4_instruction *inst,
struct brw_reg dst,
struct brw_reg src,
struct brw_reg surf_index)
{
assert(devinfo->gen >= 7);
assert(surf_index.type == BRW_REGISTER_TYPE_UD &&
surf_index.file == BRW_IMMEDIATE_VALUE);
brw_SAMPLE(p,
dst,
inst->base_mrf,
src,
surf_index.dw1.ud,
0,
GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO,
1, /* response length */
inst->mlen,
inst->header_size > 0,
BRW_SAMPLER_SIMD_MODE_SIMD4X2,
BRW_SAMPLER_RETURN_FORMAT_SINT32);
brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
}
void
vec4_generator::generate_pull_constant_load_gen7(vec4_instruction *inst,
struct brw_reg dst,
@ -1409,6 +1435,11 @@ vec4_generator::generate_code(const cfg_t *cfg)
generate_set_simd4x2_header_gen9(inst, dst);
break;
case VS_OPCODE_GET_BUFFER_SIZE:
generate_get_buffer_size(inst, dst, src[0], src[1]);
break;
case GS_OPCODE_URB_WRITE:
generate_gs_urb_write(inst);
break;