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mesa/src/mesa/drivers/dri/i965/brw_fs_generator.cpp

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i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
/*
* Copyright © 2010 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*/
i965: Rename brw_{fs,vec4}_emit.cpp to brw_{fs,vec4}_generator.cpp. The previous names were really confusing to talk about: - brw_fs_visitor() contained methods named emit_whatever(). - brw_fs_generator() contained methods named generate_whatever(), but lived in brw_fs_emit.cpp. So when someone said "the emit layer", or "emit code", we weren't sure whether they meant the visitor's emit() functions or the generator in brw_fs_emit.cpp. By renaming these files, the method names, class names, and file names all match, which is much less confusing. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Eric Anholt <eric@anholt.net>
2013-09-18 07:32:10 +01:00
/** @file brw_fs_generator.cpp
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
*
i965: Rename brw_{fs,vec4}_emit.cpp to brw_{fs,vec4}_generator.cpp. The previous names were really confusing to talk about: - brw_fs_visitor() contained methods named emit_whatever(). - brw_fs_generator() contained methods named generate_whatever(), but lived in brw_fs_emit.cpp. So when someone said "the emit layer", or "emit code", we weren't sure whether they meant the visitor's emit() functions or the generator in brw_fs_emit.cpp. By renaming these files, the method names, class names, and file names all match, which is much less confusing. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Eric Anholt <eric@anholt.net>
2013-09-18 07:32:10 +01:00
* This file supports generating code from the FS LIR to the actual
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
* native instructions.
*/
#include "brw_eu.h"
#include "brw_fs.h"
i965: Move brw_fs_cfg.* to brw_cfg.*. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-10-03 21:03:12 +01:00
#include "brw_cfg.h"
i965: Push down inclusion of brw_program.h. We were including it in headers, which then caused it to be included in tons of places it wasn't needed. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2015-11-22 23:30:59 +00:00
#include "brw_program.h"
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
i965: Add and use enum brw_reg_file. Reviewed-by: Emil Velikov <emil.velikov@collabora.co.uk> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-10-23 21:11:44 +01:00
static enum brw_reg_file
brw_file_from_reg(fs_reg *reg)
i965/fs: Move brw_file_from_reg() higher in the file. This was supposed to be part of the previous commit.
2014-12-05 17:53:11 +00:00
{
switch (reg->file) {
i965: Replace HW_REG with ARF/FIXED_GRF. HW_REGs are (were!) kind of awful. If the file was HW_REG, you had to look at different fields for type, abs, negate, writemask, swizzle, and a second file. They also caused annoying problems like immediate sources being considered scheduling barriers (commit 6148e94e2) and other such nonsense. Instead use ARF/FIXED_GRF/MRF for fixed registers in those files. After a sufficient amount of time has passed since "GRF" was used, we can rename FIXED_GRF -> GRF, but doing so now would make rebasing awful. Reviewed-by: Emil Velikov <emil.velikov@collabora.co.uk> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-10-27 00:52:57 +00:00
case ARF:
return BRW_ARCHITECTURE_REGISTER_FILE;
case FIXED_GRF:
i965: Rename GRF to VGRF. The 2-bit hardware register file field is ARF, GRF, MRF, IMM. Rename GRF to VGRF (virtual GRF) so that we can reuse the GRF name to mean an assigned general purpose register. Reviewed-by: Emil Velikov <emil.velikov@collabora.co.uk> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-10-27 00:09:25 +00:00
case VGRF:
i965/fs: Move brw_file_from_reg() higher in the file. This was supposed to be part of the previous commit.
2014-12-05 17:53:11 +00:00
return BRW_GENERAL_REGISTER_FILE;
case MRF:
return BRW_MESSAGE_REGISTER_FILE;
case IMM:
return BRW_IMMEDIATE_VALUE;
i965: Replace default case with list of enum values. If we add a new file type, we'd like to get warnings if it's not handled. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2015-10-26 13:58:56 +00:00
case BAD_FILE:
case ATTR:
case UNIFORM:
i965/fs: Move brw_file_from_reg() higher in the file. This was supposed to be part of the previous commit.
2014-12-05 17:53:11 +00:00
unreachable("not reached");
}
i965: Add and use enum brw_reg_file. Reviewed-by: Emil Velikov <emil.velikov@collabora.co.uk> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-10-23 21:11:44 +01:00
return BRW_ARCHITECTURE_REGISTER_FILE;
i965/fs: Move brw_file_from_reg() higher in the file. This was supposed to be part of the previous commit.
2014-12-05 17:53:11 +00:00
}
i965/fs: Make brw_reg_from_fs_reg static and remove prototype. And move it above its first use in brw_fs_generator.cpp. Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-11-28 20:21:03 +00:00
static struct brw_reg
i965: Make brw_reg_from_fs_reg() halve exec_size when compressed. In a5d7e144eaf43fee37e6ff9e2de194407087632b, Connor generalized the exec_size halving code to handle more cases. As part of this, he made it not halve anything if the region accessed falls completely in a single register. Unfortunately, it started producing some invalid regions: -add(16) g6<1>F g10<8,8,1>UW -g1<0,1,0>F { align1 compr }; -add(16) g8<1>F g12<8,8,1>UW -g1.1<0,1,0>F { align1 compr }; +add(16) g6<1>F g10<16,16,1>UW -g1<0,1,0>F { align1 compr }; +add(16) g8<1>F g12<16,16,1>UW -g1.1<0,1,0>F { align1 compr }; Here, the UW source region completely fits within a register. However, we have to use instruction compression because the destination region spans two registers. <16,16,1> is invalid because it's compressed. To handle this, skip the "everything fits in one register" case and fall through to the exec_size halving case when compressed. Fixes hundreds of Piglit regressions on GM965. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95370 Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-05-13 07:04:10 +01:00
brw_reg_from_fs_reg(const struct brw_codegen *p,
fs_inst *inst, fs_reg *reg, unsigned gen)
i965/fs: Make brw_reg_from_fs_reg static and remove prototype. And move it above its first use in brw_fs_generator.cpp. Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-11-28 20:21:03 +00:00
{
struct brw_reg brw_reg;
switch (reg->file) {
case MRF:
i965: Use BRW_MRF_COMPR4 macro in more places. Reviewed-by: Emil Velikov <emil.velikov@collabora.co.uk> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-11-02 18:23:12 +00:00
assert((reg->nr & ~BRW_MRF_COMPR4) < BRW_MAX_MRF(gen));
i965: Move MRF register asserts out of brw_reg.h In a later patch we will make BRW_MAX_MRF return a different value depending on the hardware generation, but it is inconvenient to add a gen parameter to the brw_reg functions only for the assertions, so move these to places where we have the hardware generation available. Ken suggested to add the asserts to brw_set_src0 and brw_set_dest since that would make sure that we catch all uses of MRF registers, even those coming from modules that generate native code directly, like blorp. Unfortunately, this is very late in the process which can make things harder to debug, so add asserts to the generator as well. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-09-16 08:08:19 +01:00
/* Fallthrough */
i965: Rename GRF to VGRF. The 2-bit hardware register file field is ARF, GRF, MRF, IMM. Rename GRF to VGRF (virtual GRF) so that we can reuse the GRF name to mean an assigned general purpose register. Reviewed-by: Emil Velikov <emil.velikov@collabora.co.uk> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-10-27 00:09:25 +00:00
case VGRF:
i965/fs: Make brw_reg_from_fs_reg static and remove prototype. And move it above its first use in brw_fs_generator.cpp. Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-11-28 20:21:03 +00:00
if (reg->stride == 0) {
i965: Use brw_reg's nr field to store register number. In addition to combining another field, we get replace silliness like "reg.reg" with something that actually makes sense, "reg.nr"; and no one will ever wonder again why dst.reg isn't a dst_reg. Moving the now 16-bit nr field to a 16-bit boundary decreases code size by about 3k. Reviewed-by: Emil Velikov <emil.velikov@collabora.co.uk> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-10-26 11:35:14 +00:00
brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->nr, 0);
i965: Make brw_reg_from_fs_reg() halve exec_size when compressed. In a5d7e144eaf43fee37e6ff9e2de194407087632b, Connor generalized the exec_size halving code to handle more cases. As part of this, he made it not halve anything if the region accessed falls completely in a single register. Unfortunately, it started producing some invalid regions: -add(16) g6<1>F g10<8,8,1>UW -g1<0,1,0>F { align1 compr }; -add(16) g8<1>F g12<8,8,1>UW -g1.1<0,1,0>F { align1 compr }; +add(16) g6<1>F g10<16,16,1>UW -g1<0,1,0>F { align1 compr }; +add(16) g8<1>F g12<16,16,1>UW -g1.1<0,1,0>F { align1 compr }; Here, the UW source region completely fits within a register. However, we have to use instruction compression because the destination region spans two registers. <16,16,1> is invalid because it's compressed. To handle this, skip the "everything fits in one register" case and fall through to the exec_size halving case when compressed. Fixes hundreds of Piglit regressions on GM965. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95370 Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-05-13 07:04:10 +01:00
} else if (!p->compressed &&
inst->exec_size * reg->stride * type_sz(reg->type) <= 32) {
i965/fs: extend exec_size halving in the generator The HW has a restriction that only vertical stride may cross register boundaries. Previously, this only mattered for SIMD16 instructions where we needed to use the same regioning parameters as the equivalent SIMD8 instruction but double the exec size. But we need to do the same splitting for 64-bit instructions as well as instructions with a stride of 2 (which effectively consume 64 bits per element). Fix up the code to do the right thing instead of special-casing SIMD16. Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-08-04 01:44:08 +01:00
brw_reg = brw_vecn_reg(inst->exec_size, brw_file_from_reg(reg),
reg->nr, 0);
i965/fs_generator: Use inst->exec_size for determining hardware reg widths Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Acked-by: Francisco Jerez <currojerez@riseup.net>
2015-06-18 21:57:37 +01:00
brw_reg = stride(brw_reg, inst->exec_size * reg->stride,
inst->exec_size, reg->stride);
i965/fs: Make brw_reg_from_fs_reg static and remove prototype. And move it above its first use in brw_fs_generator.cpp. Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-11-28 20:21:03 +00:00
} else {
/* From the Haswell PRM:
*
* VertStride must be used to cross GRF register boundaries. This
* rule implies that elements within a 'Width' cannot cross GRF
* boundaries.
*
i965/fs: extend exec_size halving in the generator The HW has a restriction that only vertical stride may cross register boundaries. Previously, this only mattered for SIMD16 instructions where we needed to use the same regioning parameters as the equivalent SIMD8 instruction but double the exec size. But we need to do the same splitting for 64-bit instructions as well as instructions with a stride of 2 (which effectively consume 64 bits per element). Fix up the code to do the right thing instead of special-casing SIMD16. Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-08-04 01:44:08 +01:00
* So, for registers that are large enough, we have to split the exec
* size in two and trust the compression state to sort it out.
i965/fs: Make brw_reg_from_fs_reg static and remove prototype. And move it above its first use in brw_fs_generator.cpp. Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-11-28 20:21:03 +00:00
*/
i965/fs: extend exec_size halving in the generator The HW has a restriction that only vertical stride may cross register boundaries. Previously, this only mattered for SIMD16 instructions where we needed to use the same regioning parameters as the equivalent SIMD8 instruction but double the exec size. But we need to do the same splitting for 64-bit instructions as well as instructions with a stride of 2 (which effectively consume 64 bits per element). Fix up the code to do the right thing instead of special-casing SIMD16. Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-08-04 01:44:08 +01:00
assert(inst->exec_size / 2 * reg->stride * type_sz(reg->type) <= 32);
brw_reg = brw_vecn_reg(inst->exec_size / 2, brw_file_from_reg(reg),
reg->nr, 0);
brw_reg = stride(brw_reg, inst->exec_size / 2 * reg->stride,
inst->exec_size / 2, reg->stride);
i965/fs: Make brw_reg_from_fs_reg static and remove prototype. And move it above its first use in brw_fs_generator.cpp. Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-11-28 20:21:03 +00:00
}
brw_reg = retype(brw_reg, reg->type);
brw_reg = byte_offset(brw_reg, reg->subreg_offset);
i965: Remove fixed_hw_reg field from backend_reg. Since backend_reg now inherits brw_reg, we can use it in place of the fixed_hw_reg field. Reviewed-by: Emil Velikov <emil.velikov@collabora.co.uk> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-10-24 23:29:03 +01:00
brw_reg.abs = reg->abs;
brw_reg.negate = reg->negate;
i965/fs: Make brw_reg_from_fs_reg static and remove prototype. And move it above its first use in brw_fs_generator.cpp. Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-11-28 20:21:03 +00:00
break;
i965: Replace HW_REG with ARF/FIXED_GRF. HW_REGs are (were!) kind of awful. If the file was HW_REG, you had to look at different fields for type, abs, negate, writemask, swizzle, and a second file. They also caused annoying problems like immediate sources being considered scheduling barriers (commit 6148e94e2) and other such nonsense. Instead use ARF/FIXED_GRF/MRF for fixed registers in those files. After a sufficient amount of time has passed since "GRF" was used, we can rename FIXED_GRF -> GRF, but doing so now would make rebasing awful. Reviewed-by: Emil Velikov <emil.velikov@collabora.co.uk> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-10-27 00:52:57 +00:00
case ARF:
case FIXED_GRF:
i965: Drop IMM fs_reg/src_reg -> brw_reg conversions. The previous two commits make this unnecessary. Reviewed-by: Emil Velikov <emil.velikov@collabora.co.uk> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-11-02 20:25:24 +00:00
case IMM:
i965: Prevent implicit upcasts to brw_reg. Now that backend_reg inherits from brw_reg, we have to be careful to avoid the object slicing problem. Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2015-11-20 05:51:37 +00:00
brw_reg = reg->as_brw_reg();
i965/fs: Make brw_reg_from_fs_reg static and remove prototype. And move it above its first use in brw_fs_generator.cpp. Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-11-28 20:21:03 +00:00
break;
case BAD_FILE:
/* Probably unused. */
brw_reg = brw_null_reg();
break;
i965: Replace default case with list of enum values. If we add a new file type, we'd like to get warnings if it's not handled. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2015-10-26 13:58:56 +00:00
case ATTR:
case UNIFORM:
i965/fs: Make brw_reg_from_fs_reg static and remove prototype. And move it above its first use in brw_fs_generator.cpp. Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-11-28 20:21:03 +00:00
unreachable("not reached");
}
return brw_reg;
}
i965: Remove the dependance on brw_context from the generators Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-04-16 22:34:04 +01:00
fs_generator::fs_generator(const struct brw_compiler *compiler, void *log_data,
i965/fs: Plumb a mem_ctx all the way through the FS compile. 'c' is going away, but we still need a memory context that lives for the duration of the compile. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-05-14 09:21:02 +01:00
void *mem_ctx,
i965: Generalize fs_generator further This removes all stage specific data from the generator, and lets us create a generator for any stage. Signed-off-by: Kristian Høgsberg <krh@bitplanet.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-10-21 06:53:31 +01:00
const void *key,
struct brw_stage_prog_data *prog_data,
i965/fs: Print spills:fills and number of promoted constants. Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2015-03-16 19:18:31 +00:00
unsigned promoted_constants,
i965: Pass a shader stage abbreviation to fs_generator(). A lot of messages hardcoded the string "FS", which is confusing on Broadwell, where we use this code for VS support as well. shader-db particularly got confused, as it reported two "FS SIMD8" shaders, and no vertex shaders at all. Craziness ensued. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-01-13 22:28:13 +00:00
bool runtime_check_aads_emit,
i965/fs/generator: Take an actual shader stage rather than a string Cc: "11.1" <mesa-stable@lists.freedesktop.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-01-15 04:27:51 +00:00
gl_shader_stage stage)
i965/fs: Split final assembly code generation out of fs_visitor. Compiling shaders requires several main steps: 1. Generating FS IR from either GLSL IR or Mesa IR 2. Optimizing the IR 3. Register allocation 4. Generating assembly code This patch splits out step 4 into a separate class named "fs_generator." There are several reasons for doing so: 1. Future hardware has a different instruction encoding. Splitting this out will allow us to replace fs_generator (which relies heavily on the brw_eu_emit.c code and struct brw_instruction) with a new code generator that writes the new format. 2. It reduces the size of the fs_visitor monolith. (Arguably, a lot more should be split out, but that's left for "future work.") 3. Separate namespaces allow us to make helper functions for generating instructions in both classes: ADD() can exist in fs_visitor and create IR, while ADD() in fs_generator() can create brw_instructions. (Patches for this upcoming.) Furthermore, this patch changes the order of operations slightly. Rather than doing steps 1-4 for SIMD8, then 1-4 for SIMD16, we now: - Do steps 1-3 for SIMD8, then repeat 1-3 for SIMD16 - Generate final assembly code for both modes together This is because the frontend work can be done independently, but final assembly generation needs to pack both into a single program store to feed the GPU. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-11-09 09:05:47 +00:00
i965: Remove the dependance on brw_context from the generators Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-04-16 22:34:04 +01:00
: compiler(compiler), log_data(log_data),
devinfo(compiler->devinfo), key(key),
i965: Remove shader program argument and member from fs_generator Now that the caller passes in the shader debug name, we don't need this anymore. Signed-off-by: Kristian Høgsberg <krh@bitplanet.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-10-28 02:43:31 +00:00
prog_data(prog_data),
i965/fs: Remove the gl_program from the generator Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2015-10-06 00:01:33 +01:00
promoted_constants(promoted_constants),
i965/fs: Print spills:fills and number of promoted constants. Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2015-03-16 19:18:31 +00:00
runtime_check_aads_emit(runtime_check_aads_emit), debug_flag(false),
i965/fs/generator: Take an actual shader stage rather than a string Cc: "11.1" <mesa-stable@lists.freedesktop.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-01-15 04:27:51 +00:00
stage(stage), mem_ctx(mem_ctx)
i965/fs: Split final assembly code generation out of fs_visitor. Compiling shaders requires several main steps: 1. Generating FS IR from either GLSL IR or Mesa IR 2. Optimizing the IR 3. Register allocation 4. Generating assembly code This patch splits out step 4 into a separate class named "fs_generator." There are several reasons for doing so: 1. Future hardware has a different instruction encoding. Splitting this out will allow us to replace fs_generator (which relies heavily on the brw_eu_emit.c code and struct brw_instruction) with a new code generator that writes the new format. 2. It reduces the size of the fs_visitor monolith. (Arguably, a lot more should be split out, but that's left for "future work.") 3. Separate namespaces allow us to make helper functions for generating instructions in both classes: ADD() can exist in fs_visitor and create IR, while ADD() in fs_generator() can create brw_instructions. (Patches for this upcoming.) Furthermore, this patch changes the order of operations slightly. Rather than doing steps 1-4 for SIMD8, then 1-4 for SIMD16, we now: - Do steps 1-3 for SIMD8, then repeat 1-3 for SIMD16 - Generate final assembly code for both modes together This is because the frontend work can be done independently, but final assembly generation needs to pack both into a single program store to feed the GPU. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-11-09 09:05:47 +00:00
{
i965: Rename brw_compile to brw_codegen This name better matches what it's actually used for. The patch was generated with the following command: for file in *; do sed -i -e s/brw_compile/brw_codegen/g $file done Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-16 19:06:57 +01:00
p = rzalloc(mem_ctx, struct brw_codegen);
brw_init_codegen(devinfo, p, mem_ctx);
i965/fs: Split final assembly code generation out of fs_visitor. Compiling shaders requires several main steps: 1. Generating FS IR from either GLSL IR or Mesa IR 2. Optimizing the IR 3. Register allocation 4. Generating assembly code This patch splits out step 4 into a separate class named "fs_generator." There are several reasons for doing so: 1. Future hardware has a different instruction encoding. Splitting this out will allow us to replace fs_generator (which relies heavily on the brw_eu_emit.c code and struct brw_instruction) with a new code generator that writes the new format. 2. It reduces the size of the fs_visitor monolith. (Arguably, a lot more should be split out, but that's left for "future work.") 3. Separate namespaces allow us to make helper functions for generating instructions in both classes: ADD() can exist in fs_visitor and create IR, while ADD() in fs_generator() can create brw_instructions. (Patches for this upcoming.) Furthermore, this patch changes the order of operations slightly. Rather than doing steps 1-4 for SIMD8, then 1-4 for SIMD16, we now: - Do steps 1-3 for SIMD8, then repeat 1-3 for SIMD16 - Generate final assembly code for both modes together This is because the frontend work can be done independently, but final assembly generation needs to pack both into a single program store to feed the GPU. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-11-09 09:05:47 +00:00
}
fs_generator::~fs_generator()
{
}
i965/fs: Move ip_record class to its one use. Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2014-11-12 19:01:16 +00:00
class ip_record : public exec_node {
public:
DECLARE_RALLOC_CXX_OPERATORS(ip_record)
ip_record(int ip)
{
this->ip = ip;
}
int ip;
};
i965/fs: Make patch_discard_jumps_to_fb_writes return bool. ... to tell us whether it emitted any code. Will be used to determine whether we need to skip an annotation for it. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
2014-05-16 21:06:45 +01:00
bool
i965/fs: Improve performance of shaders that start out with a discard. I had tried this in the past, but ran into trouble with applications that sample from undiscarded pixels in the same subspan. To fix that issue, only jump to the end for an entire subspan at a time. Improves GLbenchmark 2.7 (1024x768) performance by 7.9 +/- 1.5% (n=8). v2: Drop the br variable in the jump instruction -- if I ever do jumps pre-gen6, it'll be a different code block anyway since we don't have HALT until gen6. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-06 18:15:08 +00:00
fs_generator::patch_discard_jumps_to_fb_writes()
{
i965/fs: Add a devinfo field to the generator and use it for gen checks Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 01:45:40 +01:00
if (devinfo->gen < 6 || this->discard_halt_patches.is_empty())
i965/fs: Make patch_discard_jumps_to_fb_writes return bool. ... to tell us whether it emitted any code. Will be used to determine whether we need to skip an annotation for it. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
2014-05-16 21:06:45 +01:00
return false;
i965/fs: Improve performance of shaders that start out with a discard. I had tried this in the past, but ran into trouble with applications that sample from undiscarded pixels in the same subspan. To fix that issue, only jump to the end for an entire subspan at a time. Improves GLbenchmark 2.7 (1024x768) performance by 7.9 +/- 1.5% (n=8). v2: Drop the br variable in the jump instruction -- if I ever do jumps pre-gen6, it'll be a different code block anyway since we don't have HALT until gen6. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-06 18:15:08 +00:00
i965: Make the brw_inst helpers take a device_info instead of a context Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 02:00:06 +01:00
int scale = brw_jump_scale(p->devinfo);
i965/eu: Refactor jump distance scaling to use a helper function. Different generations of hardware measure jump distances in different units. Previously, every function that needed to set a jump target open coded this scaling, or made a hardcoded assumption (i.e. just used 2). Most functions start with the number of instructions to jump, and scale up to the hardware-specific value. So, I made the function match that. Others start with a byte offset, and divide by a constant (8) to obtain the jump distance. This is actually 16 / 2 (the jump scale for Gen5-7). v2: Make the helper a static inline defined in brw_eu.h, instead of an actual function in brw_eu_emit.c (as suggested by Matt). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-30 16:00:25 +01:00
i965/fs: Improve performance of shaders that start out with a discard. I had tried this in the past, but ran into trouble with applications that sample from undiscarded pixels in the same subspan. To fix that issue, only jump to the end for an entire subspan at a time. Improves GLbenchmark 2.7 (1024x768) performance by 7.9 +/- 1.5% (n=8). v2: Drop the br variable in the jump instruction -- if I ever do jumps pre-gen6, it'll be a different code block anyway since we don't have HALT until gen6. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-06 18:15:08 +00:00
/* There is a somewhat strange undocumented requirement of using
* HALT, according to the simulator. If some channel has HALTed to
* a particular UIP, then by the end of the program, every channel
* must have HALTed to that UIP. Furthermore, the tracking is a
* stack, so you can't do the final halt of a UIP after starting
* halting to a new UIP.
*
* Symptoms of not emitting this instruction on actual hardware
* included GPU hangs and sparkly rendering on the piglit discard
* tests.
*/
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 22:29:25 +01:00
brw_inst *last_halt = gen6_HALT(p);
i965: Make the brw_inst helpers take a device_info instead of a context Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 02:00:06 +01:00
brw_inst_set_uip(p->devinfo, last_halt, 1 * scale);
brw_inst_set_jip(p->devinfo, last_halt, 1 * scale);
i965/fs: Improve performance of shaders that start out with a discard. I had tried this in the past, but ran into trouble with applications that sample from undiscarded pixels in the same subspan. To fix that issue, only jump to the end for an entire subspan at a time. Improves GLbenchmark 2.7 (1024x768) performance by 7.9 +/- 1.5% (n=8). v2: Drop the br variable in the jump instruction -- if I ever do jumps pre-gen6, it'll be a different code block anyway since we don't have HALT until gen6. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-06 18:15:08 +00:00
int ip = p->nr_insn;
i965: Use typed foreach_in_list instead of foreach_list. Acked-by: Ian Romanick <ian.d.romanick@intel.com>
2014-06-24 23:53:19 +01:00
foreach_in_list(ip_record, patch_ip, &discard_halt_patches) {
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 22:29:25 +01:00
brw_inst *patch = &p->store[patch_ip->ip];
i965/fs: Improve performance of shaders that start out with a discard. I had tried this in the past, but ran into trouble with applications that sample from undiscarded pixels in the same subspan. To fix that issue, only jump to the end for an entire subspan at a time. Improves GLbenchmark 2.7 (1024x768) performance by 7.9 +/- 1.5% (n=8). v2: Drop the br variable in the jump instruction -- if I ever do jumps pre-gen6, it'll be a different code block anyway since we don't have HALT until gen6. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-06 18:15:08 +00:00
i965: Make the brw_inst helpers take a device_info instead of a context Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 02:00:06 +01:00
assert(brw_inst_opcode(p->devinfo, patch) == BRW_OPCODE_HALT);
i965/fs: Improve performance of shaders that start out with a discard. I had tried this in the past, but ran into trouble with applications that sample from undiscarded pixels in the same subspan. To fix that issue, only jump to the end for an entire subspan at a time. Improves GLbenchmark 2.7 (1024x768) performance by 7.9 +/- 1.5% (n=8). v2: Drop the br variable in the jump instruction -- if I ever do jumps pre-gen6, it'll be a different code block anyway since we don't have HALT until gen6. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-06 18:15:08 +00:00
/* HALT takes a half-instruction distance from the pre-incremented IP. */
i965: Make the brw_inst helpers take a device_info instead of a context Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 02:00:06 +01:00
brw_inst_set_uip(p->devinfo, patch, (ip - patch_ip->ip) * scale);
i965/fs: Improve performance of shaders that start out with a discard. I had tried this in the past, but ran into trouble with applications that sample from undiscarded pixels in the same subspan. To fix that issue, only jump to the end for an entire subspan at a time. Improves GLbenchmark 2.7 (1024x768) performance by 7.9 +/- 1.5% (n=8). v2: Drop the br variable in the jump instruction -- if I ever do jumps pre-gen6, it'll be a different code block anyway since we don't have HALT until gen6. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-06 18:15:08 +00:00
}
this->discard_halt_patches.make_empty();
i965/fs: Make patch_discard_jumps_to_fb_writes return bool. ... to tell us whether it emitted any code. Will be used to determine whether we need to skip an annotation for it. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
2014-05-16 21:06:45 +01:00
return true;
i965/fs: Improve performance of shaders that start out with a discard. I had tried this in the past, but ran into trouble with applications that sample from undiscarded pixels in the same subspan. To fix that issue, only jump to the end for an entire subspan at a time. Improves GLbenchmark 2.7 (1024x768) performance by 7.9 +/- 1.5% (n=8). v2: Drop the br variable in the jump instruction -- if I ever do jumps pre-gen6, it'll be a different code block anyway since we don't have HALT until gen6. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-06 18:15:08 +00:00
}
i965/fs: Add Gen < 6 runtime checks for line antialiasing. In Gen < 6 the hardware generates a runtime bit that indicates whether AA data has to be sent as part of the framebuffer write SEND message. This affects the specific case where we have setup antialiased line rendering and we render polygons which have one face setup in GL_LINE mode (line antialiasing will be used) and the other one in GL_FILL mode (no line antialiasing needed). Currently we are not doing this runtime test and instead we always send AA data, which produces incorrect rendering of the GL_FILL face of the polygon in in the aforementioned scenario (verified in ironlake and gm45). In Gen4 this is, likely, a regression introduced with commit 098acf6c843. In Gen5 this has never worked properly. Gen > 5 are not affected by this. The patch fixes the problem by adding the appropriate runtime check and adjusting the framebuffer write message accordingly in the conflictive scenario. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78679 Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-05 14:03:08 +01:00
void
fs_generator::fire_fb_write(fs_inst *inst,
i965/fs: Add a an optional source to the FS_OPCODE_FB_WRITE instruction Previously, we were use the base_mrf parameter of fs_inst to store the MRF location. In preparation for doing FB writes from the GRF, we now also allow you to set inst->base_mrf to -1 and provide a source register. Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-09-16 23:16:20 +01:00
struct brw_reg payload,
i965/fs: Add Gen < 6 runtime checks for line antialiasing. In Gen < 6 the hardware generates a runtime bit that indicates whether AA data has to be sent as part of the framebuffer write SEND message. This affects the specific case where we have setup antialiased line rendering and we render polygons which have one face setup in GL_LINE mode (line antialiasing will be used) and the other one in GL_FILL mode (no line antialiasing needed). Currently we are not doing this runtime test and instead we always send AA data, which produces incorrect rendering of the GL_FILL face of the polygon in in the aforementioned scenario (verified in ironlake and gm45). In Gen4 this is, likely, a regression introduced with commit 098acf6c843. In Gen5 this has never worked properly. Gen > 5 are not affected by this. The patch fixes the problem by adding the appropriate runtime check and adjusting the framebuffer write message accordingly in the conflictive scenario. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78679 Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-05 14:03:08 +01:00
struct brw_reg implied_header,
GLuint nr)
{
uint32_t msg_control;
i965/fs: Remove direct fs_generator brw_wm_prog_data dependence Instead we store a brw_stage_prog_data pointer, and cast it to brw_wm_prog_data for fragment shader specific code paths. Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-29 20:50:46 +01:00
brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
i965/fs: Add a devinfo field to the generator and use it for gen checks Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 01:45:40 +01:00
if (devinfo->gen < 6) {
i965: Fix Haswell discard regressions since Gen4-5 line AA fix. In commit dc2d3a7f5c217a7cee92380fbf503924a9591bea, Iago accidentally moved fire_fb_write() above the brw_pop_insn_state(), which caused the SEND to lose its predication and change from WE_normal to WE_all. Haswell uses predicated SENDs for discards, so this broke Piglit's tests for discards. We want the Gen4-5 MOV to be uncompressed, unpredicated, and unmasked, but the actual FB write itself should respect those. So, pop state first, and force it again around the single MOV. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=79903
2014-06-11 02:50:03 +01:00
brw_push_insn_state(p);
i965: Replace guess_execution_size with something simpler. guess_execution_size() does two things: 1. Cope with small destination registers. 2. Cope with SIMD8 vs SIMD16 mode. This patch replaces the first with a simple if block in brw_set_dest: if the destination register width is less than 8, you probably want the execution size to match. (I didn't put this in the 3src block because it doesn't seem to matter.) Since only the FS compiler cares about SIMD16 mode, it's easy to just set the default execution size there. This pattern was already been proven in the Gen8+ generator, but we didn't port it back to the existing generator when we combined the two. This is based on a patch from Ken from about a year ago. I've rebased it and and fixed a few bugs. Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-04-14 20:40:34 +01:00
brw_set_default_exec_size(p, BRW_EXECUTE_8);
i965: Fix Haswell discard regressions since Gen4-5 line AA fix. In commit dc2d3a7f5c217a7cee92380fbf503924a9591bea, Iago accidentally moved fire_fb_write() above the brw_pop_insn_state(), which caused the SEND to lose its predication and change from WE_normal to WE_all. Haswell uses predicated SENDs for discards, so this broke Piglit's tests for discards. We want the Gen4-5 MOV to be uncompressed, unpredicated, and unmasked, but the actual FB write itself should respect those. So, pop state first, and force it again around the single MOV. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=79903
2014-06-11 02:50:03 +01:00
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
i965/fs: Add a an optional source to the FS_OPCODE_FB_WRITE instruction Previously, we were use the base_mrf parameter of fs_inst to store the MRF location. In preparation for doing FB writes from the GRF, we now also allow you to set inst->base_mrf to -1 and provide a source register. Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-09-16 23:16:20 +01:00
brw_MOV(p, offset(payload, 1), brw_vec8_grf(1, 0));
i965: Fix Haswell discard regressions since Gen4-5 line AA fix. In commit dc2d3a7f5c217a7cee92380fbf503924a9591bea, Iago accidentally moved fire_fb_write() above the brw_pop_insn_state(), which caused the SEND to lose its predication and change from WE_normal to WE_all. Haswell uses predicated SENDs for discards, so this broke Piglit's tests for discards. We want the Gen4-5 MOV to be uncompressed, unpredicated, and unmasked, but the actual FB write itself should respect those. So, pop state first, and force it again around the single MOV. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=79903
2014-06-11 02:50:03 +01:00
brw_pop_insn_state(p);
i965/fs: Add Gen < 6 runtime checks for line antialiasing. In Gen < 6 the hardware generates a runtime bit that indicates whether AA data has to be sent as part of the framebuffer write SEND message. This affects the specific case where we have setup antialiased line rendering and we render polygons which have one face setup in GL_LINE mode (line antialiasing will be used) and the other one in GL_FILL mode (no line antialiasing needed). Currently we are not doing this runtime test and instead we always send AA data, which produces incorrect rendering of the GL_FILL face of the polygon in in the aforementioned scenario (verified in ironlake and gm45). In Gen4 this is, likely, a regression introduced with commit 098acf6c843. In Gen5 this has never worked properly. Gen > 5 are not affected by this. The patch fixes the problem by adding the appropriate runtime check and adjusting the framebuffer write message accordingly in the conflictive scenario. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78679 Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-05 14:03:08 +01:00
}
i965: Add optimization pass to let us use the replicate data message The data port has a SIMD16 'replicate data' message, which lets us write the same color for all 16 pixels by sending the four floats in the lower half of a register instead of sending 4 times 16 identical component values in 8 registers. The message comes with a lot of restrictions and could be made generally useful by recognizing when those restriction are satisfied. For now, this lets us enable the optimization when we know it's safe, but we don't enable it by default. The optimization works for simple color clear shaders only, but does recognized and support multiple render targets. Signed-off-by: Kristian Høgsberg <krh@bitplanet.net> Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2014-07-07 23:27:17 +01:00
if (inst->opcode == FS_OPCODE_REP_FB_WRITE)
msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED;
i965/fs: Implement SIMD16 dual source blending. From the SNB PRM, volume 4, part 1, page 193: "The dual source render target messages only have SIMD8 forms due to maximum message length limitations. SIMD16 pixel shaders must send two of these messages to cover all of the pixels. Each message contains two colors (4 channels each) for each pixel in the message payload." Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82831 Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-03-05 08:43:38 +00:00
else if (prog_data->dual_src_blend) {
i965/fs: Honour the instruction force_sechalf and exec_size fields for FB writes. We were previously guessing the half based on the EOT flag which seems rather gross. Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-07-13 13:41:34 +01:00
if (!inst->force_sechalf)
i965/fs: Implement SIMD16 dual source blending. From the SNB PRM, volume 4, part 1, page 193: "The dual source render target messages only have SIMD8 forms due to maximum message length limitations. SIMD16 pixel shaders must send two of these messages to cover all of the pixels. Each message contains two colors (4 channels each) for each pixel in the message payload." Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82831 Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-03-05 08:43:38 +00:00
msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
else
msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23;
i965/fs: Honour the instruction force_sechalf and exec_size fields for FB writes. We were previously guessing the half based on the EOT flag which seems rather gross. Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-07-13 13:41:34 +01:00
} else if (inst->exec_size == 16)
i965/fs: Add Gen < 6 runtime checks for line antialiasing. In Gen < 6 the hardware generates a runtime bit that indicates whether AA data has to be sent as part of the framebuffer write SEND message. This affects the specific case where we have setup antialiased line rendering and we render polygons which have one face setup in GL_LINE mode (line antialiasing will be used) and the other one in GL_FILL mode (no line antialiasing needed). Currently we are not doing this runtime test and instead we always send AA data, which produces incorrect rendering of the GL_FILL face of the polygon in in the aforementioned scenario (verified in ironlake and gm45). In Gen4 this is, likely, a regression introduced with commit 098acf6c843. In Gen5 this has never worked properly. Gen > 5 are not affected by this. The patch fixes the problem by adding the appropriate runtime check and adjusting the framebuffer write message accordingly in the conflictive scenario. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78679 Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-05 14:03:08 +01:00
msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
else
msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
uint32_t surf_index =
prog_data->binding_table.render_target_start + inst->target;
i965/fs: Implement SIMD16 dual source blending. From the SNB PRM, volume 4, part 1, page 193: "The dual source render target messages only have SIMD8 forms due to maximum message length limitations. SIMD16 pixel shaders must send two of these messages to cover all of the pixels. Each message contains two colors (4 channels each) for each pixel in the message payload." Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82831 Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-03-05 08:43:38 +00:00
bool last_render_target = inst->eot ||
(prog_data->dual_src_blend && dispatch_width == 16);
i965/fs: Add Gen < 6 runtime checks for line antialiasing. In Gen < 6 the hardware generates a runtime bit that indicates whether AA data has to be sent as part of the framebuffer write SEND message. This affects the specific case where we have setup antialiased line rendering and we render polygons which have one face setup in GL_LINE mode (line antialiasing will be used) and the other one in GL_FILL mode (no line antialiasing needed). Currently we are not doing this runtime test and instead we always send AA data, which produces incorrect rendering of the GL_FILL face of the polygon in in the aforementioned scenario (verified in ironlake and gm45). In Gen4 this is, likely, a regression introduced with commit 098acf6c843. In Gen5 this has never worked properly. Gen > 5 are not affected by this. The patch fixes the problem by adding the appropriate runtime check and adjusting the framebuffer write message accordingly in the conflictive scenario. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78679 Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-05 14:03:08 +01:00
brw_fb_WRITE(p,
dispatch_width,
i965/fs: Add a an optional source to the FS_OPCODE_FB_WRITE instruction Previously, we were use the base_mrf parameter of fs_inst to store the MRF location. In preparation for doing FB writes from the GRF, we now also allow you to set inst->base_mrf to -1 and provide a source register. Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-09-16 23:16:20 +01:00
payload,
i965/fs: Add Gen < 6 runtime checks for line antialiasing. In Gen < 6 the hardware generates a runtime bit that indicates whether AA data has to be sent as part of the framebuffer write SEND message. This affects the specific case where we have setup antialiased line rendering and we render polygons which have one face setup in GL_LINE mode (line antialiasing will be used) and the other one in GL_FILL mode (no line antialiasing needed). Currently we are not doing this runtime test and instead we always send AA data, which produces incorrect rendering of the GL_FILL face of the polygon in in the aforementioned scenario (verified in ironlake and gm45). In Gen4 this is, likely, a regression introduced with commit 098acf6c843. In Gen5 this has never worked properly. Gen > 5 are not affected by this. The patch fixes the problem by adding the appropriate runtime check and adjusting the framebuffer write message accordingly in the conflictive scenario. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78679 Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-05 14:03:08 +01:00
implied_header,
msg_control,
surf_index,
nr,
0,
inst->eot,
i965/fs: Implement SIMD16 dual source blending. From the SNB PRM, volume 4, part 1, page 193: "The dual source render target messages only have SIMD8 forms due to maximum message length limitations. SIMD16 pixel shaders must send two of these messages to cover all of the pixels. Each message contains two colors (4 channels each) for each pixel in the message payload." Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82831 Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-03-05 08:43:38 +00:00
last_render_target,
i965: Change header_present to header_size in backend_instruction Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-03-24 17:17:32 +00:00
inst->header_size != 0);
i965/fs: Add Gen < 6 runtime checks for line antialiasing. In Gen < 6 the hardware generates a runtime bit that indicates whether AA data has to be sent as part of the framebuffer write SEND message. This affects the specific case where we have setup antialiased line rendering and we render polygons which have one face setup in GL_LINE mode (line antialiasing will be used) and the other one in GL_FILL mode (no line antialiasing needed). Currently we are not doing this runtime test and instead we always send AA data, which produces incorrect rendering of the GL_FILL face of the polygon in in the aforementioned scenario (verified in ironlake and gm45). In Gen4 this is, likely, a regression introduced with commit 098acf6c843. In Gen5 this has never worked properly. Gen > 5 are not affected by this. The patch fixes the problem by adding the appropriate runtime check and adjusting the framebuffer write message accordingly in the conflictive scenario. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78679 Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-05 14:03:08 +01:00
brw_mark_surface_used(&prog_data->base, surf_index);
}
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
void
i965/fs: Add a an optional source to the FS_OPCODE_FB_WRITE instruction Previously, we were use the base_mrf parameter of fs_inst to store the MRF location. In preparation for doing FB writes from the GRF, we now also allow you to set inst->base_mrf to -1 and provide a source register. Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-09-16 23:16:20 +01:00
fs_generator::generate_fb_write(fs_inst *inst, struct brw_reg payload)
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
{
i965/fs: Remove direct fs_generator brw_wm_prog_data dependence Instead we store a brw_stage_prog_data pointer, and cast it to brw_wm_prog_data for fragment shader specific code paths. Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-29 20:50:46 +01:00
brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
i965/fs: Remove direct fs_generator brw_wm_prog_key dependence Instead we store a void pointer to the key, and cast it to brw_wm_prog_key for fragment shader specific code paths. Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-29 20:50:46 +01:00
const brw_wm_prog_key * const key = (brw_wm_prog_key * const) this->key;
i965/fs: Add a an optional source to the FS_OPCODE_FB_WRITE instruction Previously, we were use the base_mrf parameter of fs_inst to store the MRF location. In preparation for doing FB writes from the GRF, we now also allow you to set inst->base_mrf to -1 and provide a source register. Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-09-16 23:16:20 +01:00
struct brw_reg implied_header;
i965/fs: Add a devinfo field to the generator and use it for gen checks Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 01:45:40 +01:00
if (devinfo->gen < 8 && !devinfo->is_haswell) {
i965/fs: Treat the FB_WRITE as predicated if we're discarding. Pre-Haswell hardware couldn't actually predicate it, but it's easier to pretend as if it's predicated in the visitor since it will generate a MOV from f0.1. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-11-12 02:02:23 +00:00
brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
}
i965/fs: Add a an optional source to the FS_OPCODE_FB_WRITE instruction Previously, we were use the base_mrf parameter of fs_inst to store the MRF location. In preparation for doing FB writes from the GRF, we now also allow you to set inst->base_mrf to -1 and provide a source register. Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-09-16 23:16:20 +01:00
if (inst->base_mrf >= 0)
payload = brw_message_reg(inst->base_mrf);
i965/fs: Remove direct fs_generator brw_wm_prog_data dependence Instead we store a brw_stage_prog_data pointer, and cast it to brw_wm_prog_data for fragment shader specific code paths. Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-29 20:50:46 +01:00
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
/* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
* move, here's g1.
*/
i965: Change header_present to header_size in backend_instruction Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-03-24 17:17:32 +00:00
if (inst->header_size != 0) {
i965/fs: Move FB write default state mashing in a level. We only need to alter the default state if we're emitting MOVs for header related fields. So, we can simply move the push/pop of state in to the if (header_present) block, bypassing it in the common case. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=79903
2014-06-11 02:54:09 +01:00
brw_push_insn_state(p);
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
i965/fs: Don't set flag_subreg_nr = 1 on predicated FB write setup. On Haswell, we implement "discard" via predicated SEND messages, using f0.1 instead of f0.0. To accomplish this, we set inst->flag_subreg to 1 on the FS_OPCODE_FB_WRITE. Most instructions using fs_inst::flag_subreg expand to a single assembly instruction. However, FS_OPCODE_FB_WRITE can generate several MOVs for setting up header information. We don't want to set flag_subreg on those, so override the default state back to 0. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-08-11 00:15:51 +01:00
brw_set_default_flag_reg(p, 0, 0);
i965/fs: Move FB write default state mashing in a level. We only need to alter the default state if we're emitting MOVs for header related fields. So, we can simply move the push/pop of state in to the if (header_present) block, bypassing it in the common case. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=79903
2014-06-11 02:54:09 +01:00
i965/fs: Use conditional sends to do FB writes on HSW+. This drops the MOVs for header setup, which are totally mis-scheduled. total instructions in shared programs: 1590047 -> 1589331 (-0.05%) instructions in affected programs: 43729 -> 43013 (-1.64%) GAINED: 0 LOST: 0 glb27-trex: x before + after +-----------------------------------------------------------------------------+ | + x xx + + + | | ++ + xxx ++x xx + ** *x+ + + + x * | |+x xx x* x+++xx*x*xx+++*+*xx++** *x* x+***x*+xx+* + * + + *| | |__|__________MA___A___________|___| | +-----------------------------------------------------------------------------+ N Min Max Median Avg Stddev x 49 62.33 65.41 63.49 63.53449 0.62757822 + 50 62.28 65.4 63.7 63.6982 0.656564 No difference proven at 95.0% confidence Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-02-14 05:37:50 +00:00
/* On HSW, the GPU will use the predicate on SENDC, unless the header is
* present.
*/
i965: Set prog_data->uses_kill if simulating alpha test via discards. When using MRT on Gen4-5, we have to simulate GL's alpha test feature by emitting discards in the fragment shader. In this case, it makes sense to set prog_data->uses_kill, which means the fragment shader may kill pixels via the discard mechanism. This saves us from having to look an extra key value in a couple of places, including in the generator. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-11-08 10:34:43 +00:00
if (prog_data->uses_kill) {
i965/fs: Use conditional sends to do FB writes on HSW+. This drops the MOVs for header setup, which are totally mis-scheduled. total instructions in shared programs: 1590047 -> 1589331 (-0.05%) instructions in affected programs: 43729 -> 43013 (-1.64%) GAINED: 0 LOST: 0 glb27-trex: x before + after +-----------------------------------------------------------------------------+ | + x xx + + + | | ++ + xxx ++x xx + ** *x+ + + + x * | |+x xx x* x+++xx*x*xx+++*+*xx++** *x* x+***x*+xx+* + * + + *| | |__|__________MA___A___________|___| | +-----------------------------------------------------------------------------+ N Min Max Median Avg Stddev x 49 62.33 65.41 63.49 63.53449 0.62757822 + 50 62.28 65.4 63.7 63.6982 0.656564 No difference proven at 95.0% confidence Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-02-14 05:37:50 +00:00
struct brw_reg pixel_mask;
i965/fs: Rewrite discards to use a flag subreg to track discarded pixels. This makes much more sense on gen6+, and will also prove useful for early exit of shaders on discard. v2: fix up a stale comment from before converting gen4-5. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-06 20:15:13 +00:00
i965/fs: Add a devinfo field to the generator and use it for gen checks Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 01:45:40 +01:00
if (devinfo->gen >= 6)
i965/fs: Use conditional sends to do FB writes on HSW+. This drops the MOVs for header setup, which are totally mis-scheduled. total instructions in shared programs: 1590047 -> 1589331 (-0.05%) instructions in affected programs: 43729 -> 43013 (-1.64%) GAINED: 0 LOST: 0 glb27-trex: x before + after +-----------------------------------------------------------------------------+ | + x xx + + + | | ++ + xxx ++x xx + ** *x+ + + + x * | |+x xx x* x+++xx*x*xx+++*+*xx++** *x* x+***x*+xx+* + * + + *| | |__|__________MA___A___________|___| | +-----------------------------------------------------------------------------+ N Min Max Median Avg Stddev x 49 62.33 65.41 63.49 63.53449 0.62757822 + 50 62.28 65.4 63.7 63.6982 0.656564 No difference proven at 95.0% confidence Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-02-14 05:37:50 +00:00
pixel_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
else
pixel_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
i965/fs: Rewrite discards to use a flag subreg to track discarded pixels. This makes much more sense on gen6+, and will also prove useful for early exit of shaders on discard. v2: fix up a stale comment from before converting gen4-5. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-06 20:15:13 +00:00
i965/fs: Use conditional sends to do FB writes on HSW+. This drops the MOVs for header setup, which are totally mis-scheduled. total instructions in shared programs: 1590047 -> 1589331 (-0.05%) instructions in affected programs: 43729 -> 43013 (-1.64%) GAINED: 0 LOST: 0 glb27-trex: x before + after +-----------------------------------------------------------------------------+ | + x xx + + + | | ++ + xxx ++x xx + ** *x+ + + + x * | |+x xx x* x+++xx*x*xx+++*+*xx++** *x* x+***x*+xx+* + * + + *| | |__|__________MA___A___________|___| | +-----------------------------------------------------------------------------+ N Min Max Median Avg Stddev x 49 62.33 65.41 63.49 63.53449 0.62757822 + 50 62.28 65.4 63.7 63.6982 0.656564 No difference proven at 95.0% confidence Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-02-14 05:37:50 +00:00
brw_MOV(p, pixel_mask, brw_flag_reg(0, 1));
}
i965/fs: Rewrite discards to use a flag subreg to track discarded pixels. This makes much more sense on gen6+, and will also prove useful for early exit of shaders on discard. v2: fix up a stale comment from before converting gen4-5. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-06 20:15:13 +00:00
i965/fs: Add a devinfo field to the generator and use it for gen checks Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 01:45:40 +01:00
if (devinfo->gen >= 6) {
i965: Replace guess_execution_size with something simpler. guess_execution_size() does two things: 1. Cope with small destination registers. 2. Cope with SIMD8 vs SIMD16 mode. This patch replaces the first with a simple if block in brw_set_dest: if the destination register width is less than 8, you probably want the execution size to match. (I didn't put this in the 3src block because it doesn't seem to matter.) Since only the FS compiler cares about SIMD16 mode, it's easy to just set the default execution size there. This pattern was already been proven in the Gen8+ generator, but we didn't port it back to the existing generator when we combined the two. This is based on a patch from Ken from about a year ago. I've rebased it and and fixed a few bugs. Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-04-14 20:40:34 +01:00
brw_push_insn_state(p);
brw_set_default_exec_size(p, BRW_EXECUTE_16);
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
brw_MOV(p,
i965/fs: Add a an optional source to the FS_OPCODE_FB_WRITE instruction Previously, we were use the base_mrf parameter of fs_inst to store the MRF location. In preparation for doing FB writes from the GRF, we now also allow you to set inst->base_mrf to -1 and provide a source register. Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-09-16 23:16:20 +01:00
retype(payload, BRW_REGISTER_TYPE_UD),
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
i965: Replace guess_execution_size with something simpler. guess_execution_size() does two things: 1. Cope with small destination registers. 2. Cope with SIMD8 vs SIMD16 mode. This patch replaces the first with a simple if block in brw_set_dest: if the destination register width is less than 8, you probably want the execution size to match. (I didn't put this in the 3src block because it doesn't seem to matter.) Since only the FS compiler cares about SIMD16 mode, it's easy to just set the default execution size there. This pattern was already been proven in the Gen8+ generator, but we didn't port it back to the existing generator when we combined the two. This is based on a patch from Ken from about a year ago. I've rebased it and and fixed a few bugs. Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-04-14 20:40:34 +01:00
brw_pop_insn_state(p);
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
i965/fs: Replace c->key with a direct reference in the generators. 'c' is going away. This is also a bit shorter. Marking the key pointer as const will also deter people from changing it in these classes, as that's absolutely not OK. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-05-14 08:24:50 +01:00
if (inst->target > 0 && key->replicate_alpha) {
i965/msaa: Add sample-alpha-to-coverage support for multiple render targets Render Target Write message should include source zero alpha value when sample-alpha-to-coverage is enabled for an FBO with multiple render targets. Source zero alpha value is used as fragment coverage for all the render targets. This patch makes piglit tests draw-buffers-alpha-to-coverage and alpha-to-coverage-no-draw-buffer-zero to pass on Sandybridge. No regressions are observed with piglit all.tests. V2: Revert all the changes made in emit_color_write() function to include src0 alpha for targets > 0. Now handling this case in a if block. V3: Correctly calculate the instruction length for buffer zero. Properly handle the case of dual_src_blend when alpha-to-coverage is enabled. Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-08-02 00:32:06 +01:00
/* Set "Source0 Alpha Present to RenderTarget" bit in message
* header.
*/
brw_OR(p,
i965/fs: Add a an optional source to the FS_OPCODE_FB_WRITE instruction Previously, we were use the base_mrf parameter of fs_inst to store the MRF location. In preparation for doing FB writes from the GRF, we now also allow you to set inst->base_mrf to -1 and provide a source register. Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-09-16 23:16:20 +01:00
vec1(retype(payload, BRW_REGISTER_TYPE_UD)),
i965/msaa: Add sample-alpha-to-coverage support for multiple render targets Render Target Write message should include source zero alpha value when sample-alpha-to-coverage is enabled for an FBO with multiple render targets. Source zero alpha value is used as fragment coverage for all the render targets. This patch makes piglit tests draw-buffers-alpha-to-coverage and alpha-to-coverage-no-draw-buffer-zero to pass on Sandybridge. No regressions are observed with piglit all.tests. V2: Revert all the changes made in emit_color_write() function to include src0 alpha for targets > 0. Now handling this case in a if block. V3: Correctly calculate the instruction length for buffer zero. Properly handle the case of dual_src_blend when alpha-to-coverage is enabled. Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-08-02 00:32:06 +01:00
vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
brw_imm_ud(0x1 << 11));
}
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
if (inst->target > 0) {
/* Set the render target index for choosing BLEND_STATE. */
i965/fs: Add a an optional source to the FS_OPCODE_FB_WRITE instruction Previously, we were use the base_mrf parameter of fs_inst to store the MRF location. In preparation for doing FB writes from the GRF, we now also allow you to set inst->base_mrf to -1 and provide a source register. Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-09-16 23:16:20 +01:00
brw_MOV(p, retype(vec1(suboffset(payload, 2)),
BRW_REGISTER_TYPE_UD),
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
brw_imm_ud(inst->target));
}
i965: Implement ARB_shader_stencil_export (gen9+) v2: remove useless source_stencil_to_render_target (Ken) Squash in the actual packing function, which also got to v2: Move the definition of the OPCODE outside of FB_WRITE opcodes (Matt) Reorder the regioning to be in VWH order (Matt) Don't retype src in the backend, just assert instead (Matt) Rename the debug prints to something better (Matt) Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-10-20 22:29:39 +01:00
/* Set computes stencil to render target */
if (prog_data->computed_stencil) {
brw_OR(p,
vec1(retype(payload, BRW_REGISTER_TYPE_UD)),
vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
brw_imm_ud(0x1 << 14));
}
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
implied_header = brw_null_reg();
} else {
implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
}
i965/fs: Move FB write default state mashing in a level. We only need to alter the default state if we're emitting MOVs for header related fields. So, we can simply move the push/pop of state in to the if (header_present) block, bypassing it in the common case. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=79903
2014-06-11 02:54:09 +01:00
brw_pop_insn_state(p);
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
} else {
implied_header = brw_null_reg();
}
i965/fs: Add Gen < 6 runtime checks for line antialiasing. In Gen < 6 the hardware generates a runtime bit that indicates whether AA data has to be sent as part of the framebuffer write SEND message. This affects the specific case where we have setup antialiased line rendering and we render polygons which have one face setup in GL_LINE mode (line antialiasing will be used) and the other one in GL_FILL mode (no line antialiasing needed). Currently we are not doing this runtime test and instead we always send AA data, which produces incorrect rendering of the GL_FILL face of the polygon in in the aforementioned scenario (verified in ironlake and gm45). In Gen4 this is, likely, a regression introduced with commit 098acf6c843. In Gen5 this has never worked properly. Gen > 5 are not affected by this. The patch fixes the problem by adding the appropriate runtime check and adjusting the framebuffer write message accordingly in the conflictive scenario. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78679 Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-05 14:03:08 +01:00
if (!runtime_check_aads_emit) {
i965/fs: Add a an optional source to the FS_OPCODE_FB_WRITE instruction Previously, we were use the base_mrf parameter of fs_inst to store the MRF location. In preparation for doing FB writes from the GRF, we now also allow you to set inst->base_mrf to -1 and provide a source register. Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-09-16 23:16:20 +01:00
fire_fb_write(inst, payload, implied_header, inst->mlen);
i965/fs: Add Gen < 6 runtime checks for line antialiasing. In Gen < 6 the hardware generates a runtime bit that indicates whether AA data has to be sent as part of the framebuffer write SEND message. This affects the specific case where we have setup antialiased line rendering and we render polygons which have one face setup in GL_LINE mode (line antialiasing will be used) and the other one in GL_FILL mode (no line antialiasing needed). Currently we are not doing this runtime test and instead we always send AA data, which produces incorrect rendering of the GL_FILL face of the polygon in in the aforementioned scenario (verified in ironlake and gm45). In Gen4 this is, likely, a regression introduced with commit 098acf6c843. In Gen5 this has never worked properly. Gen > 5 are not affected by this. The patch fixes the problem by adding the appropriate runtime check and adjusting the framebuffer write message accordingly in the conflictive scenario. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78679 Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-05 14:03:08 +01:00
} else {
/* This can only happen in gen < 6 */
i965/fs: Add a devinfo field to the generator and use it for gen checks Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 01:45:40 +01:00
assert(devinfo->gen < 6);
i965/fs: Add Gen < 6 runtime checks for line antialiasing. In Gen < 6 the hardware generates a runtime bit that indicates whether AA data has to be sent as part of the framebuffer write SEND message. This affects the specific case where we have setup antialiased line rendering and we render polygons which have one face setup in GL_LINE mode (line antialiasing will be used) and the other one in GL_FILL mode (no line antialiasing needed). Currently we are not doing this runtime test and instead we always send AA data, which produces incorrect rendering of the GL_FILL face of the polygon in in the aforementioned scenario (verified in ironlake and gm45). In Gen4 this is, likely, a regression introduced with commit 098acf6c843. In Gen5 this has never worked properly. Gen > 5 are not affected by this. The patch fixes the problem by adding the appropriate runtime check and adjusting the framebuffer write message accordingly in the conflictive scenario. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78679 Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-05 14:03:08 +01:00
struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
/* Check runtime bit to detect if we have to send AA data or not */
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
brw_AND(p,
v1_null_ud,
retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD),
brw_imm_ud(1<<26));
i965: Make the brw_inst helpers take a device_info instead of a context Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 02:00:06 +01:00
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
i965/fs: Add Gen < 6 runtime checks for line antialiasing. In Gen < 6 the hardware generates a runtime bit that indicates whether AA data has to be sent as part of the framebuffer write SEND message. This affects the specific case where we have setup antialiased line rendering and we render polygons which have one face setup in GL_LINE mode (line antialiasing will be used) and the other one in GL_FILL mode (no line antialiasing needed). Currently we are not doing this runtime test and instead we always send AA data, which produces incorrect rendering of the GL_FILL face of the polygon in in the aforementioned scenario (verified in ironlake and gm45). In Gen4 this is, likely, a regression introduced with commit 098acf6c843. In Gen5 this has never worked properly. Gen > 5 are not affected by this. The patch fixes the problem by adding the appropriate runtime check and adjusting the framebuffer write message accordingly in the conflictive scenario. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78679 Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-05 14:03:08 +01:00
int jmp = brw_JMPI(p, brw_imm_ud(0), BRW_PREDICATE_NORMAL) - p->store;
i965: Make the brw_inst helpers take a device_info instead of a context Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 02:00:06 +01:00
brw_inst_set_exec_size(p->devinfo, brw_last_inst, BRW_EXECUTE_1);
i965/fs: Add Gen < 6 runtime checks for line antialiasing. In Gen < 6 the hardware generates a runtime bit that indicates whether AA data has to be sent as part of the framebuffer write SEND message. This affects the specific case where we have setup antialiased line rendering and we render polygons which have one face setup in GL_LINE mode (line antialiasing will be used) and the other one in GL_FILL mode (no line antialiasing needed). Currently we are not doing this runtime test and instead we always send AA data, which produces incorrect rendering of the GL_FILL face of the polygon in in the aforementioned scenario (verified in ironlake and gm45). In Gen4 this is, likely, a regression introduced with commit 098acf6c843. In Gen5 this has never worked properly. Gen > 5 are not affected by this. The patch fixes the problem by adding the appropriate runtime check and adjusting the framebuffer write message accordingly in the conflictive scenario. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78679 Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-05 14:03:08 +01:00
{
/* Don't send AA data */
i965/fs: Add a an optional source to the FS_OPCODE_FB_WRITE instruction Previously, we were use the base_mrf parameter of fs_inst to store the MRF location. In preparation for doing FB writes from the GRF, we now also allow you to set inst->base_mrf to -1 and provide a source register. Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-09-16 23:16:20 +01:00
fire_fb_write(inst, offset(payload, 1), implied_header, inst->mlen-1);
i965/fs: Add Gen < 6 runtime checks for line antialiasing. In Gen < 6 the hardware generates a runtime bit that indicates whether AA data has to be sent as part of the framebuffer write SEND message. This affects the specific case where we have setup antialiased line rendering and we render polygons which have one face setup in GL_LINE mode (line antialiasing will be used) and the other one in GL_FILL mode (no line antialiasing needed). Currently we are not doing this runtime test and instead we always send AA data, which produces incorrect rendering of the GL_FILL face of the polygon in in the aforementioned scenario (verified in ironlake and gm45). In Gen4 this is, likely, a regression introduced with commit 098acf6c843. In Gen5 this has never worked properly. Gen > 5 are not affected by this. The patch fixes the problem by adding the appropriate runtime check and adjusting the framebuffer write message accordingly in the conflictive scenario. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78679 Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-05 14:03:08 +01:00
}
brw_land_fwd_jump(p, jmp);
i965/fs: Add a an optional source to the FS_OPCODE_FB_WRITE instruction Previously, we were use the base_mrf parameter of fs_inst to store the MRF location. In preparation for doing FB writes from the GRF, we now also allow you to set inst->base_mrf to -1 and provide a source register. Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-09-16 23:16:20 +01:00
fire_fb_write(inst, payload, implied_header, inst->mlen);
i965/fs: Add Gen < 6 runtime checks for line antialiasing. In Gen < 6 the hardware generates a runtime bit that indicates whether AA data has to be sent as part of the framebuffer write SEND message. This affects the specific case where we have setup antialiased line rendering and we render polygons which have one face setup in GL_LINE mode (line antialiasing will be used) and the other one in GL_FILL mode (no line antialiasing needed). Currently we are not doing this runtime test and instead we always send AA data, which produces incorrect rendering of the GL_FILL face of the polygon in in the aforementioned scenario (verified in ironlake and gm45). In Gen4 this is, likely, a regression introduced with commit 098acf6c843. In Gen5 this has never worked properly. Gen > 5 are not affected by this. The patch fixes the problem by adding the appropriate runtime check and adjusting the framebuffer write message accordingly in the conflictive scenario. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78679 Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-05 14:03:08 +01:00
}
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
}
i965: Introduce a MOV_INDIRECT opcode. The geometry and tessellation control shader stages both read from multiple URB entries (one per vertex). The thread payload contains several URB handles which reference these separate memory segments. In GLSL, these inputs are represented as per-vertex arrays; the outermost array index selects which vertex's inputs to read. This array index does not necessarily need to be constant. To handle that, we need to use indirect addressing on GRFs to select which of the thread payload registers has the appropriate URB handle. (This is before we can even think about applying the pull model!) This patch introduces a new opcode which performs a MOV from a source using VxH indirect addressing (which allows each of the 8 SIMD channels to select distinct data.) Based on a patch by Jason Ekstrand. v2: Rename from INDIRECT_THREAD_PAYLOAD_MOV to MOV_INDIRECT; make it a bit more generic. Use regs_read() instead of hacking up the register allocator. (Suggested by Jason Ekstrand.) v3: Fix regs_read() to be more accurate for small unaligned regions. Also rebase on Matt's work. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com> [v3] Reviewed-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com> [v1]
2015-11-08 02:58:34 +00:00
void
fs_generator::generate_mov_indirect(fs_inst *inst,
struct brw_reg dst,
struct brw_reg reg,
struct brw_reg indirect_byte_offset)
{
assert(indirect_byte_offset.type == BRW_REGISTER_TYPE_UD);
assert(indirect_byte_offset.file == BRW_GENERAL_REGISTER_FILE);
unsigned imm_byte_offset = reg.nr * REG_SIZE + reg.subnr;
i965/fs: Add support for MOV_INDIRECT on pre-Broadwell hardware While we're at it, we also add support for the possibility that the indirect is, in fact, a constant. This shouldn't happen in the common case (if it does, that means NIR failed to constant-fold something), but it's possible so we should handle it. Reviewed-by: Kristian Høgsberg <krh@bitplanet.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-11-24 17:01:11 +00:00
if (indirect_byte_offset.file == BRW_IMMEDIATE_VALUE) {
imm_byte_offset += indirect_byte_offset.ud;
i965: Introduce a MOV_INDIRECT opcode. The geometry and tessellation control shader stages both read from multiple URB entries (one per vertex). The thread payload contains several URB handles which reference these separate memory segments. In GLSL, these inputs are represented as per-vertex arrays; the outermost array index selects which vertex's inputs to read. This array index does not necessarily need to be constant. To handle that, we need to use indirect addressing on GRFs to select which of the thread payload registers has the appropriate URB handle. (This is before we can even think about applying the pull model!) This patch introduces a new opcode which performs a MOV from a source using VxH indirect addressing (which allows each of the 8 SIMD channels to select distinct data.) Based on a patch by Jason Ekstrand. v2: Rename from INDIRECT_THREAD_PAYLOAD_MOV to MOV_INDIRECT; make it a bit more generic. Use regs_read() instead of hacking up the register allocator. (Suggested by Jason Ekstrand.) v3: Fix regs_read() to be more accurate for small unaligned regions. Also rebase on Matt's work. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com> [v3] Reviewed-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com> [v1]
2015-11-08 02:58:34 +00:00
i965/fs: Add support for MOV_INDIRECT on pre-Broadwell hardware While we're at it, we also add support for the possibility that the indirect is, in fact, a constant. This shouldn't happen in the common case (if it does, that means NIR failed to constant-fold something), but it's possible so we should handle it. Reviewed-by: Kristian Høgsberg <krh@bitplanet.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-11-24 17:01:11 +00:00
reg.nr = imm_byte_offset / REG_SIZE;
reg.subnr = imm_byte_offset % REG_SIZE;
brw_MOV(p, dst, reg);
} else {
/* Prior to Broadwell, there are only 8 address registers. */
assert(inst->exec_size == 8 || devinfo->gen >= 8);
/* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
struct brw_reg addr = vec8(brw_address_reg(0));
/* The destination stride of an instruction (in bytes) must be greater
* than or equal to the size of the rest of the instruction. Since the
* address register is of type UW, we can't use a D-type instruction.
* In order to get around this, re retype to UW and use a stride.
*/
indirect_byte_offset =
retype(spread(indirect_byte_offset, 2), BRW_REGISTER_TYPE_UW);
struct brw_reg ind_src;
if (devinfo->gen < 8) {
/* From the Haswell PRM section "Register Region Restrictions":
*
* "The lower bits of the AddressImmediate must not overflow to
* change the register address. The lower 5 bits of Address
* Immediate when added to lower 5 bits of address register gives
* the sub-register offset. The upper bits of Address Immediate
* when added to upper bits of address register gives the register
* address. Any overflow from sub-register offset is dropped."
*
* This restriction is only listed in the Haswell PRM but emperical
* testing indicates that it applies on all older generations and is
* lifted on Broadwell.
*
* Since the indirect may cause us to cross a register boundary, this
* makes the base offset almost useless. We could try and do
* something clever where we use a actual base offset if
* base_offset % 32 == 0 but that would mean we were generating
* different code depending on the base offset. Instead, for the
* sake of consistency, we'll just do the add ourselves.
*/
brw_ADD(p, addr, indirect_byte_offset, brw_imm_uw(imm_byte_offset));
ind_src = brw_VxH_indirect(0, 0);
} else {
brw_MOV(p, addr, indirect_byte_offset);
ind_src = brw_VxH_indirect(0, imm_byte_offset);
}
i965: Introduce a MOV_INDIRECT opcode. The geometry and tessellation control shader stages both read from multiple URB entries (one per vertex). The thread payload contains several URB handles which reference these separate memory segments. In GLSL, these inputs are represented as per-vertex arrays; the outermost array index selects which vertex's inputs to read. This array index does not necessarily need to be constant. To handle that, we need to use indirect addressing on GRFs to select which of the thread payload registers has the appropriate URB handle. (This is before we can even think about applying the pull model!) This patch introduces a new opcode which performs a MOV from a source using VxH indirect addressing (which allows each of the 8 SIMD channels to select distinct data.) Based on a patch by Jason Ekstrand. v2: Rename from INDIRECT_THREAD_PAYLOAD_MOV to MOV_INDIRECT; make it a bit more generic. Use regs_read() instead of hacking up the register allocator. (Suggested by Jason Ekstrand.) v3: Fix regs_read() to be more accurate for small unaligned regions. Also rebase on Matt's work. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com> [v3] Reviewed-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com> [v1]
2015-11-08 02:58:34 +00:00
i965/fs: Add support for MOV_INDIRECT on pre-Broadwell hardware While we're at it, we also add support for the possibility that the indirect is, in fact, a constant. This shouldn't happen in the common case (if it does, that means NIR failed to constant-fold something), but it's possible so we should handle it. Reviewed-by: Kristian Høgsberg <krh@bitplanet.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-11-24 17:01:11 +00:00
brw_inst *mov = brw_MOV(p, dst, retype(ind_src, dst.type));
i965: Introduce a MOV_INDIRECT opcode. The geometry and tessellation control shader stages both read from multiple URB entries (one per vertex). The thread payload contains several URB handles which reference these separate memory segments. In GLSL, these inputs are represented as per-vertex arrays; the outermost array index selects which vertex's inputs to read. This array index does not necessarily need to be constant. To handle that, we need to use indirect addressing on GRFs to select which of the thread payload registers has the appropriate URB handle. (This is before we can even think about applying the pull model!) This patch introduces a new opcode which performs a MOV from a source using VxH indirect addressing (which allows each of the 8 SIMD channels to select distinct data.) Based on a patch by Jason Ekstrand. v2: Rename from INDIRECT_THREAD_PAYLOAD_MOV to MOV_INDIRECT; make it a bit more generic. Use regs_read() instead of hacking up the register allocator. (Suggested by Jason Ekstrand.) v3: Fix regs_read() to be more accurate for small unaligned regions. Also rebase on Matt's work. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com> [v3] Reviewed-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com> [v1]
2015-11-08 02:58:34 +00:00
i965/fs: Add support for MOV_INDIRECT on pre-Broadwell hardware While we're at it, we also add support for the possibility that the indirect is, in fact, a constant. This shouldn't happen in the common case (if it does, that means NIR failed to constant-fold something), but it's possible so we should handle it. Reviewed-by: Kristian Høgsberg <krh@bitplanet.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-11-24 17:01:11 +00:00
if (devinfo->gen == 6 && dst.file == BRW_MESSAGE_REGISTER_FILE &&
!inst->get_next()->is_tail_sentinel() &&
((fs_inst *)inst->get_next())->mlen > 0) {
/* From the Sandybridge PRM:
*
* "[Errata: DevSNB(SNB)] If MRF register is updated by any
* instruction that “indexed/indirect” source AND is followed by a
* send, the instruction requires a “Switch”. This is to avoid
* race condition where send may dispatch before MRF is updated."
*/
brw_inst_set_thread_control(devinfo, mov, BRW_THREAD_SWITCH);
}
}
i965: Introduce a MOV_INDIRECT opcode. The geometry and tessellation control shader stages both read from multiple URB entries (one per vertex). The thread payload contains several URB handles which reference these separate memory segments. In GLSL, these inputs are represented as per-vertex arrays; the outermost array index selects which vertex's inputs to read. This array index does not necessarily need to be constant. To handle that, we need to use indirect addressing on GRFs to select which of the thread payload registers has the appropriate URB handle. (This is before we can even think about applying the pull model!) This patch introduces a new opcode which performs a MOV from a source using VxH indirect addressing (which allows each of the 8 SIMD channels to select distinct data.) Based on a patch by Jason Ekstrand. v2: Rename from INDIRECT_THREAD_PAYLOAD_MOV to MOV_INDIRECT; make it a bit more generic. Use regs_read() instead of hacking up the register allocator. (Suggested by Jason Ekstrand.) v3: Fix regs_read() to be more accurate for small unaligned regions. Also rebase on Matt's work. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com> [v3] Reviewed-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com> [v1]
2015-11-08 02:58:34 +00:00
}
i965: Introduce a new SHADER_OPCODE_URB_READ_SIMD8 opcode. In scalar mode, geometry shader inputs can easily take up hundreds of registers. This makes pushing VUE entries impractical; we'll need to resort to the pull model in some cases. To support this, we introduce a new opcode corresponding to the "URB Read SIMD8" message. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2015-09-29 22:32:02 +01:00
void
fs_generator::generate_urb_read(fs_inst *inst,
struct brw_reg dst,
struct brw_reg header)
{
assert(header.file == BRW_GENERAL_REGISTER_FILE);
assert(header.type == BRW_REGISTER_TYPE_UD);
brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
brw_set_dest(p, send, dst);
brw_set_src0(p, send, header);
brw_set_src1(p, send, brw_imm_ud(0u));
brw_inst_set_sfid(p->devinfo, send, BRW_SFID_URB);
brw_inst_set_urb_opcode(p->devinfo, send, GEN8_URB_OPCODE_SIMD8_READ);
i965: Add a SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT opcode. We need to use per-slot offsets when there's non-uniform indexing, as each SIMD channel could have a different index. We want to use them for any non-constant index (even if uniform), as it lives in the message header instead of the descriptor, allowing us to set offsets in GRFs rather than immediates. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
2015-11-07 09:37:33 +00:00
if (inst->opcode == SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT)
brw_inst_set_urb_per_slot_offset(p->devinfo, send, true);
i965: Introduce a new SHADER_OPCODE_URB_READ_SIMD8 opcode. In scalar mode, geometry shader inputs can easily take up hundreds of registers. This makes pushing VUE entries impractical; we'll need to resort to the pull model in some cases. To support this, we introduce a new opcode corresponding to the "URB Read SIMD8" message. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2015-09-29 22:32:02 +01:00
brw_inst_set_mlen(p->devinfo, send, inst->mlen);
brw_inst_set_rlen(p->devinfo, send, inst->regs_written);
brw_inst_set_header_present(p->devinfo, send, true);
brw_inst_set_urb_global_offset(p->devinfo, send, inst->offset);
}
i965: Add SIMD8 URB write low-level IR instruction This is all we need from the generator for SIMD8 vertex shaders. This opcode is just the send instruction, all the hard work will happen in the visitor using LOAD_PAYLOAD. Signed-off-by: Kristian Høgsberg <krh@bitplanet.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-10-21 07:00:50 +01:00
void
fs_generator::generate_urb_write(fs_inst *inst, struct brw_reg payload)
{
brw_inst *insn;
insn = brw_next_insn(p, BRW_OPCODE_SEND);
brw_set_dest(p, insn, brw_null_reg());
brw_set_src0(p, insn, payload);
brw_set_src1(p, insn, brw_imm_d(0));
i965: Make the brw_inst helpers take a device_info instead of a context Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 02:00:06 +01:00
brw_inst_set_sfid(p->devinfo, insn, BRW_SFID_URB);
brw_inst_set_urb_opcode(p->devinfo, insn, GEN8_URB_OPCODE_SIMD8_WRITE);
i965: Add SIMD8 URB write low-level IR instruction This is all we need from the generator for SIMD8 vertex shaders. This opcode is just the send instruction, all the hard work will happen in the visitor using LOAD_PAYLOAD. Signed-off-by: Kristian Høgsberg <krh@bitplanet.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-10-21 07:00:50 +01:00
i965: Introduce new SHADER_OPCODE_URB_WRITE_SIMD8_MASKED/PER_SLOT opcodes. In the vec4 backend, we have a vec4_instruction::urb_write_flags field. There are many kinds of flags for SIMD4x2 messages. However, there are really only two (per-slot offset, use channel masks) for SIMD8 messages. Rather than adding a boolean flag for per-slot offsets (polluting all instructions), I decided to just make three new opcodes. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2015-05-06 08:04:10 +01:00
if (inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT ||
inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT)
brw_inst_set_urb_per_slot_offset(p->devinfo, insn, true);
if (inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED ||
inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT)
brw_inst_set_urb_channel_mask_present(p->devinfo, insn, true);
i965: Make the brw_inst helpers take a device_info instead of a context Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 02:00:06 +01:00
brw_inst_set_mlen(p->devinfo, insn, inst->mlen);
brw_inst_set_rlen(p->devinfo, insn, 0);
brw_inst_set_eot(p->devinfo, insn, inst->eot);
brw_inst_set_header_present(p->devinfo, insn, true);
brw_inst_set_urb_global_offset(p->devinfo, insn, inst->offset);
i965: Add SIMD8 URB write low-level IR instruction This is all we need from the generator for SIMD8 vertex shaders. This opcode is just the send instruction, all the hard work will happen in the visitor using LOAD_PAYLOAD. Signed-off-by: Kristian Høgsberg <krh@bitplanet.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-10-21 07:00:50 +01:00
}
i965/cs: Add generator support for CS_OPCODE_CS_TERMINATE v2: * Don't rely on brw_eu* to generate the send instruction. We now generate the send here, and drop the "i965/cs: Add support for the SEND message that terminates a CS thread" brw_eu* patch. Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-27 19:33:25 +01:00
void
fs_generator::generate_cs_terminate(fs_inst *inst, struct brw_reg payload)
{
struct brw_inst *insn;
insn = brw_next_insn(p, BRW_OPCODE_SEND);
i965: Set dest type to UW for several send messages Without this, on SIMD 16 the send instruction destination will appear to write more than one destination register, causing the simulator to report an error. Of course, the send instruction can actually write more than one destination register regardless of the type set for the destination, so this is a bit strange. Suggested-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2016-02-01 02:28:42 +00:00
brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_UW));
i965/cs: Add generator support for CS_OPCODE_CS_TERMINATE v2: * Don't rely on brw_eu* to generate the send instruction. We now generate the send here, and drop the "i965/cs: Add support for the SEND message that terminates a CS thread" brw_eu* patch. Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-27 19:33:25 +01:00
brw_set_src0(p, insn, payload);
brw_set_src1(p, insn, brw_imm_d(0));
/* Terminate a compute shader by sending a message to the thread spawner.
*/
brw_inst_set_sfid(devinfo, insn, BRW_SFID_THREAD_SPAWNER);
brw_inst_set_mlen(devinfo, insn, 1);
brw_inst_set_rlen(devinfo, insn, 0);
brw_inst_set_eot(devinfo, insn, inst->eot);
brw_inst_set_header_present(devinfo, insn, false);
brw_inst_set_ts_opcode(devinfo, insn, 0); /* Dereference resource */
brw_inst_set_ts_request_type(devinfo, insn, 0); /* Root thread */
/* Note that even though the thread has a URB resource associated with it,
* we set the "do not dereference URB" bit, because the URB resource is
* managed by the fixed-function unit, so it will free it automatically.
*/
brw_inst_set_ts_resource_select(devinfo, insn, 1); /* Do not dereference URB */
brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE);
}
i965: Implement ARB_shader_stencil_export (gen9+) v2: remove useless source_stencil_to_render_target (Ken) Squash in the actual packing function, which also got to v2: Move the definition of the OPCODE outside of FB_WRITE opcodes (Matt) Reorder the regioning to be in VWH order (Matt) Don't retype src in the backend, just assert instead (Matt) Rename the debug prints to something better (Matt) Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-10-20 22:29:39 +01:00
void
fs_generator::generate_stencil_ref_packing(fs_inst *inst,
struct brw_reg dst,
struct brw_reg src)
{
assert(dispatch_width == 8);
assert(devinfo->gen >= 9);
/* Stencil value updates are provided in 8 slots of 1 byte per slot.
* Presumably, in order to save memory bandwidth, the stencil reference
* values written from the FS need to be packed into 2 dwords (this makes
* sense because the stencil values are limited to 1 byte each and a SIMD8
* send, so stencil slots 0-3 in dw0, and 4-7 in dw1.)
*
* The spec is confusing here because in the payload definition of MDP_RTW_S8
* (Message Data Payload for Render Target Writes with Stencil 8b) the
* stencil value seems to be dw4.0-dw4.7. However, if you look at the type of
* dw4 it is type MDPR_STENCIL (Message Data Payload Register) which is the
* packed values specified above and diagrammed below:
*
* 31 0
* --------------------------------
* DW | |
* 2-7 | IGNORED |
* | |
* --------------------------------
* DW1 | STC | STC | STC | STC |
* | slot7 | slot6 | slot5 | slot4|
* --------------------------------
* DW0 | STC | STC | STC | STC |
* | slot3 | slot2 | slot1 | slot0|
* --------------------------------
*/
src.vstride = BRW_VERTICAL_STRIDE_4;
src.width = BRW_WIDTH_1;
src.hstride = BRW_HORIZONTAL_STRIDE_0;
assert(src.type == BRW_REGISTER_TYPE_UB);
brw_MOV(p, retype(dst, BRW_REGISTER_TYPE_UB), src);
}
i965/fs: Implement support for ir_barrier Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-08-27 19:32:08 +01:00
void
fs_generator::generate_barrier(fs_inst *inst, struct brw_reg src)
{
brw_barrier(p, src);
brw_WAIT(p);
}
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
void
i965/fs: Split final assembly code generation out of fs_visitor. Compiling shaders requires several main steps: 1. Generating FS IR from either GLSL IR or Mesa IR 2. Optimizing the IR 3. Register allocation 4. Generating assembly code This patch splits out step 4 into a separate class named "fs_generator." There are several reasons for doing so: 1. Future hardware has a different instruction encoding. Splitting this out will allow us to replace fs_generator (which relies heavily on the brw_eu_emit.c code and struct brw_instruction) with a new code generator that writes the new format. 2. It reduces the size of the fs_visitor monolith. (Arguably, a lot more should be split out, but that's left for "future work.") 3. Separate namespaces allow us to make helper functions for generating instructions in both classes: ADD() can exist in fs_visitor and create IR, while ADD() in fs_generator() can create brw_instructions. (Patches for this upcoming.) Furthermore, this patch changes the order of operations slightly. Rather than doing steps 1-4 for SIMD8, then 1-4 for SIMD16, we now: - Do steps 1-3 for SIMD8, then repeat 1-3 for SIMD16 - Generate final assembly code for both modes together This is because the frontend work can be done independently, but final assembly generation needs to pack both into a single program store to feed the GPU. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-11-09 09:05:47 +00:00
fs_generator::generate_linterp(fs_inst *inst,
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
struct brw_reg dst, struct brw_reg *src)
{
i965/fs: Calculate delta_x and delta_y together. This lets SIMD16 programs on G45 and Gen5 use the PLN instruction. On Ironlake: total instructions in shared programs: 5634757 -> 5518055 (-2.07%) instructions in affected programs: 1745837 -> 1629135 (-6.68%) helped: 11439 HURT: 4 Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-04-07 01:44:40 +01:00
/* PLN reads:
* / in SIMD16 \
* -----------------------------------
* | src1+0 | src1+1 | src1+2 | src1+3 |
* |-----------------------------------|
* |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
* -----------------------------------
*
* but for the LINE/MAC pair, the LINE reads Xs and the MAC reads Ys:
*
* -----------------------------------
* | src1+0 | src1+1 | src1+2 | src1+3 |
* |-----------------------------------|
* |(x0, x1)|(y0, y1)| | | in SIMD8
* |-----------------------------------|
* |(x0, x1)|(x2, x3)|(y0, y1)|(y2, y3)| in SIMD16
* -----------------------------------
*
* See also: emit_interpolation_setup_gen4().
*/
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
struct brw_reg delta_x = src[0];
i965/fs: Calculate delta_x and delta_y together. This lets SIMD16 programs on G45 and Gen5 use the PLN instruction. On Ironlake: total instructions in shared programs: 5634757 -> 5518055 (-2.07%) instructions in affected programs: 1745837 -> 1629135 (-6.68%) helped: 11439 HURT: 4 Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-04-07 01:44:40 +01:00
struct brw_reg delta_y = offset(src[0], dispatch_width / 8);
struct brw_reg interp = src[1];
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
i965/fs: Add a devinfo field to the generator and use it for gen checks Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 01:45:40 +01:00
if (devinfo->has_pln &&
(devinfo->gen >= 7 || (delta_x.nr & 1) == 0)) {
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
brw_PLN(p, dst, interp, delta_x);
} else {
brw_LINE(p, brw_null_reg(), interp, delta_x);
brw_MAC(p, dst, suboffset(interp, 1), delta_y);
}
}
i965/fs: Implement FS_OPCODE_GET_BUFFER_SIZE Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com> Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2015-04-13 15:55:49 +01:00
void
fs_generator::generate_get_buffer_size(fs_inst *inst,
struct brw_reg dst,
struct brw_reg src,
struct brw_reg surf_index)
{
assert(devinfo->gen >= 7);
assert(surf_index.file == BRW_IMMEDIATE_VALUE);
uint32_t simd_mode;
int rlen = 4;
switch (inst->exec_size) {
case 8:
simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
break;
case 16:
simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
break;
default:
unreachable("Invalid width for texture instruction");
}
if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
rlen = 8;
dst = vec16(dst);
}
brw_SAMPLE(p,
retype(dst, BRW_REGISTER_TYPE_UW),
inst->base_mrf,
src,
i965: Make 'dw1' and 'bits' unnamed structures in brw_reg. Generated by sed -i -e 's/\.bits\././g' *.c *.h *.cpp sed -i -e 's/dw1\.//g' *.c *.h *.cpp and then reverting changes to comments in gen7_blorp.cpp and brw_fs_generator.cpp. There wasn't any utility offered by forcing the programmer to list these to access their fields. Removing them will reduce churn in future commits. This is C11 (and gcc has apparently supported it for sometime "compatibility with other compilers") See https://gcc.gnu.org/onlinedocs/gcc/Unnamed-Fields.html Reviewed-by: Emil Velikov <emil.velikov@collabora.co.uk> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-10-23 03:41:30 +01:00
surf_index.ud,
i965/fs: Implement FS_OPCODE_GET_BUFFER_SIZE Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com> Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2015-04-13 15:55:49 +01:00
0,
GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO,
rlen, /* response length */
inst->mlen,
inst->header_size > 0,
simd_mode,
BRW_SAMPLER_RETURN_FORMAT_SINT32);
i965: Make 'dw1' and 'bits' unnamed structures in brw_reg. Generated by sed -i -e 's/\.bits\././g' *.c *.h *.cpp sed -i -e 's/dw1\.//g' *.c *.h *.cpp and then reverting changes to comments in gen7_blorp.cpp and brw_fs_generator.cpp. There wasn't any utility offered by forcing the programmer to list these to access their fields. Removing them will reduce churn in future commits. This is C11 (and gcc has apparently supported it for sometime "compatibility with other compilers") See https://gcc.gnu.org/onlinedocs/gcc/Unnamed-Fields.html Reviewed-by: Emil Velikov <emil.velikov@collabora.co.uk> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-10-23 03:41:30 +01:00
brw_mark_surface_used(prog_data, surf_index.ud);
i965/fs: Implement FS_OPCODE_GET_BUFFER_SIZE Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com> Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2015-04-13 15:55:49 +01:00
}
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
void
i965/fs/Gen4-7: Pass sampler_index to generate_tex Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-08-03 10:23:31 +01:00
fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
i965/fs: Separate the sampler from the surface in generate_tex Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-11-02 23:24:05 +00:00
struct brw_reg surface_index,
i965/fs/Gen4-7: Pass sampler_index to generate_tex Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-08-03 10:23:31 +01:00
struct brw_reg sampler_index)
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
{
int msg_type = -1;
i965/fs: Use the instruction execution size directly for texture generation Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-30 01:22:57 +01:00
uint32_t simd_mode;
i965/gen4: Fix sampling from integer textures. On original gen4, the surface format didn't determine the return data type from sampling like it does on g45 and later. Fixes GL_EXT_texture_integer/texture_integer_glsl130 Reviewed-by: Paul Berry <stereotype441@gmail.com>
2011-11-10 00:07:57 +00:00
uint32_t return_format;
i965/fs: Combine tex/fb_write operations (opt) Certain platforms support the ability to sample from a texture, and write it out to the file RT - thus saving a costly send instructions (note that this is a potnential win if one wanted to backport to a tag that didn't have the patch from Topi which removed excess MOVs from LOAD_PAYLOAD - 97caf5fa04dbd2), v2: Modify the algorithm. Instead of iterating in reverse through blocks and insts, since the last block/inst is the only thing which can benefit. Rebased on top of Ken's patching modifying is_last_send v3: Rebased over almost 2 months, and Incorporated feedback from Matt: Some comment typo fixes and rewordings. Whitespace Move the optimization pass outside of the optimize loop v4: Some cosmetic changes requested from Ken. These changes ensured that the optimization function always returned true when an optimization occurred, and false when one did not. This behavior did not exist with the original patch. As a result, having the separate helper function which Matt did not like no longer made sense, and so now I believe everyone should be happy. Benchmark (n=20) %diff *OglBatch5 -1.4 *OglBatch7 -1.79 OglFillTexMulti 5.57 OglFillTexSingle 1.16 OglShMapPcf 0.05 OglTexFilterAniso 3.01 OglTexFilterTri 1.94 No piglit regressions: (http://otc-gfxtest-01.jf.intel.com:8080/view/dev/job/bwidawsk/112/) [*] I believe my measurements are incorrect for Batch5-7. If I add this new optimization, but never emit the new instruction I see similar results. v5: Remove declaration of combine_tex_header since v4 dropped that function (Ben) Remove check for impossible case of an empty block (Matt) Set dest earlier to avoid extra special-casing in generate_tex (Matt) Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-02-08 21:59:57 +00:00
bool is_combined_send = inst->eot;
i965/gen4: Fix sampling from integer textures. On original gen4, the surface format didn't determine the return data type from sampling like it does on g45 and later. Fixes GL_EXT_texture_integer/texture_integer_glsl130 Reviewed-by: Paul Berry <stereotype441@gmail.com>
2011-11-10 00:07:57 +00:00
switch (dst.type) {
case BRW_REGISTER_TYPE_D:
return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
break;
case BRW_REGISTER_TYPE_UD:
return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
break;
default:
return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
break;
}
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
i965/fs: Stomp the texture return type to UINT32 for resinfo messages Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-11-11 23:46:55 +00:00
/* Stomp the resinfo output type to UINT32. On gens 4-5, the output type
* is set as part of the message descriptor. On gen4, the PRM seems to
* allow UINT32 and FLOAT32 (i965 PRM, Vol. 4 Section 4.8.1.1), but on
* later gens UINT32 is required. Once you hit Sandy Bridge, the bit is
* gone from the message descriptor entirely and you just get UINT32 all
* the time regasrdless. Since we can really only do non-UINT32 on gen4,
* just stomp it to UINT32 all the time.
*/
if (inst->opcode == SHADER_OPCODE_TXS)
return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
i965/fs: Use the instruction execution size directly for texture generation Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-30 01:22:57 +01:00
switch (inst->exec_size) {
case 8:
simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
break;
case 16:
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
i965/fs: Use the instruction execution size directly for texture generation Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-30 01:22:57 +01:00
break;
default:
unreachable("Invalid width for texture instruction");
}
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
i965/fs: Add a devinfo field to the generator and use it for gen checks Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 01:45:40 +01:00
if (devinfo->gen >= 5) {
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
switch (inst->opcode) {
i965: Rename texturing ops from FS_OPCODE to SHADER_OPCODE, except TXB. We'll be reusing most of these for the VS shortly. The one exception is TXB (texturing with LOD bias), which is explicitly forbidden in the VS. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-10-26 20:58:37 +01:00
case SHADER_OPCODE_TEX:
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
if (inst->shadow_compare) {
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
} else {
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
}
break;
case FS_OPCODE_TXB:
if (inst->shadow_compare) {
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
} else {
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
}
break;
i965: Rename texturing ops from FS_OPCODE to SHADER_OPCODE, except TXB. We'll be reusing most of these for the VS shortly. The one exception is TXB (texturing with LOD bias), which is explicitly forbidden in the VS. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-10-26 20:58:37 +01:00
case SHADER_OPCODE_TXL:
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
if (inst->shadow_compare) {
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
} else {
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
}
break;
i965: Add infrastucture for sample lod-zero operations. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-05-04 23:46:45 +01:00
case SHADER_OPCODE_TXL_LZ:
assert(devinfo->gen >= 9);
if (inst->shadow_compare) {
msg_type = GEN9_SAMPLER_MESSAGE_SAMPLE_C_LZ;
} else {
msg_type = GEN9_SAMPLER_MESSAGE_SAMPLE_LZ;
}
break;
i965: Rename texturing ops from FS_OPCODE to SHADER_OPCODE, except TXB. We'll be reusing most of these for the VS shortly. The one exception is TXB (texturing with LOD bias), which is explicitly forbidden in the VS. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-10-26 20:58:37 +01:00
case SHADER_OPCODE_TXS:
i965/fs: Implement textureSize (TXS) on Gen5+. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2011-06-19 09:47:50 +01:00
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
break;
i965: Rename texturing ops from FS_OPCODE to SHADER_OPCODE, except TXB. We'll be reusing most of these for the VS shortly. The one exception is TXB (texturing with LOD bias), which is explicitly forbidden in the VS. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-10-26 20:58:37 +01:00
case SHADER_OPCODE_TXD:
i965: Use Haswell's sample_d_c for textureGrad with shadow samplers. The new hardware actually just supports this now. Reviewed-by: Eric Anholt <eric@anholt.net>
2013-01-04 15:53:09 +00:00
if (inst->shadow_compare) {
/* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
i965/fs: Add a devinfo field to the generator and use it for gen checks Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 01:45:40 +01:00
assert(devinfo->gen >= 8 || devinfo->is_haswell);
i965: Use Haswell's sample_d_c for textureGrad with shadow samplers. The new hardware actually just supports this now. Reviewed-by: Eric Anholt <eric@anholt.net>
2013-01-04 15:53:09 +00:00
msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
} else {
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
}
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
break;
i965: Rename texturing ops from FS_OPCODE to SHADER_OPCODE, except TXB. We'll be reusing most of these for the VS shortly. The one exception is TXB (texturing with LOD bias), which is explicitly forbidden in the VS. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-10-26 20:58:37 +01:00
case SHADER_OPCODE_TXF:
i965/fs: Implement texelFetch() on Ironlake and Sandybridge. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-08-26 01:13:37 +01:00
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
break;
i965: Add infrastucture for sample lod-zero operations. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-05-04 23:46:45 +01:00
case SHADER_OPCODE_TXF_LZ:
assert(devinfo->gen >= 9);
msg_type = GEN9_SAMPLER_MESSAGE_SAMPLE_LD_LZ;
break;
i965/fs/skl+: Use ld2dms_w instead of ld2dms In order to support 16x MSAA, skl+ has a wider version of ld2dms that takes two parameters for the MCS data. The MCS data retrieved from the ld_mcs instruction already returns 4 or 8 registers and is documented to return zeroes for the mcsh value when the sample count is less than 16. v2: Use get_lowered_simd_width to fall back to SIMD8 instructions when the message length would be too long in SIMD16. Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
2015-09-08 15:52:09 +01:00
case SHADER_OPCODE_TXF_CMS_W:
assert(devinfo->gen >= 9);
msg_type = GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W;
break;
i965: rename tex_ms to tex_cms Prepares for the introduction of non-compressed multi-sampled lookup used in the blorp programs. v2: now also taking into account gen8 Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-12-10 14:36:31 +00:00
case SHADER_OPCODE_TXF_CMS:
i965/fs: Add a devinfo field to the generator and use it for gen checks Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 01:45:40 +01:00
if (devinfo->gen >= 7)
i965: add a new virtual opcode: SHADER_OPCODE_TXF_MS This is very similar to the TXF opcode, but lowers to `ld2dms` rather than `ld` on Gen7. V4: - add SHADER_OPCODE_TXF_MS to is_tex() functions, so regalloc thinks it actually writes the correct number of registers. Otherwise in nontrivial shaders some of the registers tend to get clobbered, producing bad results. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-01-24 08:35:15 +00:00
msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
else
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
break;
i965/fs: introduce non-compressed equivalent of tex_cms v2: introduces 'SHADER_OPCODE_TXF_UMS' also for gen8 Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-12-10 14:38:15 +00:00
case SHADER_OPCODE_TXF_UMS:
i965/fs: Add a devinfo field to the generator and use it for gen checks Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 01:45:40 +01:00
assert(devinfo->gen >= 7);
i965/fs: introduce non-compressed equivalent of tex_cms v2: introduces 'SHADER_OPCODE_TXF_UMS' also for gen8 Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-12-10 14:38:15 +00:00
msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
break;
i965: Add shader opcode for sampling MCS surface Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Paul Berry <stereotype441@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-29 21:32:16 +00:00
case SHADER_OPCODE_TXF_MCS:
i965/fs: Add a devinfo field to the generator and use it for gen checks Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 01:45:40 +01:00
assert(devinfo->gen >= 7);
i965: Add shader opcode for sampling MCS surface Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Paul Berry <stereotype441@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-29 21:32:16 +00:00
msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
break;
i965/fs: Generate LOD sampler message from ir_lod. v2: Support Ironlake as well. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-06 22:47:01 +00:00
case SHADER_OPCODE_LOD:
msg_type = GEN5_SAMPLER_MESSAGE_LOD;
break;
i965: add SHADER_OPCODE_TG4 Adds the Gen7 message IDs, a new SHADER_OPCODE_TG4 pseudo-op, and low-level support for emitting it via generate_tex(). V3: Updated for changes in master. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-31 09:31:12 +01:00
case SHADER_OPCODE_TG4:
i965/fs: Add support for shadow comparitors with gather4 Note that gather4_po_c's parameters are too long for SIMD16. It might be worth emitting 2xSIMD8 messages in this case at some point. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-10-10 07:57:29 +01:00
if (inst->shadow_compare) {
i965/fs: Add a devinfo field to the generator and use it for gen checks Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 01:45:40 +01:00
assert(devinfo->gen >= 7);
i965/fs: Add support for shadow comparitors with gather4 Note that gather4_po_c's parameters are too long for SIMD16. It might be worth emitting 2xSIMD8 messages in this case at some point. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-10-10 07:57:29 +01:00
msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
} else {
i965/fs: Add a devinfo field to the generator and use it for gen checks Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 01:45:40 +01:00
assert(devinfo->gen >= 6);
i965/fs: Add support for shadow comparitors with gather4 Note that gather4_po_c's parameters are too long for SIMD16. It might be worth emitting 2xSIMD8 messages in this case at some point. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-10-10 07:57:29 +01:00
msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
}
i965: add SHADER_OPCODE_TG4 Adds the Gen7 message IDs, a new SHADER_OPCODE_TG4 pseudo-op, and low-level support for emitting it via generate_tex(). V3: Updated for changes in master. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-31 09:31:12 +01:00
break;
i965: Add SHADER_OPCODE_TG4_OFFSET for gather with nonconstant offsets. The generator code ends up clearer this way than if we had to sniff via the message length. Implemented via the gather4_po message in hardware, which is present in Gen7 and later. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-10-08 09:42:10 +01:00
case SHADER_OPCODE_TG4_OFFSET:
i965/fs: Add a devinfo field to the generator and use it for gen checks Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 01:45:40 +01:00
assert(devinfo->gen >= 7);
i965/fs: Add support for shadow comparitors with gather4 Note that gather4_po_c's parameters are too long for SIMD16. It might be worth emitting 2xSIMD8 messages in this case at some point. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-10-10 07:57:29 +01:00
if (inst->shadow_compare) {
msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
} else {
msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
}
i965: Add SHADER_OPCODE_TG4_OFFSET for gather with nonconstant offsets. The generator code ends up clearer this way than if we had to sniff via the message length. Implemented via the gather4_po message in hardware, which is present in Gen7 and later. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-10-08 09:42:10 +01:00
break;
i965: add support for textureSamples function Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> [v2: kayden-supplied code in fs_nir replacing need for logical opcode] Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-08-12 01:37:32 +01:00
case SHADER_OPCODE_SAMPLEINFO:
msg_type = GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO;
break;
i965: Create a shared enum for hardware and compiler-internal opcodes. This should make gdbing more pleasant, and it might be used in sharing part of the codegen between the VS and FS backends.
2011-05-03 18:55:50 +01:00
default:
i965: Use unreachable() instead of unconditional assert(). Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-06-29 22:54:01 +01:00
unreachable("not reached");
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
}
} else {
switch (inst->opcode) {
i965: Rename texturing ops from FS_OPCODE to SHADER_OPCODE, except TXB. We'll be reusing most of these for the VS shortly. The one exception is TXB (texturing with LOD bias), which is explicitly forbidden in the VS. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-10-26 20:58:37 +01:00
case SHADER_OPCODE_TEX:
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
/* Note that G45 and older determines shadow compare and dispatch width
* from message length for most messages.
*/
i965/fs: Use exec_size instead of dispatch_width to determine the message variant. dispatch_width is global for a single compilation and doesn't necessarily match the desired execution width if we had to lower the original full-width instruction due to hardware limitations. These were all inside a Gen4-specific branch so this patch shouldn't have any effect on more recent hardware. Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-07-13 13:42:20 +01:00
if (inst->exec_size == 8) {
i965: Implement SIMD16 texturing on Gen4. This allows SIMD16 mode to work for a lot more programs. Texturing is also more efficient in SIMD16 mode than SIMD8. Several messages don't actually exist in SIMD8 mode, so we did SIMD16 messages and threw away half of the data. Now we compute real data in both halves. Also, the SIMD16 "sample" message doesn't require all three coordinate components to exist (like the SIMD8 one), so we can shorten the message lengths, cutting register usage a bit. I chose to implement the visitor functionality in a separate function, since mixing true SIMD16 with SIMD8 code that uses SIMD16 fallbacks seemed like a mess. The new code bails on a few cases where we'd have to do two SIMD8 messages - we just fall back to SIMD8 for now. Improves performance in "Shadowrun: Dragonfall - Director's Cut" by about 20% on GM45 (measured with LIBGL_SHOW_FPS=1 while standing around in the first mission). v2: Add ir_txf to the has_lod case (caught by Jordan Justen). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2015-02-20 23:11:49 +00:00
msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
if (inst->shadow_compare) {
assert(inst->mlen == 6);
} else {
assert(inst->mlen <= 4);
}
} else {
if (inst->shadow_compare) {
msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE;
assert(inst->mlen == 9);
} else {
msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE;
assert(inst->mlen <= 7 && inst->mlen % 2 == 1);
}
}
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
break;
case FS_OPCODE_TXB:
if (inst->shadow_compare) {
i965/fs: Use exec_size instead of dispatch_width to determine the message variant. dispatch_width is global for a single compilation and doesn't necessarily match the desired execution width if we had to lower the original full-width instruction due to hardware limitations. These were all inside a Gen4-specific branch so this patch shouldn't have any effect on more recent hardware. Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-07-13 13:42:20 +01:00
assert(inst->exec_size == 8);
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
assert(inst->mlen == 6);
msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
} else {
assert(inst->mlen == 9);
msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
}
break;
i965: Rename texturing ops from FS_OPCODE to SHADER_OPCODE, except TXB. We'll be reusing most of these for the VS shortly. The one exception is TXB (texturing with LOD bias), which is explicitly forbidden in the VS. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-10-26 20:58:37 +01:00
case SHADER_OPCODE_TXL:
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
if (inst->shadow_compare) {
i965/fs: Use exec_size instead of dispatch_width to determine the message variant. dispatch_width is global for a single compilation and doesn't necessarily match the desired execution width if we had to lower the original full-width instruction due to hardware limitations. These were all inside a Gen4-specific branch so this patch shouldn't have any effect on more recent hardware. Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-07-13 13:42:20 +01:00
assert(inst->exec_size == 8);
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
assert(inst->mlen == 6);
msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
} else {
assert(inst->mlen == 9);
msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
}
break;
i965: Rename texturing ops from FS_OPCODE to SHADER_OPCODE, except TXB. We'll be reusing most of these for the VS shortly. The one exception is TXB (texturing with LOD bias), which is explicitly forbidden in the VS. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-10-26 20:58:37 +01:00
case SHADER_OPCODE_TXD:
i965/fs: Add support for TXD with shadow comparisons. Our hardware doesn't have a sample_d_c message, so we have to do a regular sample_d and emit instructions to manually perform the comparison. This requires a state dependent recompile whenever the sampler's compare mode or function change. This adds the per-sampler comparison functions to brw_wm_prog_key, but only sets them when the sampler's compare mode is GL_COMPARE_R_TO_TEXTURE (i.e. only for shadow sampling). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-06-10 22:48:46 +01:00
/* There is no sample_d_c message; comparisons are done manually */
i965/fs: Use exec_size instead of dispatch_width to determine the message variant. dispatch_width is global for a single compilation and doesn't necessarily match the desired execution width if we had to lower the original full-width instruction due to hardware limitations. These were all inside a Gen4-specific branch so this patch shouldn't have any effect on more recent hardware. Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-07-13 13:42:20 +01:00
assert(inst->exec_size == 8);
i965/fs: Add support for non-shadow textureGrad (TXD) on gen4. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-06-09 00:05:34 +01:00
assert(inst->mlen == 7 || inst->mlen == 10);
msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
break;
i965: Rename texturing ops from FS_OPCODE to SHADER_OPCODE, except TXB. We'll be reusing most of these for the VS shortly. The one exception is TXB (texturing with LOD bias), which is explicitly forbidden in the VS. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-10-26 20:58:37 +01:00
case SHADER_OPCODE_TXF:
i965: Implement SIMD16 texturing on Gen4. This allows SIMD16 mode to work for a lot more programs. Texturing is also more efficient in SIMD16 mode than SIMD8. Several messages don't actually exist in SIMD8 mode, so we did SIMD16 messages and threw away half of the data. Now we compute real data in both halves. Also, the SIMD16 "sample" message doesn't require all three coordinate components to exist (like the SIMD8 one), so we can shorten the message lengths, cutting register usage a bit. I chose to implement the visitor functionality in a separate function, since mixing true SIMD16 with SIMD8 code that uses SIMD16 fallbacks seemed like a mess. The new code bails on a few cases where we'd have to do two SIMD8 messages - we just fall back to SIMD8 for now. Improves performance in "Shadowrun: Dragonfall - Director's Cut" by about 20% on GM45 (measured with LIBGL_SHOW_FPS=1 while standing around in the first mission). v2: Add ir_txf to the has_lod case (caught by Jordan Justen). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2015-02-20 23:11:49 +00:00
assert(inst->mlen <= 9 && inst->mlen % 2 == 1);
i965/fs: Implement texelFetch() on Gen4. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-09-07 00:39:01 +01:00
msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
break;
i965: Rename texturing ops from FS_OPCODE to SHADER_OPCODE, except TXB. We'll be reusing most of these for the VS shortly. The one exception is TXB (texturing with LOD bias), which is explicitly forbidden in the VS. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-10-26 20:58:37 +01:00
case SHADER_OPCODE_TXS:
i965: Implement textureSize (TXS) on Gen4. Also, remove the BRW_SAMPLER_MESSAGE_SIMD8_RESINFO #define because there totally isn't a SIMD8 variant. Unfortunately, resinfo returns FLOAT32 on Broadwater/Crestline, unlike G45 which returns a proper UINT32. This turns out to be simple, however: when we emit MOVs to select the desired half of the SIMD16 result, we can simply override the register type to be float so it's converted to an integer. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2011-08-17 18:45:47 +01:00
assert(inst->mlen == 3);
msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO;
simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
break;
i965: Create a shared enum for hardware and compiler-internal opcodes. This should make gdbing more pleasant, and it might be used in sharing part of the codegen between the VS and FS backends.
2011-05-03 18:55:50 +01:00
default:
i965: Use unreachable() instead of unconditional assert(). Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-06-29 22:54:01 +01:00
unreachable("not reached");
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
}
}
assert(msg_type != -1);
if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
dst = vec16(dst);
}
i965: Change header_present to header_size in backend_instruction Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-03-24 17:17:32 +00:00
assert(devinfo->gen < 7 || inst->header_size == 0 ||
i965/fs_reg: Allocate double the number of vgrfs in SIMD16 mode This is actually the squash of a bunch of different changes. Individual commit titles follow: i965/fs: Always 2-align registers SIMD16 for gen <= 5 i965/fs: Use the register width when applying offsets This reworks both byte_offset() and offset() to be more intelligent. The byte_offset() function now supports offsets bigger than 32. The offset() function uses the byte_offset() function together with the register width and the type size to offset the register by the correct amount. i965/fs: Change regs_read to be in hardware registers i965/fs: Change regs_written to be actual hardware registers i965/fs: Properly handle register widths in LOAD_PAYLOAD The LOAD_PAYLOAD instruction is a bit special because it collects a bunch of registers (with possibly different widths) into a single payload block. Once the payload is constructed, it's treated as a single block of data and most of the information such as register widths doesn't matter anymore. In particular, the offset of any particular source register is the accumulation of the sizes of the previous source registers. i965/fs: Properly set writemasks in LOAD_PAYLOAD i965/fs: Handle register widths in demote_pull_constants i965/fs: Get rid of implicit register doubling in the allocator i965/fs: Reserve enough registers for PLN instructions i965/fs: Make sources and destinations interfere in 16-wide i965/fs: Properly handle register widths in CSE i965/fs: Properly handle register widths in register_coalesce i965/fs: Properly handle widths in copy propagation i965/fs: Properly handle register widths in VARYING_PULL_CONSTANT_LOAD i965/fs: Properly handle register widths and odd register sizes in spilling i965/fs: Don't waste a register on texture lookups for gen >= 7 Previously, we were waisting a register in SIMD16 mode because we could only allocate registers in pairs. Now that we can allocate and address odd-sized registers, let's get rid of this special-case. Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-18 22:27:55 +01:00
src.file == BRW_GENERAL_REGISTER_FILE);
i965/fs: Convert gen7 to using GRFs for texture messages. Looking at Lightsmark's shaders, the way we used MRFs (or in gen7's case, GRFs) was bad in a couple of ways. One was that it prevented compute-to-MRF for the common case of a texcoord that gets used exactly once, but where the texcoord setup all gets emitted before the texture calls (such as when it's a bare fragment shader input, which gets interpolated before processing main()). Another was that it introduced a bunch of dependencies that constrained scheduling, and forced waits for texture operations to be done before they are required. For example, we can now move the compute-to-MRF interpolation for the second texture send down after the first send. The downside is that this generally prevents remove_duplicate_mrf_writes() from doing anything, whereas previously it avoided work for the case of sampling from the same texcoord twice. However, I suspect that most of the win that originally justified that code was in avoiding the WAR stall on the first send, which this patch also avoids, rather than the small cost of the extra instruction. We see instruction count regressions in shaders in unigine, yofrankie, savage2, hon, and gstreamer. Improves GLB2.7 performance by 0.633628% +/- 0.491809% (n=121/125, avg of ~66fps, outliers below 61 dropped). Improves openarena performance by 1.01092% +/- 0.66897% (n=425). No significant difference on Lightsmark (n=44). v2: Squash in the fix for register unspilling for send-from-GRF, fixing a segfault in lightsmark. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Matt Turner <mattst88@gmail.com>
2013-10-10 01:17:59 +01:00
i965/fs/Gen4-7: Pass sampler_index to generate_tex Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-08-03 10:23:31 +01:00
assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
i965/fs: Move message header and texture offset setup to generate_tex(). Setting the texture offset bits in the message header involves very specific hardware register descriptions. As such, I feel it's better suited for the lower level "generate" layer that has direct access to the weird register layouts, rather than at the fs_inst abstraction layer. This also parallels the approach I took in the VS backend. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2012-08-05 04:33:13 +01:00
/* Load the message header if present. If there's a texture offset,
* we need to set it up explicitly and load the offset bitfield.
* Otherwise, we can use an implied move from g0 to the first message reg.
*/
i965: Change header_present to header_size in backend_instruction Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-03-24 17:17:32 +00:00
if (inst->header_size != 0) {
i965/fs: Add a devinfo field to the generator and use it for gen checks Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 01:45:40 +01:00
if (devinfo->gen < 6 && !inst->offset) {
i965/fs: Refactor sampler message header to duplicate less code. Previously, the code to copy g0 to the message header existed in two places - one for the texture offset case, and one for any other case. By treating texture_offset as a special case of header_present, we can remove this duplication and shorten the code. Future patches which add new header fields also won't have to add additional duplication. This also clarifies a confusing construct. The old code contained: } else if (inst->header_present) { if (brw->gen >= 7) { ...explicit copy from g0 to the message header... } else { /* Set up an implied move from g0 to the MRF. */ } } This looks like it might set up an implied move on Sandybridge, which doesn't support those. However, Sandybridge only uses a message header for texture offsets, so it would never hit this code path. The new code avoids this implicit knowledge by only setting up an implied move on Gen4-5. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-01-18 20:48:18 +00:00
/* Set up an implied move from g0 to the MRF. */
src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
i965/fs: Convert gen7 to using GRFs for texture messages. Looking at Lightsmark's shaders, the way we used MRFs (or in gen7's case, GRFs) was bad in a couple of ways. One was that it prevented compute-to-MRF for the common case of a texcoord that gets used exactly once, but where the texcoord setup all gets emitted before the texture calls (such as when it's a bare fragment shader input, which gets interpolated before processing main()). Another was that it introduced a bunch of dependencies that constrained scheduling, and forced waits for texture operations to be done before they are required. For example, we can now move the compute-to-MRF interpolation for the second texture send down after the first send. The downside is that this generally prevents remove_duplicate_mrf_writes() from doing anything, whereas previously it avoided work for the case of sampling from the same texcoord twice. However, I suspect that most of the win that originally justified that code was in avoiding the WAR stall on the first send, which this patch also avoids, rather than the small cost of the extra instruction. We see instruction count regressions in shaders in unigine, yofrankie, savage2, hon, and gstreamer. Improves GLB2.7 performance by 0.633628% +/- 0.491809% (n=121/125, avg of ~66fps, outliers below 61 dropped). Improves openarena performance by 1.01092% +/- 0.66897% (n=425). No significant difference on Lightsmark (n=44). v2: Squash in the fix for register unspilling for send-from-GRF, fixing a segfault in lightsmark. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Matt Turner <mattst88@gmail.com>
2013-10-10 01:17:59 +01:00
} else {
i965/fs: Refactor sampler message header to duplicate less code. Previously, the code to copy g0 to the message header existed in two places - one for the texture offset case, and one for any other case. By treating texture_offset as a special case of header_present, we can remove this duplication and shorten the code. Future patches which add new header fields also won't have to add additional duplication. This also clarifies a confusing construct. The old code contained: } else if (inst->header_present) { if (brw->gen >= 7) { ...explicit copy from g0 to the message header... } else { /* Set up an implied move from g0 to the MRF. */ } } This looks like it might set up an implied move on Sandybridge, which doesn't support those. However, Sandybridge only uses a message header for texture offsets, so it would never hit this code path. The new code avoids this implicit knowledge by only setting up an implied move on Gen4-5. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-01-18 20:48:18 +00:00
struct brw_reg header_reg;
i965/fs: Add a devinfo field to the generator and use it for gen checks Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 01:45:40 +01:00
if (devinfo->gen >= 7) {
i965/fs: Refactor sampler message header to duplicate less code. Previously, the code to copy g0 to the message header existed in two places - one for the texture offset case, and one for any other case. By treating texture_offset as a special case of header_present, we can remove this duplication and shorten the code. Future patches which add new header fields also won't have to add additional duplication. This also clarifies a confusing construct. The old code contained: } else if (inst->header_present) { if (brw->gen >= 7) { ...explicit copy from g0 to the message header... } else { /* Set up an implied move from g0 to the MRF. */ } } This looks like it might set up an implied move on Sandybridge, which doesn't support those. However, Sandybridge only uses a message header for texture offsets, so it would never hit this code path. The new code avoids this implicit knowledge by only setting up an implied move on Gen4-5. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-01-18 20:48:18 +00:00
header_reg = src;
} else {
assert(inst->base_mrf != -1);
header_reg = brw_message_reg(inst->base_mrf);
}
i965/fs: Fix handling of sampler messages with header but zero offset Gather unconditionally uses a header, but in some cases the texture_offset value will be zero. V2: Don't introduce a bogus conversion. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-10-13 00:20:03 +01:00
brw_push_insn_state(p);
i965: Replace guess_execution_size with something simpler. guess_execution_size() does two things: 1. Cope with small destination registers. 2. Cope with SIMD8 vs SIMD16 mode. This patch replaces the first with a simple if block in brw_set_dest: if the destination register width is less than 8, you probably want the execution size to match. (I didn't put this in the 3src block because it doesn't seem to matter.) Since only the FS compiler cares about SIMD16 mode, it's easy to just set the default execution size there. This pattern was already been proven in the Gen8+ generator, but we didn't port it back to the existing generator when we combined the two. This is based on a patch from Ken from about a year ago. I've rebased it and and fixed a few bugs. Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-04-14 20:40:34 +01:00
brw_set_default_exec_size(p, BRW_EXECUTE_8);
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
i965/fs: Refactor sampler message header to duplicate less code. Previously, the code to copy g0 to the message header existed in two places - one for the texture offset case, and one for any other case. By treating texture_offset as a special case of header_present, we can remove this duplication and shorten the code. Future patches which add new header fields also won't have to add additional duplication. This also clarifies a confusing construct. The old code contained: } else if (inst->header_present) { if (brw->gen >= 7) { ...explicit copy from g0 to the message header... } else { /* Set up an implied move from g0 to the MRF. */ } } This looks like it might set up an implied move on Sandybridge, which doesn't support those. However, Sandybridge only uses a message header for texture offsets, so it would never hit this code path. The new code avoids this implicit knowledge by only setting up an implied move on Gen4-5. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-01-18 20:48:18 +00:00
/* Explicitly set up the message header by copying g0 to the MRF. */
brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
i965: Combine offset/texture_offset fields. texture_offset was only used by some texturing operations, and offset was only used by spill/unspill and some URB operations. These fields are never used at the same time. Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-11-12 19:28:02 +00:00
if (inst->offset) {
i965/fs: Refactor sampler message header to duplicate less code. Previously, the code to copy g0 to the message header existed in two places - one for the texture offset case, and one for any other case. By treating texture_offset as a special case of header_present, we can remove this duplication and shorten the code. Future patches which add new header fields also won't have to add additional duplication. This also clarifies a confusing construct. The old code contained: } else if (inst->header_present) { if (brw->gen >= 7) { ...explicit copy from g0 to the message header... } else { /* Set up an implied move from g0 to the MRF. */ } } This looks like it might set up an implied move on Sandybridge, which doesn't support those. However, Sandybridge only uses a message header for texture offsets, so it would never hit this code path. The new code avoids this implicit knowledge by only setting up an implied move on Gen4-5. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-01-18 20:48:18 +00:00
/* Set the offset bits in DWord 2. */
brw_MOV(p, get_element_ud(header_reg, 2),
i965: Combine offset/texture_offset fields. texture_offset was only used by some texturing operations, and offset was only used by spill/unspill and some URB operations. These fields are never used at the same time. Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-11-12 19:28:02 +00:00
brw_imm_ud(inst->offset));
i965/fs: Always set channel 2 of texture headers in some stages In the vertex and fragment stages, the hardware is nice to us and leaves g0.2 zerod out for us so we can use it for headers. However, in compute, geometry, and tessellation stages, the hardware is not so nice. In particular, for compute shaders on BDW, the hardware places some debug bits in 23:15. As it happens, bit 15 is interpreted by the sampler as the alpha channel mask. This means that if you use a texturing instruction with a header in a compute shader, you may randomly get the alpha channel disabled. Since channel masks affect the return length of the sampler message, this can lead the GPU to expect a different mlen to the one you specified in the shader and this, in turn, hangs your GPU. Cc: "11.1" <mesa-stable@lists.freedesktop.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2016-01-15 04:42:47 +00:00
} else if (stage != MESA_SHADER_VERTEX &&
stage != MESA_SHADER_FRAGMENT) {
/* The vertex and fragment stages have g0.2 set to 0, so
* header0.2 is 0 when g0 is copied. Other stages may not, so we
* must set it to 0 to avoid setting undesirable bits in the
* message.
*/
brw_MOV(p, get_element_ud(header_reg, 2), brw_imm_ud(0));
i965/fs: Refactor sampler message header to duplicate less code. Previously, the code to copy g0 to the message header existed in two places - one for the texture offset case, and one for any other case. By treating texture_offset as a special case of header_present, we can remove this duplication and shorten the code. Future patches which add new header fields also won't have to add additional duplication. This also clarifies a confusing construct. The old code contained: } else if (inst->header_present) { if (brw->gen >= 7) { ...explicit copy from g0 to the message header... } else { /* Set up an implied move from g0 to the MRF. */ } } This looks like it might set up an implied move on Sandybridge, which doesn't support those. However, Sandybridge only uses a message header for texture offsets, so it would never hit this code path. The new code avoids this implicit knowledge by only setting up an implied move on Gen4-5. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-01-18 20:48:18 +00:00
}
i965/fs: Support arbitrarily large sampler state indices on Haswell+. The message descriptor's "Sampler Index" field is only 4 bits (on all generations of hardware), so it can only represent indices 0 through 15. Haswell introduced a new field in the message header - "Sampler State Pointer". Normally, this is copied straight from g0, but we can also add a byte offset (as long as it's a multiple of 32). This patch uses a "Sampler State Pointer" offset to select a group of 16 sampler states, and then uses the "Sampler Index" field to select the state within that group. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-01-18 21:29:39 +00:00
i965/emit: Do the sampler index adjustment directly in header.0.3 Prior to this commit, the adjust_sampler_state_pointer function took an extra register that it could use as scratch space. The usual candidate was the destination of the sampler instruction. However, if that register ever aliased anything important such as the sampler index, this would scratch all over important data. Fortunately, the calculation is such that we can just do it in place and we don't need the scratch space at all. Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2015-01-22 21:46:44 +00:00
brw_adjust_sampler_state_pointer(p, header_reg, sampler_index);
i965/fs: Fix handling of sampler messages with header but zero offset Gather unconditionally uses a header, but in some cases the texture_offset value will be zero. V2: Don't introduce a bogus conversion. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-10-13 00:20:03 +01:00
brw_pop_insn_state(p);
}
i965/fs: Move message header and texture offset setup to generate_tex(). Setting the texture offset bits in the message header involves very specific hardware register descriptions. As such, I feel it's better suited for the lower level "generate" layer that has direct access to the weird register layouts, rather than at the fs_inst abstraction layer. This also parallels the approach I took in the VS backend. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2012-08-05 04:33:13 +01:00
}
i965/fs: Refactor generate_tex in prep for nonconst sampler indexing Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-10 00:58:06 +01:00
uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
inst->opcode == SHADER_OPCODE_TG4_OFFSET)
i965/fs: Remove direct fs_generator brw_wm_prog_data dependence Instead we store a brw_stage_prog_data pointer, and cast it to brw_wm_prog_data for fragment shader specific code paths. Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-29 20:50:46 +01:00
? prog_data->binding_table.gather_texture_start
: prog_data->binding_table.texture_start;
i965/fs: Refactor generate_tex in prep for nonconst sampler indexing Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-10 00:58:06 +01:00
i965/fs: Separate the sampler from the surface in generate_tex Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-11-02 23:24:05 +00:00
if (surface_index.file == BRW_IMMEDIATE_VALUE &&
sampler_index.file == BRW_IMMEDIATE_VALUE) {
uint32_t surface = surface_index.ud;
i965: Make 'dw1' and 'bits' unnamed structures in brw_reg. Generated by sed -i -e 's/\.bits\././g' *.c *.h *.cpp sed -i -e 's/dw1\.//g' *.c *.h *.cpp and then reverting changes to comments in gen7_blorp.cpp and brw_fs_generator.cpp. There wasn't any utility offered by forcing the programmer to list these to access their fields. Removing them will reduce churn in future commits. This is C11 (and gcc has apparently supported it for sometime "compatibility with other compilers") See https://gcc.gnu.org/onlinedocs/gcc/Unnamed-Fields.html Reviewed-by: Emil Velikov <emil.velikov@collabora.co.uk> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-10-23 03:41:30 +01:00
uint32_t sampler = sampler_index.ud;
i965/fs: Refactor generate_tex in prep for nonconst sampler indexing Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-10 00:58:06 +01:00
brw_SAMPLE(p,
retype(dst, BRW_REGISTER_TYPE_UW),
inst->base_mrf,
src,
i965/fs: Separate the sampler from the surface in generate_tex Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-11-02 23:24:05 +00:00
surface + base_binding_table_index,
i965/fs: Refactor generate_tex in prep for nonconst sampler indexing Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-10 00:58:06 +01:00
sampler % 16,
msg_type,
i965/fs: Use inst->regs_written for rlen for texture instructions Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2015-10-09 19:24:35 +01:00
inst->regs_written,
i965/fs: Refactor generate_tex in prep for nonconst sampler indexing Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-10 00:58:06 +01:00
inst->mlen,
i965: Change header_present to header_size in backend_instruction Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-03-24 17:17:32 +00:00
inst->header_size != 0,
i965/fs: Refactor generate_tex in prep for nonconst sampler indexing Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-10 00:58:06 +01:00
simd_mode,
return_format);
i965/fs: Separate the sampler from the surface in generate_tex Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-11-02 23:24:05 +00:00
brw_mark_surface_used(prog_data, surface + base_binding_table_index);
i965/fs: Refactor generate_tex in prep for nonconst sampler indexing Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-10 00:58:06 +01:00
} else {
i965/fs: Add support for non-const sampler indices in generator Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-10 01:02:22 +01:00
/* Non-const sampler index */
struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
i965/fs: Separate the sampler from the surface in generate_tex Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-11-02 23:24:05 +00:00
struct brw_reg surface_reg = vec1(retype(surface_index, BRW_REGISTER_TYPE_UD));
i965/fs: Add support for non-const sampler indices in generator Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-10 01:02:22 +01:00
struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
brw_push_insn_state(p);
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
brw_set_default_access_mode(p, BRW_ALIGN_1);
i965: Fix undefined df bits in brw_reg comparisons. Commit 5310bca024f77da40ea6f4c275455f9cb0528f9e added a new "double df" field to the brw_reg struct, adding an extra 4 bytes of data that isn't usually initialized (or may contain irrelevant garbage if the struct is mutated). This means that it's no longer safe to memcmp(). Instead, add a brw_regs_equal() function which ignores the extra df bits unless they matter. To keep the implementation cheap, we wrap the first set of fields in a union/struct so that we can use a single DWord comparison. v2: Drop unnecessary casts (caught by Francisco Jerez). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Francisco Jerez <currojerez@riseup.net> Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
2016-05-14 00:41:13 +01:00
if (brw_regs_equal(&surface_reg, &sampler_reg)) {
i965/fs: Separate the sampler from the surface in generate_tex Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-11-02 23:24:05 +00:00
brw_MUL(p, addr, sampler_reg, brw_imm_uw(0x101));
} else {
brw_SHL(p, addr, sampler_reg, brw_imm_ud(8));
brw_OR(p, addr, addr, surface_reg);
}
i965: Don't add base_binding_table_index if it's zero When calculating the binding table index for non-constant sampler array indexing it needs to add the base binding table index which is a constant within the generated code. Often this base is zero so we can avoid a redundant instruction in that case. It looks like nothing in shader-db is doing non-constant sampler array indexing so this patch doesn't make any difference but it might be worth having anyway. Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Ben Widawsky <ben@bwidawsk.net>
2015-05-29 13:41:48 +01:00
if (base_binding_table_index)
brw_ADD(p, addr, addr, brw_imm_ud(base_binding_table_index));
i965: Don't use a temporary when generating an indirect sample Previously when generating the send instruction for a sample instruction with an indirect sampler it would use the destination register as a temporary store. This breaks when used in combination with the opt_sampler_eot optimisation because that forces the destination to be null. This patch fixes that by avoiding the temp register altogether. The reason the temporary register was needed was because it was trying to ensure the binding table index doesn't overflow a byte by and'ing it with 0xff. The result is then or'd with samper_index<<8. This patch instead just and's the whole thing by 0xfff. This will ensure that a bogus sampler index won't overflow into the rest of the message descriptor but unlike the previous code it won't ensure that the binding table index doesn't overflow into the sampler index. It doesn't seem like that should matter very much though because if the shader is generating a bogus sampler index then it's going to just get garbage out either way. Instead of doing sampler_index<<8|(sampler_index+base_table_index) the new code avoids one operation by doing sampler_index*0x101+base_table_index which should be equivalent. However if we wanted to avoid the multiply for some reason we could do this by adding an extra or instruction still without needing the temporary register. This fixes a number of Piglit tests on Skylake that were using indirect samplers such as: spec@arb_gpu_shader5@execution@sampler_array_indexing@fs-simple Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Ben Widawsky <ben@bwidawsk.net> Tested-by: Anuj Phogat <anuj.phogat@gmail.com>
2015-05-28 15:27:31 +01:00
brw_AND(p, addr, addr, brw_imm_ud(0xfff));
i965/fs: Add support for non-const sampler indices in generator Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-10 01:02:22 +01:00
i965: Don't disable exec masking for sampler message sends. This was telling the sampler to do texture fetches for *all* channels in the non-constant surface index case, what could have reduced throughput unnecessarily when some of the channels were disabled by control flow. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2015-02-26 15:24:03 +00:00
brw_pop_insn_state(p);
i965: Factor out logic to build a send message instruction with indirect descriptor. This is going to be useful because the Gen7+ uniform and varying pull constant, texturing, typed and untyped surface read, write, and atomic generation code on the vec4 and fs back-end all require the same logic to handle conditionally indirect surface indices. In pseudocode: | if (surface.file == BRW_IMMEDIATE_VALUE) { | inst = brw_SEND(p, dst, payload); | set_descriptor_control_bits(inst, surface, ...); | } else { | inst = brw_OR(p, addr, surface, 0); | set_descriptor_control_bits(inst, ...); | inst = brw_SEND(p, dst, payload); | set_indirect_send_descriptor(inst, addr); | } This patch abstracts out this frequently recurring pattern so we can now write: | inst = brw_send_indirect_message(p, sfid, dst, payload, surface) | set_descriptor_control_bits(inst, ...); without worrying about handling the immediate and indirect surface index cases explicitly. v2: Rebase. Improve documentatation and commit message. (Topi) Preserve UW destination type cargo-cult. (Topi, Ken, Matt) Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2015-03-19 13:44:24 +00:00
/* dst = send(offset, a0.0 | <descriptor>) */
brw_inst *insn = brw_send_indirect_message(
p, BRW_SFID_SAMPLER, dst, src, addr);
brw_set_sampler_message(p, insn,
i965/fs: Add support for non-const sampler indices in generator Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-10 01:02:22 +01:00
0 /* surface */,
0 /* sampler */,
msg_type,
i965/fs: Use inst->regs_written for rlen for texture instructions Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2015-10-09 19:24:35 +01:00
inst->regs_written,
i965/fs: Add support for non-const sampler indices in generator Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-10 01:02:22 +01:00
inst->mlen /* mlen */,
i965: Change header_present to header_size in backend_instruction Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-03-24 17:17:32 +00:00
inst->header_size != 0 /* header */,
i965/fs: Add support for non-const sampler indices in generator Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-10 01:02:22 +01:00
simd_mode,
return_format);
/* visitor knows more than we do about the surface limit required,
* so has already done marking.
*/
i965/fs: Refactor generate_tex in prep for nonconst sampler indexing Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-10 00:58:06 +01:00
}
i965/fs: Combine tex/fb_write operations (opt) Certain platforms support the ability to sample from a texture, and write it out to the file RT - thus saving a costly send instructions (note that this is a potnential win if one wanted to backport to a tag that didn't have the patch from Topi which removed excess MOVs from LOAD_PAYLOAD - 97caf5fa04dbd2), v2: Modify the algorithm. Instead of iterating in reverse through blocks and insts, since the last block/inst is the only thing which can benefit. Rebased on top of Ken's patching modifying is_last_send v3: Rebased over almost 2 months, and Incorporated feedback from Matt: Some comment typo fixes and rewordings. Whitespace Move the optimization pass outside of the optimize loop v4: Some cosmetic changes requested from Ken. These changes ensured that the optimization function always returned true when an optimization occurred, and false when one did not. This behavior did not exist with the original patch. As a result, having the separate helper function which Matt did not like no longer made sense, and so now I believe everyone should be happy. Benchmark (n=20) %diff *OglBatch5 -1.4 *OglBatch7 -1.79 OglFillTexMulti 5.57 OglFillTexSingle 1.16 OglShMapPcf 0.05 OglTexFilterAniso 3.01 OglTexFilterTri 1.94 No piglit regressions: (http://otc-gfxtest-01.jf.intel.com:8080/view/dev/job/bwidawsk/112/) [*] I believe my measurements are incorrect for Batch5-7. If I add this new optimization, but never emit the new instruction I see similar results. v5: Remove declaration of combine_tex_header since v4 dropped that function (Ben) Remove check for impossible case of an empty block (Matt) Set dest earlier to avoid extra special-casing in generate_tex (Matt) Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-02-08 21:59:57 +00:00
if (is_combined_send) {
i965: Make the brw_inst helpers take a device_info instead of a context Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 02:00:06 +01:00
brw_inst_set_eot(p->devinfo, brw_last_inst, true);
brw_inst_set_opcode(p->devinfo, brw_last_inst, BRW_OPCODE_SENDC);
i965/fs: Combine tex/fb_write operations (opt) Certain platforms support the ability to sample from a texture, and write it out to the file RT - thus saving a costly send instructions (note that this is a potnential win if one wanted to backport to a tag that didn't have the patch from Topi which removed excess MOVs from LOAD_PAYLOAD - 97caf5fa04dbd2), v2: Modify the algorithm. Instead of iterating in reverse through blocks and insts, since the last block/inst is the only thing which can benefit. Rebased on top of Ken's patching modifying is_last_send v3: Rebased over almost 2 months, and Incorporated feedback from Matt: Some comment typo fixes and rewordings. Whitespace Move the optimization pass outside of the optimize loop v4: Some cosmetic changes requested from Ken. These changes ensured that the optimization function always returned true when an optimization occurred, and false when one did not. This behavior did not exist with the original patch. As a result, having the separate helper function which Matt did not like no longer made sense, and so now I believe everyone should be happy. Benchmark (n=20) %diff *OglBatch5 -1.4 *OglBatch7 -1.79 OglFillTexMulti 5.57 OglFillTexSingle 1.16 OglShMapPcf 0.05 OglTexFilterAniso 3.01 OglTexFilterTri 1.94 No piglit regressions: (http://otc-gfxtest-01.jf.intel.com:8080/view/dev/job/bwidawsk/112/) [*] I believe my measurements are incorrect for Batch5-7. If I add this new optimization, but never emit the new instruction I see similar results. v5: Remove declaration of combine_tex_header since v4 dropped that function (Ben) Remove check for impossible case of an empty block (Matt) Set dest earlier to avoid extra special-casing in generate_tex (Matt) Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-02-08 21:59:57 +00:00
}
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
}
/* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
* looking like:
*
* arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
*
i965: compute DDX in a subspan based only on top row Consider only the top-left and top-right pixels to approximate DDX in a 2x2 subspan, unless the application requests a more accurate approximation via GL_FRAGMENT_SHADER_DERIVATIVE_HINT or this optimization is disabled from the new driconf option disable_derivative_optimization. This results in a less accurate approximation. However, it improves the performance of Xonotic with Ultra settings by 24.3879% +/- 0.832202% (at 95.0% confidence) on Haswell. No noticeable image quality difference observed. The improvement comes from faster sample_d. It seems, on Haswell, some optimizations are introduced to allow faster sample_d when all pixels in a subspan have the same derivative. I considered SAMPLE_STATE too, which allows one to control the quality of sample_d on Haswell. But it gave much worse image quality without giving better performance comparing to this change. No piglit quick.tests regression on Haswell (tested with v1). v2: better guess for precompile program key Signed-off-by: Chia-I Wu <olv@lunarg.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2013-09-12 06:00:52 +01:00
* Ideally, we want to produce:
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
*
* DDX DDY
* dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
* (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
* (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
* (ss0.br - ss0.bl) (ss0.tr - ss0.br)
* (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
* (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
* (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
* (ss1.br - ss1.bl) (ss1.tr - ss1.br)
*
* and add another set of two more subspans if in 16-pixel dispatch mode.
*
* For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
* for each pair, and vertstride = 2 jumps us 2 elements after processing a
i965: compute DDX in a subspan based only on top row Consider only the top-left and top-right pixels to approximate DDX in a 2x2 subspan, unless the application requests a more accurate approximation via GL_FRAGMENT_SHADER_DERIVATIVE_HINT or this optimization is disabled from the new driconf option disable_derivative_optimization. This results in a less accurate approximation. However, it improves the performance of Xonotic with Ultra settings by 24.3879% +/- 0.832202% (at 95.0% confidence) on Haswell. No noticeable image quality difference observed. The improvement comes from faster sample_d. It seems, on Haswell, some optimizations are introduced to allow faster sample_d when all pixels in a subspan have the same derivative. I considered SAMPLE_STATE too, which allows one to control the quality of sample_d on Haswell. But it gave much worse image quality without giving better performance comparing to this change. No piglit quick.tests regression on Haswell (tested with v1). v2: better guess for precompile program key Signed-off-by: Chia-I Wu <olv@lunarg.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2013-09-12 06:00:52 +01:00
* pair. But the ideal approximation may impose a huge performance cost on
* sample_d. On at least Haswell, sample_d instruction does some
* optimizations if the same LOD is used for all pixels in the subspan.
*
i965/fs: Improve accuracy of dFdy() to match dFdx(). Previously, we computed dFdy() using the following instruction: add(8) dst<1>F src<4,4,0)F -src.2<4,4,0>F { align1 1Q } That had the disadvantage that it computed the same value for all 4 pixels of a 2x2 subspan, which meant that it was less accurate than dFdx(). This patch changes it to the following instruction when c->key.high_quality_derivatives is set: add(8) dst<1>F src<4,4,1>.xyxyF -src<4,4,1>.zwzwF { align16 1Q } This gives it comparable accuracy to dFdx(). Unfortunately, align16 instructions can't be compressed, so in SIMD16 shaders, instead of emitting this instruction: add(16) dst<1>F src<4,4,1>.xyxyF -src<4,4,1>.zwzwF { align16 1H } We need to unroll to two instructions: add(8) dst<1>F src<4,4,1>.xyxyF -src<4,4,1>.zwzwF { align16 1Q } add(8) (dst+1)<1>F (src+1)<4,4,1>.xyxyF -(src+1)<4,4,1>.zwzwF { align16 2Q } Fixes piglit test spec/glsl-1.10/execution/fs-dfdy-accuracy. Acked-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-09-20 17:04:31 +01:00
* For DDY, we need to use ALIGN16 mode since it's capable of doing the
* appropriate swizzling.
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
*/
void
i965/fs: Handle derivative quality decisions in the front-end. Kristian noted that there's very little use of brw_wm_prog_key in the generator, and that it basically just generates what it's told, without caring about what stage it's handling. One exception to this is derivative handling. When handling dFdxCoarse and dFdxFine, we packed an enum value in a second source register, explicitly telling the generator what to do. For dFdx, we specified an enum value of "please use the hint", then checked the program key in the generator level code. A natural method is to define separate FS_OPCODE_DD[XY]_{COARSE,FINE} opcodes, and have the front-end (which already decides what IR to generate based on the program key) decide which dPdx/dPdy should correspond to. This consolidates the decision making in one place. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-11-08 09:39:14 +00:00
fs_generator::generate_ddx(enum opcode opcode,
struct brw_reg dst, struct brw_reg src)
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
{
i965: compute DDX in a subspan based only on top row Consider only the top-left and top-right pixels to approximate DDX in a 2x2 subspan, unless the application requests a more accurate approximation via GL_FRAGMENT_SHADER_DERIVATIVE_HINT or this optimization is disabled from the new driconf option disable_derivative_optimization. This results in a less accurate approximation. However, it improves the performance of Xonotic with Ultra settings by 24.3879% +/- 0.832202% (at 95.0% confidence) on Haswell. No noticeable image quality difference observed. The improvement comes from faster sample_d. It seems, on Haswell, some optimizations are introduced to allow faster sample_d when all pixels in a subspan have the same derivative. I considered SAMPLE_STATE too, which allows one to control the quality of sample_d on Haswell. But it gave much worse image quality without giving better performance comparing to this change. No piglit quick.tests regression on Haswell (tested with v1). v2: better guess for precompile program key Signed-off-by: Chia-I Wu <olv@lunarg.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2013-09-12 06:00:52 +01:00
unsigned vstride, width;
i965/fs: Handle derivative quality decisions in the front-end. Kristian noted that there's very little use of brw_wm_prog_key in the generator, and that it basically just generates what it's told, without caring about what stage it's handling. One exception to this is derivative handling. When handling dFdxCoarse and dFdxFine, we packed an enum value in a second source register, explicitly telling the generator what to do. For dFdx, we specified an enum value of "please use the hint", then checked the program key in the generator level code. A natural method is to define separate FS_OPCODE_DD[XY]_{COARSE,FINE} opcodes, and have the front-end (which already decides what IR to generate based on the program key) decide which dPdx/dPdy should correspond to. This consolidates the decision making in one place. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-11-08 09:39:14 +00:00
if (opcode == FS_OPCODE_DDX_FINE) {
i965: compute DDX in a subspan based only on top row Consider only the top-left and top-right pixels to approximate DDX in a 2x2 subspan, unless the application requests a more accurate approximation via GL_FRAGMENT_SHADER_DERIVATIVE_HINT or this optimization is disabled from the new driconf option disable_derivative_optimization. This results in a less accurate approximation. However, it improves the performance of Xonotic with Ultra settings by 24.3879% +/- 0.832202% (at 95.0% confidence) on Haswell. No noticeable image quality difference observed. The improvement comes from faster sample_d. It seems, on Haswell, some optimizations are introduced to allow faster sample_d when all pixels in a subspan have the same derivative. I considered SAMPLE_STATE too, which allows one to control the quality of sample_d on Haswell. But it gave much worse image quality without giving better performance comparing to this change. No piglit quick.tests regression on Haswell (tested with v1). v2: better guess for precompile program key Signed-off-by: Chia-I Wu <olv@lunarg.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2013-09-12 06:00:52 +01:00
/* produce accurate derivatives */
vstride = BRW_VERTICAL_STRIDE_2;
width = BRW_WIDTH_2;
i965/fs: Handle derivative quality decisions in the front-end. Kristian noted that there's very little use of brw_wm_prog_key in the generator, and that it basically just generates what it's told, without caring about what stage it's handling. One exception to this is derivative handling. When handling dFdxCoarse and dFdxFine, we packed an enum value in a second source register, explicitly telling the generator what to do. For dFdx, we specified an enum value of "please use the hint", then checked the program key in the generator level code. A natural method is to define separate FS_OPCODE_DD[XY]_{COARSE,FINE} opcodes, and have the front-end (which already decides what IR to generate based on the program key) decide which dPdx/dPdy should correspond to. This consolidates the decision making in one place. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-11-08 09:39:14 +00:00
} else {
i965: compute DDX in a subspan based only on top row Consider only the top-left and top-right pixels to approximate DDX in a 2x2 subspan, unless the application requests a more accurate approximation via GL_FRAGMENT_SHADER_DERIVATIVE_HINT or this optimization is disabled from the new driconf option disable_derivative_optimization. This results in a less accurate approximation. However, it improves the performance of Xonotic with Ultra settings by 24.3879% +/- 0.832202% (at 95.0% confidence) on Haswell. No noticeable image quality difference observed. The improvement comes from faster sample_d. It seems, on Haswell, some optimizations are introduced to allow faster sample_d when all pixels in a subspan have the same derivative. I considered SAMPLE_STATE too, which allows one to control the quality of sample_d on Haswell. But it gave much worse image quality without giving better performance comparing to this change. No piglit quick.tests regression on Haswell (tested with v1). v2: better guess for precompile program key Signed-off-by: Chia-I Wu <olv@lunarg.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2013-09-12 06:00:52 +01:00
/* replicate the derivative at the top-left pixel to other pixels */
vstride = BRW_VERTICAL_STRIDE_4;
width = BRW_WIDTH_4;
}
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
i965/brw_reg: struct constructor now needs explicit negate and abs values. We were assuming, when constructing a new brw_reg struct, that the negate and abs register modifiers would not be present by default in the new register. Now, we force explicitly setting these values when constructing a new register. This will avoid problems like forgetting to properly set them when we are using a previous register to generate this new register, as it was happening in the dFdx and dFdy generation functions. Fixes piglit test shaders/glsl-deriv-varyings Cc: "10.4 10.3" <mesa-stable@lists.freedesktop.org> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82991 Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-12-12 16:19:07 +00:00
src.negate, src.abs,
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
BRW_REGISTER_TYPE_F,
i965: compute DDX in a subspan based only on top row Consider only the top-left and top-right pixels to approximate DDX in a 2x2 subspan, unless the application requests a more accurate approximation via GL_FRAGMENT_SHADER_DERIVATIVE_HINT or this optimization is disabled from the new driconf option disable_derivative_optimization. This results in a less accurate approximation. However, it improves the performance of Xonotic with Ultra settings by 24.3879% +/- 0.832202% (at 95.0% confidence) on Haswell. No noticeable image quality difference observed. The improvement comes from faster sample_d. It seems, on Haswell, some optimizations are introduced to allow faster sample_d when all pixels in a subspan have the same derivative. I considered SAMPLE_STATE too, which allows one to control the quality of sample_d on Haswell. But it gave much worse image quality without giving better performance comparing to this change. No piglit quick.tests regression on Haswell (tested with v1). v2: better guess for precompile program key Signed-off-by: Chia-I Wu <olv@lunarg.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2013-09-12 06:00:52 +01:00
vstride,
width,
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
BRW_HORIZONTAL_STRIDE_0,
BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
i965/brw_reg: struct constructor now needs explicit negate and abs values. We were assuming, when constructing a new brw_reg struct, that the negate and abs register modifiers would not be present by default in the new register. Now, we force explicitly setting these values when constructing a new register. This will avoid problems like forgetting to properly set them when we are using a previous register to generate this new register, as it was happening in the dFdx and dFdy generation functions. Fixes piglit test shaders/glsl-deriv-varyings Cc: "10.4 10.3" <mesa-stable@lists.freedesktop.org> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82991 Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-12-12 16:19:07 +00:00
src.negate, src.abs,
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
BRW_REGISTER_TYPE_F,
i965: compute DDX in a subspan based only on top row Consider only the top-left and top-right pixels to approximate DDX in a 2x2 subspan, unless the application requests a more accurate approximation via GL_FRAGMENT_SHADER_DERIVATIVE_HINT or this optimization is disabled from the new driconf option disable_derivative_optimization. This results in a less accurate approximation. However, it improves the performance of Xonotic with Ultra settings by 24.3879% +/- 0.832202% (at 95.0% confidence) on Haswell. No noticeable image quality difference observed. The improvement comes from faster sample_d. It seems, on Haswell, some optimizations are introduced to allow faster sample_d when all pixels in a subspan have the same derivative. I considered SAMPLE_STATE too, which allows one to control the quality of sample_d on Haswell. But it gave much worse image quality without giving better performance comparing to this change. No piglit quick.tests regression on Haswell (tested with v1). v2: better guess for precompile program key Signed-off-by: Chia-I Wu <olv@lunarg.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2013-09-12 06:00:52 +01:00
vstride,
width,
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
BRW_HORIZONTAL_STRIDE_0,
BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
brw_ADD(p, dst, src0, negate(src1));
}
i965: Compute dFdy() correctly for FBOs. On i965, dFdx() and dFdy() are computed by taking advantage of the fact that each consecutive set of 4 pixels dispatched to the fragment shader always constitutes a contiguous 2x2 block of pixels in a fixed arrangement known as a "sub-span". So we calculate dFdx() by taking the difference between the values computed for the left and right halves of the sub-span, and we calculate dFdy() by taking the difference between the values computed for the top and bottom halves of the sub-span. However, there's a subtlety when FBOs are in use: since FBOs use a coordinate system where the origin is at the upper left, and window system framebuffers use a coordinate system where the origin is at the lower left, the computation of dFdy() needs to be negated for FBOs. This patch modifies the fragment shader back-ends to negate the value of dFdy() when an FBO is in use. It also modifies the code that populates the program key (brw_wm_populate_key() and brw_fs_precompile()) so that they always record in the program key whether we are rendering to an FBO or to a window system framebuffer; this ensures that the fragment shader will get recompiled when switching between FBO and non-FBO use. This will result in unnecessary recompiles of fragment shaders that don't use dFdy(). To fix that, we will need to adapt the GLSL and NV_fragment_program front-ends to record whether or not a given shader uses dFdy(). I plan to implement this in a future patch series; I've left FIXME comments in the code as a reminder. Fixes Piglit test "fbo-deriv". NOTE: This is a candidate for stable release branches. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-06-20 21:40:45 +01:00
/* The negate_value boolean is used to negate the derivative computation for
* FBOs, since they place the origin at the upper left instead of the lower
* left.
*/
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
void
i965/fs: Handle derivative quality decisions in the front-end. Kristian noted that there's very little use of brw_wm_prog_key in the generator, and that it basically just generates what it's told, without caring about what stage it's handling. One exception to this is derivative handling. When handling dFdxCoarse and dFdxFine, we packed an enum value in a second source register, explicitly telling the generator what to do. For dFdx, we specified an enum value of "please use the hint", then checked the program key in the generator level code. A natural method is to define separate FS_OPCODE_DD[XY]_{COARSE,FINE} opcodes, and have the front-end (which already decides what IR to generate based on the program key) decide which dPdx/dPdy should correspond to. This consolidates the decision making in one place. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-11-08 09:39:14 +00:00
fs_generator::generate_ddy(enum opcode opcode,
i965, anv: Use NIR FragCoord re-center and y-transform passes. This handles gl_FragCoord transformations and other window system vs. user FBO coordinate system flipping by multiplying/adding uniform values, rather than recompiles. This is much better because we have no decent way to guess whether the application is going to use a shader with the window system FBO or a user FBO, much less the drawable height. This led to a lot of recompiles in many applications. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-05-17 09:52:16 +01:00
struct brw_reg dst, struct brw_reg src)
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
{
i965/fs: Handle derivative quality decisions in the front-end. Kristian noted that there's very little use of brw_wm_prog_key in the generator, and that it basically just generates what it's told, without caring about what stage it's handling. One exception to this is derivative handling. When handling dFdxCoarse and dFdxFine, we packed an enum value in a second source register, explicitly telling the generator what to do. For dFdx, we specified an enum value of "please use the hint", then checked the program key in the generator level code. A natural method is to define separate FS_OPCODE_DD[XY]_{COARSE,FINE} opcodes, and have the front-end (which already decides what IR to generate based on the program key) decide which dPdx/dPdy should correspond to. This consolidates the decision making in one place. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-11-08 09:39:14 +00:00
if (opcode == FS_OPCODE_DDY_FINE) {
i965/fs: Only unroll high-accuracy dFdy() from SIMD16 to SIMD8 on gen4 and IVB. In commit 800610f (i965/fs: Improve accuracy of dFdy() to match dFdx()) I unrolled the high-accuracy dFdy() computation from a single SIMD16 instruction to two SIMD8 instructions because of text I found in the i965 (gen4) PRM saying that instruction compression could not be used in align16 mode. I couldn't find similar text in later hardware docs, and I observed problems trying to use instruction compression on align16 mode on Ivy Bridge, so I assumed that the restriction still applied and the associated documentation had simply been lost. After consultation with the hardware engineers, it turns out this is not the case. In point of fact, the restriction was dropped in gen5, re-introduced in Ivy Bridge, and dropped again in Haswell. The reason I didn't notice this is that in the Ivy Bridge documentation, the restriction was in a different section, and described using different language. Now that we know that the restriction only applies to Gen4 and Ivy Bridge, we can limit the unrolling to those platforms. Tested on gen5, gen6, and gen7 (both Ivy Bridge and Haswell). Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-10-22 13:56:37 +01:00
/* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
* Region Restrictions):
*
* In Align16 access mode, SIMD16 is not allowed for DW operations
* and SIMD8 is not allowed for DF operations.
*
* In this context, "DW operations" means "operations acting on 32-bit
* values", so it includes operations on floats.
*
* Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
* (Instruction Compression -> Rules and Restrictions):
*
* A compressed instruction must be in Align1 access mode. Align16
* mode instructions cannot be compressed.
*
* Similar text exists in the g45 PRM.
*
i965: Unroll SIMD16 DDY_FINE on Sandybridge. This fixes 10 dEQP-GLES3 subtests: dEQP-GLES3.functional.shaders.derivate.dfdy.texture.float_nicest.*. Matt noticed that our Piglit tests for this use even numbered registers, while the failing dEQP tests use odd numbered registers. We believe that it works for even numbered registers, but not otherwise. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-03-29 09:32:52 +01:00
* Empirically, compressed align16 instructions using odd register
* numbers don't appear to work on Sandybridge either.
*
i965/fs: Only unroll high-accuracy dFdy() from SIMD16 to SIMD8 on gen4 and IVB. In commit 800610f (i965/fs: Improve accuracy of dFdy() to match dFdx()) I unrolled the high-accuracy dFdy() computation from a single SIMD16 instruction to two SIMD8 instructions because of text I found in the i965 (gen4) PRM saying that instruction compression could not be used in align16 mode. I couldn't find similar text in later hardware docs, and I observed problems trying to use instruction compression on align16 mode on Ivy Bridge, so I assumed that the restriction still applied and the associated documentation had simply been lost. After consultation with the hardware engineers, it turns out this is not the case. In point of fact, the restriction was dropped in gen5, re-introduced in Ivy Bridge, and dropped again in Haswell. The reason I didn't notice this is that in the Ivy Bridge documentation, the restriction was in a different section, and described using different language. Now that we know that the restriction only applies to Gen4 and Ivy Bridge, we can limit the unrolling to those platforms. Tested on gen5, gen6, and gen7 (both Ivy Bridge and Haswell). Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-10-22 13:56:37 +01:00
* On these platforms, if we're building a SIMD16 shader, we need to
* manually unroll to a pair of SIMD8 instructions.
*/
bool unroll_to_simd8 =
(dispatch_width == 16 &&
i965: Unroll SIMD16 DDY_FINE on Sandybridge. This fixes 10 dEQP-GLES3 subtests: dEQP-GLES3.functional.shaders.derivate.dfdy.texture.float_nicest.*. Matt noticed that our Piglit tests for this use even numbered registers, while the failing dEQP tests use odd numbered registers. We believe that it works for even numbered registers, but not otherwise. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-03-29 09:32:52 +01:00
(devinfo->gen == 4 || devinfo->gen == 6 ||
(devinfo->gen == 7 && !devinfo->is_haswell)));
i965/fs: Only unroll high-accuracy dFdy() from SIMD16 to SIMD8 on gen4 and IVB. In commit 800610f (i965/fs: Improve accuracy of dFdy() to match dFdx()) I unrolled the high-accuracy dFdy() computation from a single SIMD16 instruction to two SIMD8 instructions because of text I found in the i965 (gen4) PRM saying that instruction compression could not be used in align16 mode. I couldn't find similar text in later hardware docs, and I observed problems trying to use instruction compression on align16 mode on Ivy Bridge, so I assumed that the restriction still applied and the associated documentation had simply been lost. After consultation with the hardware engineers, it turns out this is not the case. In point of fact, the restriction was dropped in gen5, re-introduced in Ivy Bridge, and dropped again in Haswell. The reason I didn't notice this is that in the Ivy Bridge documentation, the restriction was in a different section, and described using different language. Now that we know that the restriction only applies to Gen4 and Ivy Bridge, we can limit the unrolling to those platforms. Tested on gen5, gen6, and gen7 (both Ivy Bridge and Haswell). Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-10-22 13:56:37 +01:00
i965/fs: Improve accuracy of dFdy() to match dFdx(). Previously, we computed dFdy() using the following instruction: add(8) dst<1>F src<4,4,0)F -src.2<4,4,0>F { align1 1Q } That had the disadvantage that it computed the same value for all 4 pixels of a 2x2 subspan, which meant that it was less accurate than dFdx(). This patch changes it to the following instruction when c->key.high_quality_derivatives is set: add(8) dst<1>F src<4,4,1>.xyxyF -src<4,4,1>.zwzwF { align16 1Q } This gives it comparable accuracy to dFdx(). Unfortunately, align16 instructions can't be compressed, so in SIMD16 shaders, instead of emitting this instruction: add(16) dst<1>F src<4,4,1>.xyxyF -src<4,4,1>.zwzwF { align16 1H } We need to unroll to two instructions: add(8) dst<1>F src<4,4,1>.xyxyF -src<4,4,1>.zwzwF { align16 1Q } add(8) (dst+1)<1>F (src+1)<4,4,1>.xyxyF -(src+1)<4,4,1>.zwzwF { align16 2Q } Fixes piglit test spec/glsl-1.10/execution/fs-dfdy-accuracy. Acked-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-09-20 17:04:31 +01:00
/* produce accurate derivatives */
struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
i965/brw_reg: struct constructor now needs explicit negate and abs values. We were assuming, when constructing a new brw_reg struct, that the negate and abs register modifiers would not be present by default in the new register. Now, we force explicitly setting these values when constructing a new register. This will avoid problems like forgetting to properly set them when we are using a previous register to generate this new register, as it was happening in the dFdx and dFdy generation functions. Fixes piglit test shaders/glsl-deriv-varyings Cc: "10.4 10.3" <mesa-stable@lists.freedesktop.org> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82991 Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-12-12 16:19:07 +00:00
src.negate, src.abs,
i965/fs: Improve accuracy of dFdy() to match dFdx(). Previously, we computed dFdy() using the following instruction: add(8) dst<1>F src<4,4,0)F -src.2<4,4,0>F { align1 1Q } That had the disadvantage that it computed the same value for all 4 pixels of a 2x2 subspan, which meant that it was less accurate than dFdx(). This patch changes it to the following instruction when c->key.high_quality_derivatives is set: add(8) dst<1>F src<4,4,1>.xyxyF -src<4,4,1>.zwzwF { align16 1Q } This gives it comparable accuracy to dFdx(). Unfortunately, align16 instructions can't be compressed, so in SIMD16 shaders, instead of emitting this instruction: add(16) dst<1>F src<4,4,1>.xyxyF -src<4,4,1>.zwzwF { align16 1H } We need to unroll to two instructions: add(8) dst<1>F src<4,4,1>.xyxyF -src<4,4,1>.zwzwF { align16 1Q } add(8) (dst+1)<1>F (src+1)<4,4,1>.xyxyF -(src+1)<4,4,1>.zwzwF { align16 2Q } Fixes piglit test spec/glsl-1.10/execution/fs-dfdy-accuracy. Acked-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-09-20 17:04:31 +01:00
BRW_REGISTER_TYPE_F,
BRW_VERTICAL_STRIDE_4,
BRW_WIDTH_4,
BRW_HORIZONTAL_STRIDE_1,
BRW_SWIZZLE_XYXY, WRITEMASK_XYZW);
struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
i965/brw_reg: struct constructor now needs explicit negate and abs values. We were assuming, when constructing a new brw_reg struct, that the negate and abs register modifiers would not be present by default in the new register. Now, we force explicitly setting these values when constructing a new register. This will avoid problems like forgetting to properly set them when we are using a previous register to generate this new register, as it was happening in the dFdx and dFdy generation functions. Fixes piglit test shaders/glsl-deriv-varyings Cc: "10.4 10.3" <mesa-stable@lists.freedesktop.org> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82991 Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-12-12 16:19:07 +00:00
src.negate, src.abs,
i965/fs: Improve accuracy of dFdy() to match dFdx(). Previously, we computed dFdy() using the following instruction: add(8) dst<1>F src<4,4,0)F -src.2<4,4,0>F { align1 1Q } That had the disadvantage that it computed the same value for all 4 pixels of a 2x2 subspan, which meant that it was less accurate than dFdx(). This patch changes it to the following instruction when c->key.high_quality_derivatives is set: add(8) dst<1>F src<4,4,1>.xyxyF -src<4,4,1>.zwzwF { align16 1Q } This gives it comparable accuracy to dFdx(). Unfortunately, align16 instructions can't be compressed, so in SIMD16 shaders, instead of emitting this instruction: add(16) dst<1>F src<4,4,1>.xyxyF -src<4,4,1>.zwzwF { align16 1H } We need to unroll to two instructions: add(8) dst<1>F src<4,4,1>.xyxyF -src<4,4,1>.zwzwF { align16 1Q } add(8) (dst+1)<1>F (src+1)<4,4,1>.xyxyF -(src+1)<4,4,1>.zwzwF { align16 2Q } Fixes piglit test spec/glsl-1.10/execution/fs-dfdy-accuracy. Acked-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-09-20 17:04:31 +01:00
BRW_REGISTER_TYPE_F,
BRW_VERTICAL_STRIDE_4,
BRW_WIDTH_4,
BRW_HORIZONTAL_STRIDE_1,
BRW_SWIZZLE_ZWZW, WRITEMASK_XYZW);
brw_push_insn_state(p);
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_access_mode(p, BRW_ALIGN_16);
i965/fs: Only unroll high-accuracy dFdy() from SIMD16 to SIMD8 on gen4 and IVB. In commit 800610f (i965/fs: Improve accuracy of dFdy() to match dFdx()) I unrolled the high-accuracy dFdy() computation from a single SIMD16 instruction to two SIMD8 instructions because of text I found in the i965 (gen4) PRM saying that instruction compression could not be used in align16 mode. I couldn't find similar text in later hardware docs, and I observed problems trying to use instruction compression on align16 mode on Ivy Bridge, so I assumed that the restriction still applied and the associated documentation had simply been lost. After consultation with the hardware engineers, it turns out this is not the case. In point of fact, the restriction was dropped in gen5, re-introduced in Ivy Bridge, and dropped again in Haswell. The reason I didn't notice this is that in the Ivy Bridge documentation, the restriction was in a different section, and described using different language. Now that we know that the restriction only applies to Gen4 and Ivy Bridge, we can limit the unrolling to those platforms. Tested on gen5, gen6, and gen7 (both Ivy Bridge and Haswell). Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-10-22 13:56:37 +01:00
if (unroll_to_simd8) {
i965/fs: set execution size to 8 with simd8 ddy instruction Commit dd5c825 changed the way how execution size for instructions get set. Previously it was based on destination register width, now it is set explicitly when emitting instructions. Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Francisco Jerez <currojerez@riseup.net> Reviewed-by: Matt Turner <mattst88@gmail.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90258
2015-05-12 12:24:08 +01:00
brw_set_default_exec_size(p, BRW_EXECUTE_8);
i965/brw_reg: Add a firsthalf function and use it in the generator Right now, this function is a no-op but it indicates that we intend to only use the first half of the 16-wide register. Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-13 20:23:47 +01:00
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
i965: Delete dead dFdy flipping code. Rob's nir_lower_wpos_ytransform() pass flips dFdy in the opposite case of what I expected, so we always take the negate_value case. It doesn't really matter. v2: Write src0 before src1 in ADD instructions (requested by Matt). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-05-18 18:35:54 +01:00
brw_ADD(p, firsthalf(dst), negate(firsthalf(src0)), firsthalf(src1));
brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
brw_ADD(p, sechalf(dst), negate(sechalf(src0)), sechalf(src1));
i965/brw_reg: Add a firsthalf function and use it in the generator Right now, this function is a no-op but it indicates that we intend to only use the first half of the 16-wide register. Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-13 20:23:47 +01:00
} else {
i965: Delete dead dFdy flipping code. Rob's nir_lower_wpos_ytransform() pass flips dFdy in the opposite case of what I expected, so we always take the negate_value case. It doesn't really matter. v2: Write src0 before src1 in ADD instructions (requested by Matt). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-05-18 18:35:54 +01:00
brw_ADD(p, dst, negate(src0), src1);
i965/fs: Improve accuracy of dFdy() to match dFdx(). Previously, we computed dFdy() using the following instruction: add(8) dst<1>F src<4,4,0)F -src.2<4,4,0>F { align1 1Q } That had the disadvantage that it computed the same value for all 4 pixels of a 2x2 subspan, which meant that it was less accurate than dFdx(). This patch changes it to the following instruction when c->key.high_quality_derivatives is set: add(8) dst<1>F src<4,4,1>.xyxyF -src<4,4,1>.zwzwF { align16 1Q } This gives it comparable accuracy to dFdx(). Unfortunately, align16 instructions can't be compressed, so in SIMD16 shaders, instead of emitting this instruction: add(16) dst<1>F src<4,4,1>.xyxyF -src<4,4,1>.zwzwF { align16 1H } We need to unroll to two instructions: add(8) dst<1>F src<4,4,1>.xyxyF -src<4,4,1>.zwzwF { align16 1Q } add(8) (dst+1)<1>F (src+1)<4,4,1>.xyxyF -(src+1)<4,4,1>.zwzwF { align16 2Q } Fixes piglit test spec/glsl-1.10/execution/fs-dfdy-accuracy. Acked-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-09-20 17:04:31 +01:00
}
brw_pop_insn_state(p);
} else {
/* replicate the derivative at the top-left pixel to other pixels */
struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
i965/brw_reg: struct constructor now needs explicit negate and abs values. We were assuming, when constructing a new brw_reg struct, that the negate and abs register modifiers would not be present by default in the new register. Now, we force explicitly setting these values when constructing a new register. This will avoid problems like forgetting to properly set them when we are using a previous register to generate this new register, as it was happening in the dFdx and dFdy generation functions. Fixes piglit test shaders/glsl-deriv-varyings Cc: "10.4 10.3" <mesa-stable@lists.freedesktop.org> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82991 Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-12-12 16:19:07 +00:00
src.negate, src.abs,
i965/fs: Improve accuracy of dFdy() to match dFdx(). Previously, we computed dFdy() using the following instruction: add(8) dst<1>F src<4,4,0)F -src.2<4,4,0>F { align1 1Q } That had the disadvantage that it computed the same value for all 4 pixels of a 2x2 subspan, which meant that it was less accurate than dFdx(). This patch changes it to the following instruction when c->key.high_quality_derivatives is set: add(8) dst<1>F src<4,4,1>.xyxyF -src<4,4,1>.zwzwF { align16 1Q } This gives it comparable accuracy to dFdx(). Unfortunately, align16 instructions can't be compressed, so in SIMD16 shaders, instead of emitting this instruction: add(16) dst<1>F src<4,4,1>.xyxyF -src<4,4,1>.zwzwF { align16 1H } We need to unroll to two instructions: add(8) dst<1>F src<4,4,1>.xyxyF -src<4,4,1>.zwzwF { align16 1Q } add(8) (dst+1)<1>F (src+1)<4,4,1>.xyxyF -(src+1)<4,4,1>.zwzwF { align16 2Q } Fixes piglit test spec/glsl-1.10/execution/fs-dfdy-accuracy. Acked-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-09-20 17:04:31 +01:00
BRW_REGISTER_TYPE_F,
BRW_VERTICAL_STRIDE_4,
BRW_WIDTH_4,
BRW_HORIZONTAL_STRIDE_0,
BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
i965/brw_reg: struct constructor now needs explicit negate and abs values. We were assuming, when constructing a new brw_reg struct, that the negate and abs register modifiers would not be present by default in the new register. Now, we force explicitly setting these values when constructing a new register. This will avoid problems like forgetting to properly set them when we are using a previous register to generate this new register, as it was happening in the dFdx and dFdy generation functions. Fixes piglit test shaders/glsl-deriv-varyings Cc: "10.4 10.3" <mesa-stable@lists.freedesktop.org> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82991 Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-12-12 16:19:07 +00:00
src.negate, src.abs,
i965/fs: Improve accuracy of dFdy() to match dFdx(). Previously, we computed dFdy() using the following instruction: add(8) dst<1>F src<4,4,0)F -src.2<4,4,0>F { align1 1Q } That had the disadvantage that it computed the same value for all 4 pixels of a 2x2 subspan, which meant that it was less accurate than dFdx(). This patch changes it to the following instruction when c->key.high_quality_derivatives is set: add(8) dst<1>F src<4,4,1>.xyxyF -src<4,4,1>.zwzwF { align16 1Q } This gives it comparable accuracy to dFdx(). Unfortunately, align16 instructions can't be compressed, so in SIMD16 shaders, instead of emitting this instruction: add(16) dst<1>F src<4,4,1>.xyxyF -src<4,4,1>.zwzwF { align16 1H } We need to unroll to two instructions: add(8) dst<1>F src<4,4,1>.xyxyF -src<4,4,1>.zwzwF { align16 1Q } add(8) (dst+1)<1>F (src+1)<4,4,1>.xyxyF -(src+1)<4,4,1>.zwzwF { align16 2Q } Fixes piglit test spec/glsl-1.10/execution/fs-dfdy-accuracy. Acked-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-09-20 17:04:31 +01:00
BRW_REGISTER_TYPE_F,
BRW_VERTICAL_STRIDE_4,
BRW_WIDTH_4,
BRW_HORIZONTAL_STRIDE_0,
BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
i965: Delete dead dFdy flipping code. Rob's nir_lower_wpos_ytransform() pass flips dFdy in the opposite case of what I expected, so we always take the negate_value case. It doesn't really matter. v2: Write src0 before src1 in ADD instructions (requested by Matt). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-05-18 18:35:54 +01:00
brw_ADD(p, dst, negate(src0), src1);
i965/fs: Improve accuracy of dFdy() to match dFdx(). Previously, we computed dFdy() using the following instruction: add(8) dst<1>F src<4,4,0)F -src.2<4,4,0>F { align1 1Q } That had the disadvantage that it computed the same value for all 4 pixels of a 2x2 subspan, which meant that it was less accurate than dFdx(). This patch changes it to the following instruction when c->key.high_quality_derivatives is set: add(8) dst<1>F src<4,4,1>.xyxyF -src<4,4,1>.zwzwF { align16 1Q } This gives it comparable accuracy to dFdx(). Unfortunately, align16 instructions can't be compressed, so in SIMD16 shaders, instead of emitting this instruction: add(16) dst<1>F src<4,4,1>.xyxyF -src<4,4,1>.zwzwF { align16 1H } We need to unroll to two instructions: add(8) dst<1>F src<4,4,1>.xyxyF -src<4,4,1>.zwzwF { align16 1Q } add(8) (dst+1)<1>F (src+1)<4,4,1>.xyxyF -(src+1)<4,4,1>.zwzwF { align16 2Q } Fixes piglit test spec/glsl-1.10/execution/fs-dfdy-accuracy. Acked-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-09-20 17:04:31 +01:00
}
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
}
i965/fs: Improve performance of shaders that start out with a discard. I had tried this in the past, but ran into trouble with applications that sample from undiscarded pixels in the same subspan. To fix that issue, only jump to the end for an entire subspan at a time. Improves GLbenchmark 2.7 (1024x768) performance by 7.9 +/- 1.5% (n=8). v2: Drop the br variable in the jump instruction -- if I ever do jumps pre-gen6, it'll be a different code block anyway since we don't have HALT until gen6. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-06 18:15:08 +00:00
void
fs_generator::generate_discard_jump(fs_inst *inst)
{
i965/fs: Add a devinfo field to the generator and use it for gen checks Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 01:45:40 +01:00
assert(devinfo->gen >= 6);
i965/fs: Improve performance of shaders that start out with a discard. I had tried this in the past, but ran into trouble with applications that sample from undiscarded pixels in the same subspan. To fix that issue, only jump to the end for an entire subspan at a time. Improves GLbenchmark 2.7 (1024x768) performance by 7.9 +/- 1.5% (n=8). v2: Drop the br variable in the jump instruction -- if I ever do jumps pre-gen6, it'll be a different code block anyway since we don't have HALT until gen6. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-06 18:15:08 +00:00
/* This HALT will be patched up at FB write time to point UIP at the end of
* the program, and at brw_uip_jip() JIP will be set to the end of the
* current block (or the program).
*/
this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
brw_push_insn_state(p);
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
i965/fs: Improve performance of shaders that start out with a discard. I had tried this in the past, but ran into trouble with applications that sample from undiscarded pixels in the same subspan. To fix that issue, only jump to the end for an entire subspan at a time. Improves GLbenchmark 2.7 (1024x768) performance by 7.9 +/- 1.5% (n=8). v2: Drop the br variable in the jump instruction -- if I ever do jumps pre-gen6, it'll be a different code block anyway since we don't have HALT until gen6. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-06 18:15:08 +00:00
gen6_HALT(p);
brw_pop_insn_state(p);
}
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
void
i965: Merge together opcodes for SHADER_OPCODE_GEN4_SCRATCH_READ/WRITE I'm going to be introducing gen7 variants, and the previous naming was going to get confusing. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-10-16 19:45:06 +01:00
fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
{
assert(inst->mlen != 0);
brw_MOV(p,
i965/fs: Use instruction execution sizes when generating scratch reads/writes Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2014-10-24 19:35:51 +01:00
brw_uvec_mrf(inst->exec_size, (inst->base_mrf + 1), 0),
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
retype(src, BRW_REGISTER_TYPE_UD));
i965/fs: Fix register spilling for 16-wide. Things blew up when I enabled the debug register spill code without disabling 16-wide, so I decided to just fix 16-wide spilling. We still don't generate 16-wide when register spilling happens as part of allocation (since we expect it to be slower), but now we can experiment with allowing it in some cases in the future. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-10-16 20:16:51 +01:00
brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
i965/fs: Use instruction execution sizes when generating scratch reads/writes Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2014-10-24 19:35:51 +01:00
inst->exec_size / 8, inst->offset);
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
}
void
i965: Merge together opcodes for SHADER_OPCODE_GEN4_SCRATCH_READ/WRITE I'm going to be introducing gen7 variants, and the previous naming was going to get confusing. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-10-16 19:45:06 +01:00
fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst)
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
{
assert(inst->mlen != 0);
i965/fs: Fix register spilling for 16-wide. Things blew up when I enabled the debug register spill code without disabling 16-wide, so I decided to just fix 16-wide spilling. We still don't generate 16-wide when register spilling happens as part of allocation (since we expect it to be slower), but now we can experiment with allowing it in some cases in the future. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-10-16 20:16:51 +01:00
brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf),
i965/fs: Use instruction execution sizes when generating scratch reads/writes Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2014-10-24 19:35:51 +01:00
inst->exec_size / 8, inst->offset);
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
}
i965/fs: Use the gen7 scratch read opcode when possible. This avoids a lot of message setup we had to do otherwise. Improves GLB2.7 performance with register spilling force enabled by 1.6442% +/- 0.553218% (n=4). v2: Use BRW_PREDICATE_NONE, improve a comment (by Paul). Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-10-16 19:51:22 +01:00
void
fs_generator::generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst)
{
i965/fs: Use instruction execution sizes when generating scratch reads/writes Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2014-10-24 19:35:51 +01:00
gen7_block_read_scratch(p, dst, inst->exec_size / 8, inst->offset);
i965/fs: Use the gen7 scratch read opcode when possible. This avoids a lot of message setup we had to do otherwise. Improves GLB2.7 performance with register spilling force enabled by 1.6442% +/- 0.553218% (n=4). v2: Use BRW_PREDICATE_NONE, improve a comment (by Paul). Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-10-16 19:51:22 +01:00
}
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
void
i965/fs: Rename the existing pull constant load opcode. We're going to use another send message for handling loads with a varying per-fragment array index.
2012-11-07 18:42:34 +00:00
fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
struct brw_reg dst,
struct brw_reg index,
struct brw_reg offset)
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
{
assert(inst->mlen != 0);
i965/fs: Communicate the pull constant block read parameters through fs_regs. I wanted to add the surface index as a variable value for UBO support, and a reg seemed like the obvious way to go. This exposes more of the information to CSE, which we'll probably want to apply to pull constant loads for UBOs eventually (you might access 4 floats in a row, each of which would produce an oword block read of the same block). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-06-20 23:41:14 +01:00
assert(index.file == BRW_IMMEDIATE_VALUE &&
index.type == BRW_REGISTER_TYPE_UD);
i965: Make 'dw1' and 'bits' unnamed structures in brw_reg. Generated by sed -i -e 's/\.bits\././g' *.c *.h *.cpp sed -i -e 's/dw1\.//g' *.c *.h *.cpp and then reverting changes to comments in gen7_blorp.cpp and brw_fs_generator.cpp. There wasn't any utility offered by forcing the programmer to list these to access their fields. Removing them will reduce churn in future commits. This is C11 (and gcc has apparently supported it for sometime "compatibility with other compilers") See https://gcc.gnu.org/onlinedocs/gcc/Unnamed-Fields.html Reviewed-by: Emil Velikov <emil.velikov@collabora.co.uk> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-10-23 03:41:30 +01:00
uint32_t surf_index = index.ud;
i965/fs: Communicate the pull constant block read parameters through fs_regs. I wanted to add the surface index as a variable value for UBO support, and a reg seemed like the obvious way to go. This exposes more of the information to CSE, which we'll probably want to apply to pull constant loads for UBOs eventually (you might access 4 floats in a row, each of which would produce an oword block read of the same block). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-06-20 23:41:14 +01:00
assert(offset.file == BRW_IMMEDIATE_VALUE &&
offset.type == BRW_REGISTER_TYPE_UD);
i965: Make 'dw1' and 'bits' unnamed structures in brw_reg. Generated by sed -i -e 's/\.bits\././g' *.c *.h *.cpp sed -i -e 's/dw1\.//g' *.c *.h *.cpp and then reverting changes to comments in gen7_blorp.cpp and brw_fs_generator.cpp. There wasn't any utility offered by forcing the programmer to list these to access their fields. Removing them will reduce churn in future commits. This is C11 (and gcc has apparently supported it for sometime "compatibility with other compilers") See https://gcc.gnu.org/onlinedocs/gcc/Unnamed-Fields.html Reviewed-by: Emil Velikov <emil.velikov@collabora.co.uk> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-10-23 03:41:30 +01:00
uint32_t read_offset = offset.ud;
i965/fs: Communicate the pull constant block read parameters through fs_regs. I wanted to add the surface index as a variable value for UBO support, and a reg seemed like the obvious way to go. This exposes more of the information to CSE, which we'll probably want to apply to pull constant loads for UBOs eventually (you might access 4 floats in a row, each of which would produce an oword block read of the same block). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-06-20 23:41:14 +01:00
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
i965/fs: Communicate the pull constant block read parameters through fs_regs. I wanted to add the surface index as a variable value for UBO support, and a reg seemed like the obvious way to go. This exposes more of the information to CSE, which we'll probably want to apply to pull constant loads for UBOs eventually (you might access 4 floats in a row, each of which would produce an oword block read of the same block). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-06-20 23:41:14 +01:00
read_offset, surf_index);
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
}
i965/fs: Set up gen7 UBO loads as sends from GRFs. This gives the instruction scheduler a chance to schedule between the loads, whereas before it was restricted due to the dependencies between the MRFs for setting them up. For one shader in gles3conform, it goes from getting stuck in register allocation for as long as anybody's bothered to leave it running down to 23 seconds, thanks to the LIFO scheduling. Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-05 08:06:30 +00:00
void
fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
struct brw_reg dst,
struct brw_reg index,
struct brw_reg offset)
{
i965/fs: Generate indirect sends for nonconstant UBO array accesses Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
2014-08-02 03:27:21 +01:00
assert(index.type == BRW_REGISTER_TYPE_UD);
i965/fs: Set up gen7 UBO loads as sends from GRFs. This gives the instruction scheduler a chance to schedule between the loads, whereas before it was restricted due to the dependencies between the MRFs for setting them up. For one shader in gles3conform, it goes from getting stuck in register allocation for as long as anybody's bothered to leave it running down to 23 seconds, thanks to the LIFO scheduling. Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-05 08:06:30 +00:00
assert(offset.file == BRW_GENERAL_REGISTER_FILE);
i965/fs: Switch to using sampler LD messages for uniform pull constants. When forcing the compiler to always generate pull constants instead of push constants (in order to have an easy to use testcase), improves performance of my old GLSL demo 23.3553% +/- 1.42968% (n=7). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60866 Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-06 22:47:22 +00:00
/* Reference just the dword we need, to avoid angering validate_reg(). */
offset = brw_vec1_grf(offset.nr, 0);
i965/fs: Set up gen7 UBO loads as sends from GRFs. This gives the instruction scheduler a chance to schedule between the loads, whereas before it was restricted due to the dependencies between the MRFs for setting them up. For one shader in gles3conform, it goes from getting stuck in register allocation for as long as anybody's bothered to leave it running down to 23 seconds, thanks to the LIFO scheduling. Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-05 08:06:30 +00:00
i965/fs: Switch to using sampler LD messages for uniform pull constants. When forcing the compiler to always generate pull constants instead of push constants (in order to have an easy to use testcase), improves performance of my old GLSL demo 23.3553% +/- 1.42968% (n=7). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60866 Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-06 22:47:22 +00:00
/* We use the SIMD4x2 mode because we want to end up with 4 components in
* the destination loaded consecutively from the same offset (which appears
* in the first component, and the rest are ignored).
*/
dst.width = BRW_WIDTH_4;
i965/fs: Track the binding table size in brw_wm_prog_data. By tracking the maximum surface index used by the shader, we know just how small we can make the binding table. Since it depends entirely on the shader program, we can just compute it once at compile time, rather than at binding table emit time (which happens during drawing). v2: Store binding_table_size, rather than max_surface_index, for consistency with the VS (which needs to be able to represent 0 surfaces). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-08-15 03:49:33 +01:00
i965/skl: Always use a header for SIMD4x2 sampler messages SKL+ overloads the SIMD4x2 SIMD mode to mean either SIMD8D or SIMD4x2 depending on bit 22 in the message header. If the bit is 0 or there is no header we get SIMD8D. We always wand SIMD4x2 in vec4 and for fs pull constants, so use a message header in those cases and set bit 22 there. Based on an initial patch from Ken. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
2014-12-10 22:59:26 +00:00
struct brw_reg src = offset;
bool header_present = false;
i965/fs: Add a devinfo field to the generator and use it for gen checks Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 01:45:40 +01:00
if (devinfo->gen >= 9) {
i965/skl: Always use a header for SIMD4x2 sampler messages SKL+ overloads the SIMD4x2 SIMD mode to mean either SIMD8D or SIMD4x2 depending on bit 22 in the message header. If the bit is 0 or there is no header we get SIMD8D. We always wand SIMD4x2 in vec4 and for fs pull constants, so use a message header in those cases and set bit 22 there. Based on an initial patch from Ken. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
2014-12-10 22:59:26 +00:00
/* Skylake requires a message header in order to use SIMD4x2 mode. */
i965/fs: Actually set/use the mlen for gen7 uniform pull constant loads Previously, we were allocating the payload with different sizes per gen and then figuring out the mlen in the generator based on gen. This meant, among other things, that the higher level passes knew nothing about it. Acked-by: Francisco Jerez <currojerez@riseup.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-06-19 20:58:37 +01:00
src = retype(brw_vec4_grf(offset.nr, 0), BRW_REGISTER_TYPE_UD);
i965/skl: Always use a header for SIMD4x2 sampler messages SKL+ overloads the SIMD4x2 SIMD mode to mean either SIMD8D or SIMD4x2 depending on bit 22 in the message header. If the bit is 0 or there is no header we get SIMD8D. We always wand SIMD4x2 in vec4 and for fs pull constants, so use a message header in those cases and set bit 22 there. Based on an initial patch from Ken. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
2014-12-10 22:59:26 +00:00
header_present = true;
brw_push_insn_state(p);
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
i965/skl: Force the exec size to 8 when initing header for SIMD4x2 On Gen9+ there needs to be a header when sampling using SIMD4x2. The header is set up by copying from the g0 register. Commit 07c571a39f tried to fix this mov instruction to always use an exec size of 8 because previously it was incorrectly using 4. It did this by casting the type of the destination register to vec8. This was done because there is code in brw_set_dest to guess the exec size based on the width of the dest register. However I misunderstood how this works because it is actually only used when the width is less than 8. That means the patch actually changed it to use the default exec size which on SIMD16 would be 16 and the MOV would clobber over the first register in the send message. This patch makes it additionally set the default exec size to 8. This is similar to how the message is set up in fs_generator::generate_tex. I think this wasn't picked up by any Piglit tests because we don't have any fragment shaders that hit this code path so nothing was using SIMD16. However the patch caused failures in deqp tests. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90153 Reviewed-by: Matt Turner <mattst88@gmail.com> Tested-by: Tapani Pälli <tapani.palli@intel.com>
2015-04-23 18:09:52 +01:00
brw_set_default_exec_size(p, BRW_EXECUTE_8);
i965/skl: Use an exec size of 8 to initialise the message header Commit e93566a15c61c33faa changed the message header code needed to make Skylake use SIMD4x2 so that it uses a register with width 4 instead of 8 as the source register in the send message. However it also changed the width for the dest in the MOV instruction which is used to initialise the header register with the values from g0. The width of the destination is used to determine the exec size in brw_set_dest so this would end up making the MOV have an exec size of 4. I think this would end up leaving the top half of the register uninitialised. The top half of the header has meaningful values so this probably isn't a good idea. This patch just casts the dest register for the MOV instruction back to a vec8 to fix it. It doesn't cause any changes to a Piglit run. Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
2015-04-10 17:20:21 +01:00
brw_MOV(p, vec8(src), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
i965/skl: Always use a header for SIMD4x2 sampler messages SKL+ overloads the SIMD4x2 SIMD mode to mean either SIMD8D or SIMD4x2 depending on bit 22 in the message header. If the bit is 0 or there is no header we get SIMD8D. We always wand SIMD4x2 in vec4 and for fs pull constants, so use a message header in those cases and set bit 22 there. Based on an initial patch from Ken. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
2014-12-10 22:59:26 +00:00
brw_set_default_access_mode(p, BRW_ALIGN_1);
brw_MOV(p, get_element_ud(src, 2),
brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2));
brw_pop_insn_state(p);
}
i965/fs: Generate indirect sends for nonconstant UBO array accesses Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
2014-08-02 03:27:21 +01:00
if (index.file == BRW_IMMEDIATE_VALUE) {
i965: Make 'dw1' and 'bits' unnamed structures in brw_reg. Generated by sed -i -e 's/\.bits\././g' *.c *.h *.cpp sed -i -e 's/dw1\.//g' *.c *.h *.cpp and then reverting changes to comments in gen7_blorp.cpp and brw_fs_generator.cpp. There wasn't any utility offered by forcing the programmer to list these to access their fields. Removing them will reduce churn in future commits. This is C11 (and gcc has apparently supported it for sometime "compatibility with other compilers") See https://gcc.gnu.org/onlinedocs/gcc/Unnamed-Fields.html Reviewed-by: Emil Velikov <emil.velikov@collabora.co.uk> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-10-23 03:41:30 +01:00
uint32_t surf_index = index.ud;
i965/fs: Generate indirect sends for nonconstant UBO array accesses Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
2014-08-02 03:27:21 +01:00
brw_push_insn_state(p);
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
i965/fs: Set exec size for gen7 pull const loads v2 (Topi): - No need to set the execsize for the indirect send message, the next patch will handle that. - Set the execution size explicitly instead of taking it from the width of the dst that we set before. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2015-12-03 09:59:23 +00:00
brw_inst_set_exec_size(devinfo, send, BRW_EXECUTE_4);
i965/fs: Generate indirect sends for nonconstant UBO array accesses Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
2014-08-02 03:27:21 +01:00
brw_pop_insn_state(p);
brw_set_dest(p, send, dst);
i965/skl: Always use a header for SIMD4x2 sampler messages SKL+ overloads the SIMD4x2 SIMD mode to mean either SIMD8D or SIMD4x2 depending on bit 22 in the message header. If the bit is 0 or there is no header we get SIMD8D. We always wand SIMD4x2 in vec4 and for fs pull constants, so use a message header in those cases and set bit 22 there. Based on an initial patch from Ken. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
2014-12-10 22:59:26 +00:00
brw_set_src0(p, send, src);
i965/fs: Generate indirect sends for nonconstant UBO array accesses Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
2014-08-02 03:27:21 +01:00
brw_set_sampler_message(p, send,
surf_index,
0, /* LD message ignores sampler unit */
GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1, /* rlen */
i965/fs: Actually set/use the mlen for gen7 uniform pull constant loads Previously, we were allocating the payload with different sizes per gen and then figuring out the mlen in the generator based on gen. This meant, among other things, that the higher level passes knew nothing about it. Acked-by: Francisco Jerez <currojerez@riseup.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-06-19 20:58:37 +01:00
inst->mlen,
i965/skl: Always use a header for SIMD4x2 sampler messages SKL+ overloads the SIMD4x2 SIMD mode to mean either SIMD8D or SIMD4x2 depending on bit 22 in the message header. If the bit is 0 or there is no header we get SIMD8D. We always wand SIMD4x2 in vec4 and for fs pull constants, so use a message header in those cases and set bit 22 there. Based on an initial patch from Ken. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
2014-12-10 22:59:26 +00:00
header_present,
i965/fs: Generate indirect sends for nonconstant UBO array accesses Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
2014-08-02 03:27:21 +01:00
BRW_SAMPLER_SIMD_MODE_SIMD4X2,
0);
} else {
struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
brw_push_insn_state(p);
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
brw_set_default_access_mode(p, BRW_ALIGN_1);
/* a0.0 = surf_index & 0xff */
brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
i965: Make the brw_inst helpers take a device_info instead of a context Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 02:00:06 +01:00
brw_inst_set_exec_size(p->devinfo, insn_and, BRW_EXECUTE_1);
i965/fs: Generate indirect sends for nonconstant UBO array accesses Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
2014-08-02 03:27:21 +01:00
brw_set_dest(p, insn_and, addr);
brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
i965: Factor out logic to build a send message instruction with indirect descriptor. This is going to be useful because the Gen7+ uniform and varying pull constant, texturing, typed and untyped surface read, write, and atomic generation code on the vec4 and fs back-end all require the same logic to handle conditionally indirect surface indices. In pseudocode: | if (surface.file == BRW_IMMEDIATE_VALUE) { | inst = brw_SEND(p, dst, payload); | set_descriptor_control_bits(inst, surface, ...); | } else { | inst = brw_OR(p, addr, surface, 0); | set_descriptor_control_bits(inst, ...); | inst = brw_SEND(p, dst, payload); | set_indirect_send_descriptor(inst, addr); | } This patch abstracts out this frequently recurring pattern so we can now write: | inst = brw_send_indirect_message(p, sfid, dst, payload, surface) | set_descriptor_control_bits(inst, ...); without worrying about handling the immediate and indirect surface index cases explicitly. v2: Rebase. Improve documentatation and commit message. (Topi) Preserve UW destination type cargo-cult. (Topi, Ken, Matt) Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2015-03-19 13:44:24 +00:00
/* dst = send(payload, a0.0 | <descriptor>) */
brw_inst *insn = brw_send_indirect_message(
p, BRW_SFID_SAMPLER, dst, src, addr);
brw_set_sampler_message(p, insn,
0,
0, /* LD message ignores sampler unit */
i965/fs: Generate indirect sends for nonconstant UBO array accesses Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
2014-08-02 03:27:21 +01:00
GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
i965: Factor out logic to build a send message instruction with indirect descriptor. This is going to be useful because the Gen7+ uniform and varying pull constant, texturing, typed and untyped surface read, write, and atomic generation code on the vec4 and fs back-end all require the same logic to handle conditionally indirect surface indices. In pseudocode: | if (surface.file == BRW_IMMEDIATE_VALUE) { | inst = brw_SEND(p, dst, payload); | set_descriptor_control_bits(inst, surface, ...); | } else { | inst = brw_OR(p, addr, surface, 0); | set_descriptor_control_bits(inst, ...); | inst = brw_SEND(p, dst, payload); | set_indirect_send_descriptor(inst, addr); | } This patch abstracts out this frequently recurring pattern so we can now write: | inst = brw_send_indirect_message(p, sfid, dst, payload, surface) | set_descriptor_control_bits(inst, ...); without worrying about handling the immediate and indirect surface index cases explicitly. v2: Rebase. Improve documentatation and commit message. (Topi) Preserve UW destination type cargo-cult. (Topi, Ken, Matt) Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2015-03-19 13:44:24 +00:00
1, /* rlen */
i965/fs: Actually set/use the mlen for gen7 uniform pull constant loads Previously, we were allocating the payload with different sizes per gen and then figuring out the mlen in the generator based on gen. This meant, among other things, that the higher level passes knew nothing about it. Acked-by: Francisco Jerez <currojerez@riseup.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-06-19 20:58:37 +01:00
inst->mlen,
i965/skl: Always use a header for SIMD4x2 sampler messages SKL+ overloads the SIMD4x2 SIMD mode to mean either SIMD8D or SIMD4x2 depending on bit 22 in the message header. If the bit is 0 or there is no header we get SIMD8D. We always wand SIMD4x2 in vec4 and for fs pull constants, so use a message header in those cases and set bit 22 there. Based on an initial patch from Ken. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
2014-12-10 22:59:26 +00:00
header_present,
i965/fs: Generate indirect sends for nonconstant UBO array accesses Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
2014-08-02 03:27:21 +01:00
BRW_SAMPLER_SIMD_MODE_SIMD4X2,
0);
brw_pop_insn_state(p);
}
i965/fs: Set up gen7 UBO loads as sends from GRFs. This gives the instruction scheduler a chance to schedule between the loads, whereas before it was restricted due to the dependencies between the MRFs for setting them up. For one shader in gles3conform, it goes from getting stuck in register allocation for as long as anybody's bothered to leave it running down to 23 seconds, thanks to the LIFO scheduling. Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-05 08:06:30 +00:00
}
i965/fs: Add instruction emit for varying-index reads of uniforms. The gen7 send-from-GRF path is sufficiently different from the perspective of IR generation and optimization that I just made it a separate opcode. v2: fix whitespace, rebase on Ken's recent refactor.
2012-11-07 19:18:34 +00:00
void
i965/fs: Rename Gen4 physical varying pull constant load opcode. For consistency with the Gen7 variant. I'm not doing the same to the uniform pull constant message at this point because the non-GEN7 one is still overloaded to be either an expression-like logical instruction or a Gen4-specific physical send message. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-05-20 21:03:31 +01:00
fs_generator::generate_varying_pull_constant_load_gen4(fs_inst *inst,
struct brw_reg dst,
struct brw_reg index)
i965/fs: Add instruction emit for varying-index reads of uniforms. The gen7 send-from-GRF path is sufficiently different from the perspective of IR generation and optimization that I just made it a separate opcode. v2: fix whitespace, rebase on Ken's recent refactor.
2012-11-07 19:18:34 +00:00
{
i965/fs: Add a devinfo field to the generator and use it for gen checks Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 01:45:40 +01:00
assert(devinfo->gen < 7); /* Should use the gen7 variant. */
i965: Change header_present to header_size in backend_instruction Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-03-24 17:17:32 +00:00
assert(inst->header_size != 0);
i965/fs: Use LD messages for pre-gen7 varying-index uniform loads This comes at a minor performance cost at the moment (-3.2% +/- 0.2%, n=14 on my GM45 forced to load all uniforms through the varying-index path), but we get a whole vec4 at a time to reuse in the next commit. v2: Fix comment about channels in the other message. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> NOTE: This is a candidate for the 9.1 branch.
2013-03-18 17:16:42 +00:00
assert(inst->mlen);
i965/fs: Add instruction emit for varying-index reads of uniforms. The gen7 send-from-GRF path is sufficiently different from the perspective of IR generation and optimization that I just made it a separate opcode. v2: fix whitespace, rebase on Ken's recent refactor.
2012-11-07 19:18:34 +00:00
assert(index.file == BRW_IMMEDIATE_VALUE &&
index.type == BRW_REGISTER_TYPE_UD);
i965: Make 'dw1' and 'bits' unnamed structures in brw_reg. Generated by sed -i -e 's/\.bits\././g' *.c *.h *.cpp sed -i -e 's/dw1\.//g' *.c *.h *.cpp and then reverting changes to comments in gen7_blorp.cpp and brw_fs_generator.cpp. There wasn't any utility offered by forcing the programmer to list these to access their fields. Removing them will reduce churn in future commits. This is C11 (and gcc has apparently supported it for sometime "compatibility with other compilers") See https://gcc.gnu.org/onlinedocs/gcc/Unnamed-Fields.html Reviewed-by: Emil Velikov <emil.velikov@collabora.co.uk> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-10-23 03:41:30 +01:00
uint32_t surf_index = index.ud;
i965/fs: Add instruction emit for varying-index reads of uniforms. The gen7 send-from-GRF path is sufficiently different from the perspective of IR generation and optimization that I just made it a separate opcode. v2: fix whitespace, rebase on Ken's recent refactor.
2012-11-07 19:18:34 +00:00
i965/fs: Use LD messages for pre-gen7 varying-index uniform loads This comes at a minor performance cost at the moment (-3.2% +/- 0.2%, n=14 on my GM45 forced to load all uniforms through the varying-index path), but we get a whole vec4 at a time to reuse in the next commit. v2: Fix comment about channels in the other message. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> NOTE: This is a candidate for the 9.1 branch.
2013-03-18 17:16:42 +00:00
uint32_t simd_mode, rlen, msg_type;
i965/fs: Add instruction emit for varying-index reads of uniforms. The gen7 send-from-GRF path is sufficiently different from the perspective of IR generation and optimization that I just made it a separate opcode. v2: fix whitespace, rebase on Ken's recent refactor.
2012-11-07 19:18:34 +00:00
if (dispatch_width == 16) {
i965/fs: Use LD messages for pre-gen7 varying-index uniform loads This comes at a minor performance cost at the moment (-3.2% +/- 0.2%, n=14 on my GM45 forced to load all uniforms through the varying-index path), but we get a whole vec4 at a time to reuse in the next commit. v2: Fix comment about channels in the other message. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> NOTE: This is a candidate for the 9.1 branch.
2013-03-18 17:16:42 +00:00
simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
rlen = 8;
i965/fs: Add instruction emit for varying-index reads of uniforms. The gen7 send-from-GRF path is sufficiently different from the perspective of IR generation and optimization that I just made it a separate opcode. v2: fix whitespace, rebase on Ken's recent refactor.
2012-11-07 19:18:34 +00:00
} else {
i965/fs: Use LD messages for pre-gen7 varying-index uniform loads This comes at a minor performance cost at the moment (-3.2% +/- 0.2%, n=14 on my GM45 forced to load all uniforms through the varying-index path), but we get a whole vec4 at a time to reuse in the next commit. v2: Fix comment about channels in the other message. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> NOTE: This is a candidate for the 9.1 branch.
2013-03-18 17:16:42 +00:00
simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
rlen = 4;
i965/fs: Add instruction emit for varying-index reads of uniforms. The gen7 send-from-GRF path is sufficiently different from the perspective of IR generation and optimization that I just made it a separate opcode. v2: fix whitespace, rebase on Ken's recent refactor.
2012-11-07 19:18:34 +00:00
}
i965/fs: Add a devinfo field to the generator and use it for gen checks Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 01:45:40 +01:00
if (devinfo->gen >= 5)
i965/fs: Use LD messages for pre-gen7 varying-index uniform loads This comes at a minor performance cost at the moment (-3.2% +/- 0.2%, n=14 on my GM45 forced to load all uniforms through the varying-index path), but we get a whole vec4 at a time to reuse in the next commit. v2: Fix comment about channels in the other message. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> NOTE: This is a candidate for the 9.1 branch.
2013-03-18 17:16:42 +00:00
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
else {
/* We always use the SIMD16 message so that we only have to load U, and
* not V or R.
*/
msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
assert(inst->mlen == 3);
assert(inst->regs_written == 8);
rlen = 8;
simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
}
i965/fs: Add instruction emit for varying-index reads of uniforms. The gen7 send-from-GRF path is sufficiently different from the perspective of IR generation and optimization that I just made it a separate opcode. v2: fix whitespace, rebase on Ken's recent refactor.
2012-11-07 19:18:34 +00:00
struct brw_reg header = brw_vec8_grf(0, 0);
gen6_resolve_implied_move(p, &header, inst->base_mrf);
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 22:29:25 +01:00
brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
i965: Make the brw_inst helpers take a device_info instead of a context Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 02:00:06 +01:00
brw_inst_set_qtr_control(p->devinfo, send, BRW_COMPRESSION_NONE);
i965: Retype pre-Gen6 varying pull load destination to UW. This sets up the proper execution mask for sends in SIMD16 mode. Fixes Piglit's glsl-fs-normalmatrix, glsl-fs-uniform-array-2, glsl-fs-uniform-array-6, and glsl-fs-uniform-array-7 on Ironlake, which regressed when I enabled SIMD16 pull parameter support in commit b207e88b25e526d0f1ada7b19605b880a27866dc. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2014-04-17 04:15:23 +01:00
brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
i965/fs: Add instruction emit for varying-index reads of uniforms. The gen7 send-from-GRF path is sufficiently different from the perspective of IR generation and optimization that I just made it a separate opcode. v2: fix whitespace, rebase on Ken's recent refactor.
2012-11-07 19:18:34 +00:00
brw_set_src0(p, send, header);
i965/fs: Add a devinfo field to the generator and use it for gen checks Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 01:45:40 +01:00
if (devinfo->gen < 6)
i965: Make the brw_inst helpers take a device_info instead of a context Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 02:00:06 +01:00
brw_inst_set_base_mrf(p->devinfo, send, inst->base_mrf);
i965/fs: Use LD messages for pre-gen7 varying-index uniform loads This comes at a minor performance cost at the moment (-3.2% +/- 0.2%, n=14 on my GM45 forced to load all uniforms through the varying-index path), but we get a whole vec4 at a time to reuse in the next commit. v2: Fix comment about channels in the other message. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> NOTE: This is a candidate for the 9.1 branch.
2013-03-18 17:16:42 +00:00
/* Our surface is set up as floats, regardless of what actual data is
* stored in it.
*/
uint32_t return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
brw_set_sampler_message(p, send,
i965/fs: Add instruction emit for varying-index reads of uniforms. The gen7 send-from-GRF path is sufficiently different from the perspective of IR generation and optimization that I just made it a separate opcode. v2: fix whitespace, rebase on Ken's recent refactor.
2012-11-07 19:18:34 +00:00
surf_index,
i965/fs: Use LD messages for pre-gen7 varying-index uniform loads This comes at a minor performance cost at the moment (-3.2% +/- 0.2%, n=14 on my GM45 forced to load all uniforms through the varying-index path), but we get a whole vec4 at a time to reuse in the next commit. v2: Fix comment about channels in the other message. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> NOTE: This is a candidate for the 9.1 branch.
2013-03-18 17:16:42 +00:00
0, /* sampler (unused) */
i965/fs: Add instruction emit for varying-index reads of uniforms. The gen7 send-from-GRF path is sufficiently different from the perspective of IR generation and optimization that I just made it a separate opcode. v2: fix whitespace, rebase on Ken's recent refactor.
2012-11-07 19:18:34 +00:00
msg_type,
i965/fs: Use LD messages for pre-gen7 varying-index uniform loads This comes at a minor performance cost at the moment (-3.2% +/- 0.2%, n=14 on my GM45 forced to load all uniforms through the varying-index path), but we get a whole vec4 at a time to reuse in the next commit. v2: Fix comment about channels in the other message. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> NOTE: This is a candidate for the 9.1 branch.
2013-03-18 17:16:42 +00:00
rlen,
i965/fs: Add instruction emit for varying-index reads of uniforms. The gen7 send-from-GRF path is sufficiently different from the perspective of IR generation and optimization that I just made it a separate opcode. v2: fix whitespace, rebase on Ken's recent refactor.
2012-11-07 19:18:34 +00:00
inst->mlen,
i965: Change header_present to header_size in backend_instruction Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-03-24 17:17:32 +00:00
inst->header_size != 0,
i965/fs: Use LD messages for pre-gen7 varying-index uniform loads This comes at a minor performance cost at the moment (-3.2% +/- 0.2%, n=14 on my GM45 forced to load all uniforms through the varying-index path), but we get a whole vec4 at a time to reuse in the next commit. v2: Fix comment about channels in the other message. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> NOTE: This is a candidate for the 9.1 branch.
2013-03-18 17:16:42 +00:00
simd_mode,
return_format);
i965/fs: Add instruction emit for varying-index reads of uniforms. The gen7 send-from-GRF path is sufficiently different from the perspective of IR generation and optimization that I just made it a separate opcode. v2: fix whitespace, rebase on Ken's recent refactor.
2012-11-07 19:18:34 +00:00
}
void
fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
struct brw_reg dst,
struct brw_reg index,
struct brw_reg offset)
{
i965/fs: Add a devinfo field to the generator and use it for gen checks Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 01:45:40 +01:00
assert(devinfo->gen >= 7);
i965/fs: Add instruction emit for varying-index reads of uniforms. The gen7 send-from-GRF path is sufficiently different from the perspective of IR generation and optimization that I just made it a separate opcode. v2: fix whitespace, rebase on Ken's recent refactor.
2012-11-07 19:18:34 +00:00
/* Varying-offset pull constant loads are treated as a normal expression on
* gen7, so the fact that it's a send message is hidden at the IR level.
*/
i965: Change header_present to header_size in backend_instruction Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-03-24 17:17:32 +00:00
assert(inst->header_size == 0);
i965/fs: Add instruction emit for varying-index reads of uniforms. The gen7 send-from-GRF path is sufficiently different from the perspective of IR generation and optimization that I just made it a separate opcode. v2: fix whitespace, rebase on Ken's recent refactor.
2012-11-07 19:18:34 +00:00
assert(!inst->mlen);
i965/fs: Generate indirect sends for nonconstant UBO array accesses Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
2014-08-02 03:27:21 +01:00
assert(index.type == BRW_REGISTER_TYPE_UD);
i965/fs: Add instruction emit for varying-index reads of uniforms. The gen7 send-from-GRF path is sufficiently different from the perspective of IR generation and optimization that I just made it a separate opcode. v2: fix whitespace, rebase on Ken's recent refactor.
2012-11-07 19:18:34 +00:00
i965/fs: Improve performance of varying-index uniform loads on IVB. Like we have done for the VS and for constant-index uniform loads, we use the sampler engine to get caching in front of the L3 to avoid tickling the IVB L3 bug. This is also a bit of a functional change, as we're now loading a vec4 instead of a single dword, though we're not taking advantage of the other 3 components of the vec4 (yet). With the driver hacked to always take the varying-index path for all uniforms, improves performance of my old GLSL demo by 315% +/- 2% (n=4). This a major fix for some blur shaders in compositors from the varying-index uniforms support I introduced in 9.1. v2: Move old offset computation into the pre-gen7 path. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=61554 NOTE: This is a candidate for the 9.1 branch.
2013-03-13 21:48:55 +00:00
uint32_t simd_mode, rlen, mlen;
i965/fs: Add instruction emit for varying-index reads of uniforms. The gen7 send-from-GRF path is sufficiently different from the perspective of IR generation and optimization that I just made it a separate opcode. v2: fix whitespace, rebase on Ken's recent refactor.
2012-11-07 19:18:34 +00:00
if (dispatch_width == 16) {
i965/fs: Improve performance of varying-index uniform loads on IVB. Like we have done for the VS and for constant-index uniform loads, we use the sampler engine to get caching in front of the L3 to avoid tickling the IVB L3 bug. This is also a bit of a functional change, as we're now loading a vec4 instead of a single dword, though we're not taking advantage of the other 3 components of the vec4 (yet). With the driver hacked to always take the varying-index path for all uniforms, improves performance of my old GLSL demo by 315% +/- 2% (n=4). This a major fix for some blur shaders in compositors from the varying-index uniforms support I introduced in 9.1. v2: Move old offset computation into the pre-gen7 path. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=61554 NOTE: This is a candidate for the 9.1 branch.
2013-03-13 21:48:55 +00:00
mlen = 2;
rlen = 8;
simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
i965/fs: Add instruction emit for varying-index reads of uniforms. The gen7 send-from-GRF path is sufficiently different from the perspective of IR generation and optimization that I just made it a separate opcode. v2: fix whitespace, rebase on Ken's recent refactor.
2012-11-07 19:18:34 +00:00
} else {
i965/fs: Improve performance of varying-index uniform loads on IVB. Like we have done for the VS and for constant-index uniform loads, we use the sampler engine to get caching in front of the L3 to avoid tickling the IVB L3 bug. This is also a bit of a functional change, as we're now loading a vec4 instead of a single dword, though we're not taking advantage of the other 3 components of the vec4 (yet). With the driver hacked to always take the varying-index path for all uniforms, improves performance of my old GLSL demo by 315% +/- 2% (n=4). This a major fix for some blur shaders in compositors from the varying-index uniforms support I introduced in 9.1. v2: Move old offset computation into the pre-gen7 path. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=61554 NOTE: This is a candidate for the 9.1 branch.
2013-03-13 21:48:55 +00:00
mlen = 1;
rlen = 4;
simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
i965/fs: Add instruction emit for varying-index reads of uniforms. The gen7 send-from-GRF path is sufficiently different from the perspective of IR generation and optimization that I just made it a separate opcode. v2: fix whitespace, rebase on Ken's recent refactor.
2012-11-07 19:18:34 +00:00
}
i965/fs: Generate indirect sends for nonconstant UBO array accesses Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
2014-08-02 03:27:21 +01:00
if (index.file == BRW_IMMEDIATE_VALUE) {
i965/fs: Track the binding table size in brw_wm_prog_data. By tracking the maximum surface index used by the shader, we know just how small we can make the binding table. Since it depends entirely on the shader program, we can just compute it once at compile time, rather than at binding table emit time (which happens during drawing). v2: Store binding_table_size, rather than max_surface_index, for consistency with the VS (which needs to be able to represent 0 surfaces). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-08-15 03:49:33 +01:00
i965: Make 'dw1' and 'bits' unnamed structures in brw_reg. Generated by sed -i -e 's/\.bits\././g' *.c *.h *.cpp sed -i -e 's/dw1\.//g' *.c *.h *.cpp and then reverting changes to comments in gen7_blorp.cpp and brw_fs_generator.cpp. There wasn't any utility offered by forcing the programmer to list these to access their fields. Removing them will reduce churn in future commits. This is C11 (and gcc has apparently supported it for sometime "compatibility with other compilers") See https://gcc.gnu.org/onlinedocs/gcc/Unnamed-Fields.html Reviewed-by: Emil Velikov <emil.velikov@collabora.co.uk> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-10-23 03:41:30 +01:00
uint32_t surf_index = index.ud;
i965/fs: Generate indirect sends for nonconstant UBO array accesses Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
2014-08-02 03:27:21 +01:00
brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
i965/fs: Use the UW type for the destination of VARYING_PULL_CONSTANT_LOAD instructions Using a floating-point type doesn't usually cause hangs on my HSW, but the simulator complains about it quite a bit. Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-09-08 23:26:24 +01:00
brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
i965/fs: Generate indirect sends for nonconstant UBO array accesses Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
2014-08-02 03:27:21 +01:00
brw_set_src0(p, send, offset);
brw_set_sampler_message(p, send,
surf_index,
0, /* LD message ignores sampler unit */
GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
rlen,
mlen,
false, /* no header */
simd_mode,
0);
} else {
struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
brw_push_insn_state(p);
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
brw_set_default_access_mode(p, BRW_ALIGN_1);
/* a0.0 = surf_index & 0xff */
brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
i965: Make the brw_inst helpers take a device_info instead of a context Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 02:00:06 +01:00
brw_inst_set_exec_size(p->devinfo, insn_and, BRW_EXECUTE_1);
i965/fs: Generate indirect sends for nonconstant UBO array accesses Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
2014-08-02 03:27:21 +01:00
brw_set_dest(p, insn_and, addr);
brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
i965: Don't disable exec masking for sampler message sends. This was telling the sampler to do texture fetches for *all* channels in the non-constant surface index case, what could have reduced throughput unnecessarily when some of the channels were disabled by control flow. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2015-02-26 15:24:03 +00:00
brw_pop_insn_state(p);
i965: Factor out logic to build a send message instruction with indirect descriptor. This is going to be useful because the Gen7+ uniform and varying pull constant, texturing, typed and untyped surface read, write, and atomic generation code on the vec4 and fs back-end all require the same logic to handle conditionally indirect surface indices. In pseudocode: | if (surface.file == BRW_IMMEDIATE_VALUE) { | inst = brw_SEND(p, dst, payload); | set_descriptor_control_bits(inst, surface, ...); | } else { | inst = brw_OR(p, addr, surface, 0); | set_descriptor_control_bits(inst, ...); | inst = brw_SEND(p, dst, payload); | set_indirect_send_descriptor(inst, addr); | } This patch abstracts out this frequently recurring pattern so we can now write: | inst = brw_send_indirect_message(p, sfid, dst, payload, surface) | set_descriptor_control_bits(inst, ...); without worrying about handling the immediate and indirect surface index cases explicitly. v2: Rebase. Improve documentatation and commit message. (Topi) Preserve UW destination type cargo-cult. (Topi, Ken, Matt) Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2015-03-19 13:44:24 +00:00
/* dst = send(offset, a0.0 | <descriptor>) */
brw_inst *insn = brw_send_indirect_message(
p, BRW_SFID_SAMPLER, retype(dst, BRW_REGISTER_TYPE_UW),
offset, addr);
brw_set_sampler_message(p, insn,
i965/fs: Generate indirect sends for nonconstant UBO array accesses Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
2014-08-02 03:27:21 +01:00
0 /* surface */,
0 /* sampler */,
GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
rlen /* rlen */,
mlen /* mlen */,
false /* header */,
simd_mode,
0);
}
i965/fs: Add instruction emit for varying-index reads of uniforms. The gen7 send-from-GRF path is sufficiently different from the perspective of IR generation and optimization that I just made it a separate opcode. v2: fix whitespace, rebase on Ken's recent refactor.
2012-11-07 19:18:34 +00:00
}
i965/fs: Add FS_OPCODE_MOV_DISPATCH_TO_FLAGS to fragment shader backend. In order to compute centroid varyings correctly, the fragment shader needs to be able to load the current pixel/sample mask into a flag register. This patch adds an opcode to the fragment shader back-end to do this; the opcode gets translated into the instruction mov(1) f0<1>UW g1.14<0,1,0>UW { align1 WE_all } Since this instruction clobbers f0, instruction scheduling has to treat it the same as instructions that have a conditional modifier. Reviewed-by: Eric Anholt <eric@anholt.net>
2012-06-18 22:50:04 +01:00
/**
* Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
* into the flags register (f0.0).
*
* Used only on Gen6 and above.
*/
void
i965/fs: Add an instruction flag for choosing the flag subregister. We're going to redo discard handling to track discards in the other flag subregister, saving instructions in the discard and allowing predicated jumps out to the end of the shader. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-06 18:36:11 +00:00
fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
i965/fs: Add FS_OPCODE_MOV_DISPATCH_TO_FLAGS to fragment shader backend. In order to compute centroid varyings correctly, the fragment shader needs to be able to load the current pixel/sample mask into a flag register. This patch adds an opcode to the fragment shader back-end to do this; the opcode gets translated into the instruction mov(1) f0<1>UW g1.14<0,1,0>UW { align1 WE_all } Since this instruction clobbers f0, instruction scheduling has to treat it the same as instructions that have a conditional modifier. Reviewed-by: Eric Anholt <eric@anholt.net>
2012-06-18 22:50:04 +01:00
{
i965/fs: Add an instruction flag for choosing the flag subregister. We're going to redo discard handling to track discards in the other flag subregister, saving instructions in the discard and allowing predicated jumps out to the end of the shader. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-06 18:36:11 +00:00
struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg);
i965/fs: Rewrite discards to use a flag subreg to track discarded pixels. This makes much more sense on gen6+, and will also prove useful for early exit of shaders on discard. v2: fix up a stale comment from before converting gen4-5. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-06 20:15:13 +00:00
struct brw_reg dispatch_mask;
i965/fs: Add a devinfo field to the generator and use it for gen checks Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 01:45:40 +01:00
if (devinfo->gen >= 6)
i965/fs: Rewrite discards to use a flag subreg to track discarded pixels. This makes much more sense on gen6+, and will also prove useful for early exit of shaders on discard. v2: fix up a stale comment from before converting gen4-5. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-06 20:15:13 +00:00
dispatch_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
else
dispatch_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
i965/fs: Add FS_OPCODE_MOV_DISPATCH_TO_FLAGS to fragment shader backend. In order to compute centroid varyings correctly, the fragment shader needs to be able to load the current pixel/sample mask into a flag register. This patch adds an opcode to the fragment shader back-end to do this; the opcode gets translated into the instruction mov(1) f0<1>UW g1.14<0,1,0>UW { align1 WE_all } Since this instruction clobbers f0, instruction scheduling has to treat it the same as instructions that have a conditional modifier. Reviewed-by: Eric Anholt <eric@anholt.net>
2012-06-18 22:50:04 +01:00
brw_push_insn_state(p);
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
i965/fs: Rewrite discards to use a flag subreg to track discarded pixels. This makes much more sense on gen6+, and will also prove useful for early exit of shaders on discard. v2: fix up a stale comment from before converting gen4-5. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-06 20:15:13 +00:00
brw_MOV(p, flags, dispatch_mask);
i965/fs: Add FS_OPCODE_MOV_DISPATCH_TO_FLAGS to fragment shader backend. In order to compute centroid varyings correctly, the fragment shader needs to be able to load the current pixel/sample mask into a flag register. This patch adds an opcode to the fragment shader back-end to do this; the opcode gets translated into the instruction mov(1) f0<1>UW g1.14<0,1,0>UW { align1 WE_all } Since this instruction clobbers f0, instruction scheduling has to treat it the same as instructions that have a conditional modifier. Reviewed-by: Eric Anholt <eric@anholt.net>
2012-06-18 22:50:04 +01:00
brw_pop_insn_state(p);
}
i965/fs: add generator support for pixel interpolator query V5: - Split into separate opcodes - Pass message data in src1 immediate - Put noperspective bit in fs_inst rather than adding any junk to backend_instruction Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-18 08:13:13 +00:00
void
fs_generator::generate_pixel_interpolator_query(fs_inst *inst,
struct brw_reg dst,
struct brw_reg src,
struct brw_reg msg_data,
unsigned msg_type)
{
i965/fs: Handle non-const sample number in interpolateAtSample If a non-const sample number is given to interpolateAtSample it will now generate an indirect send message with the sample ID similar to how non-const sampler array indexing works. Previously non-const values were ignored and instead it ended up using a constant 0 value. The generator will try to determine if the sample ID is dynamically uniform via nir_src_is_dynamically_uniform. If not it will query the pixel interpolator in a loop, once for each different live sample number. The next live sample number is found using emit_uniformize. If multiple live channels have the same sample number then they will be handled in a single iteration of the loop. The loop is necessary because the indirect send message doesn't seem to have a way to specify a different value for each fragment. This fixes the following two Piglit tests: arb_gpu_shader5-interpolateAtSample-nonconst arb_gpu_shader5-interpolateAtSample-dynamically-nonuniform v2: Handle dynamically non-uniform sample ids. v3: Remove the BREAK instruction and predicate the WHILE directly. Make the tokens arrays const. (Matt Turner) v4: Iterate over the live channels instead of each possible sample number. v5: Don't special case immediate values in brw_pixel_interpolator_query. Make a better wrapper for the function to set up the PI send instruction. Ensure that the SHL instructions are scalar. (Francisco Jerez). Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2015-07-17 14:40:03 +01:00
assert(msg_data.type == BRW_REGISTER_TYPE_UD);
i965/fs: add generator support for pixel interpolator query V5: - Split into separate opcodes - Pass message data in src1 immediate - Put noperspective bit in fs_inst rather than adding any junk to backend_instruction Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-18 08:13:13 +00:00
brw_pixel_interpolator_query(p,
retype(dst, BRW_REGISTER_TYPE_UW),
src,
inst->pi_noperspective,
msg_type,
i965/fs: Handle non-const sample number in interpolateAtSample If a non-const sample number is given to interpolateAtSample it will now generate an indirect send message with the sample ID similar to how non-const sampler array indexing works. Previously non-const values were ignored and instead it ended up using a constant 0 value. The generator will try to determine if the sample ID is dynamically uniform via nir_src_is_dynamically_uniform. If not it will query the pixel interpolator in a loop, once for each different live sample number. The next live sample number is found using emit_uniformize. If multiple live channels have the same sample number then they will be handled in a single iteration of the loop. The loop is necessary because the indirect send message doesn't seem to have a way to specify a different value for each fragment. This fixes the following two Piglit tests: arb_gpu_shader5-interpolateAtSample-nonconst arb_gpu_shader5-interpolateAtSample-dynamically-nonuniform v2: Handle dynamically non-uniform sample ids. v3: Remove the BREAK instruction and predicate the WHILE directly. Make the tokens arrays const. (Matt Turner) v4: Iterate over the live channels instead of each possible sample number. v5: Don't special case immediate values in brw_pixel_interpolator_query. Make a better wrapper for the function to set up the PI send instruction. Ensure that the SHL instructions are scalar. (Francisco Jerez). Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2015-07-17 14:40:03 +01:00
msg_data,
i965/fs: add generator support for pixel interpolator query V5: - Split into separate opcodes - Pass message data in src1 immediate - Put noperspective bit in fs_inst rather than adding any junk to backend_instruction Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-18 08:13:13 +00:00
inst->mlen,
inst->regs_written);
}
i965/fs: Add FS_OPCODE_MOV_DISPATCH_TO_FLAGS to fragment shader backend. In order to compute centroid varyings correctly, the fragment shader needs to be able to load the current pixel/sample mask into a flag register. This patch adds an opcode to the fragment shader back-end to do this; the opcode gets translated into the instruction mov(1) f0<1>UW g1.14<0,1,0>UW { align1 WE_all } Since this instruction clobbers f0, instruction scheduling has to treat it the same as instructions that have a conditional modifier. Reviewed-by: Eric Anholt <eric@anholt.net>
2012-06-18 22:50:04 +01:00
i965/fs: Set up gen7 UBO loads as sends from GRFs. This gives the instruction scheduler a chance to schedule between the loads, whereas before it was restricted due to the dependencies between the MRFs for setting them up. For one shader in gles3conform, it goes from getting stuck in register allocation for as long as anybody's bothered to leave it running down to 23 seconds, thanks to the LIFO scheduling. Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-05 08:06:30 +00:00
/**
i965/fs: Switch to using sampler LD messages for uniform pull constants. When forcing the compiler to always generate pull constants instead of push constants (in order to have an easy to use testcase), improves performance of my old GLSL demo 23.3553% +/- 1.42968% (n=7). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60866 Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-06 22:47:22 +00:00
* Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
* sampler LD messages.
i965/fs: Set up gen7 UBO loads as sends from GRFs. This gives the instruction scheduler a chance to schedule between the loads, whereas before it was restricted due to the dependencies between the MRFs for setting them up. For one shader in gles3conform, it goes from getting stuck in register allocation for as long as anybody's bothered to leave it running down to 23 seconds, thanks to the LIFO scheduling. Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-05 08:06:30 +00:00
*
i965/fs: Switch to using sampler LD messages for uniform pull constants. When forcing the compiler to always generate pull constants instead of push constants (in order to have an easy to use testcase), improves performance of my old GLSL demo 23.3553% +/- 1.42968% (n=7). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60866 Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-06 22:47:22 +00:00
* We don't want to bake it into the send message's code generation because
* that means we don't get a chance to schedule the instructions.
i965/fs: Set up gen7 UBO loads as sends from GRFs. This gives the instruction scheduler a chance to schedule between the loads, whereas before it was restricted due to the dependencies between the MRFs for setting them up. For one shader in gles3conform, it goes from getting stuck in register allocation for as long as anybody's bothered to leave it running down to 23 seconds, thanks to the LIFO scheduling. Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-05 08:06:30 +00:00
*/
void
i965/fs: Switch to using sampler LD messages for uniform pull constants. When forcing the compiler to always generate pull constants instead of push constants (in order to have an easy to use testcase), improves performance of my old GLSL demo 23.3553% +/- 1.42968% (n=7). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60866 Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-06 22:47:22 +00:00
fs_generator::generate_set_simd4x2_offset(fs_inst *inst,
struct brw_reg dst,
struct brw_reg value)
i965/fs: Set up gen7 UBO loads as sends from GRFs. This gives the instruction scheduler a chance to schedule between the loads, whereas before it was restricted due to the dependencies between the MRFs for setting them up. For one shader in gles3conform, it goes from getting stuck in register allocation for as long as anybody's bothered to leave it running down to 23 seconds, thanks to the LIFO scheduling. Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-05 08:06:30 +00:00
{
assert(value.file == BRW_IMMEDIATE_VALUE);
brw_push_insn_state(p);
i965: Replace guess_execution_size with something simpler. guess_execution_size() does two things: 1. Cope with small destination registers. 2. Cope with SIMD8 vs SIMD16 mode. This patch replaces the first with a simple if block in brw_set_dest: if the destination register width is less than 8, you probably want the execution size to match. (I didn't put this in the 3src block because it doesn't seem to matter.) Since only the FS compiler cares about SIMD16 mode, it's easy to just set the default execution size there. This pattern was already been proven in the Gen8+ generator, but we didn't port it back to the existing generator when we combined the two. This is based on a patch from Ken from about a year ago. I've rebased it and and fixed a few bugs. Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-04-14 20:40:34 +01:00
brw_set_default_exec_size(p, BRW_EXECUTE_8);
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
i965/fs: Switch to using sampler LD messages for uniform pull constants. When forcing the compiler to always generate pull constants instead of push constants (in order to have an easy to use testcase), improves performance of my old GLSL demo 23.3553% +/- 1.42968% (n=7). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60866 Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-06 22:47:22 +00:00
brw_MOV(p, retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value);
i965/fs: Set up gen7 UBO loads as sends from GRFs. This gives the instruction scheduler a chance to schedule between the loads, whereas before it was restricted due to the dependencies between the MRFs for setting them up. For one shader in gles3conform, it goes from getting stuck in register allocation for as long as anybody's bothered to leave it running down to 23 seconds, thanks to the LIFO scheduling. Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-05 08:06:30 +00:00
brw_pop_insn_state(p);
}
i965: Add FS backend for builtin gl_SampleID V2: - Update comments - Add compute_sample_id variables in brw_wm_prog_key - Add a special backend instruction to compute sample_id. V3: - Make changes to support simd16 mode. Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-10-25 00:17:08 +01:00
/* Sets vstride=1, width=4, hstride=0 of register src1 during
* the ADD instruction.
*/
void
fs_generator::generate_set_sample_id(fs_inst *inst,
struct brw_reg dst,
struct brw_reg src0,
struct brw_reg src1)
{
assert(dst.type == BRW_REGISTER_TYPE_D ||
dst.type == BRW_REGISTER_TYPE_UD);
assert(src0.type == BRW_REGISTER_TYPE_D ||
src0.type == BRW_REGISTER_TYPE_UD);
i965/fs: Use type-W for immediate in SampleID setup. Not a functional difference, but register is loaded with a signed immediate (V) and added to a signed type (D) producing a signed result (D). Also change the type of g0 to allow for compaction. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2015-10-21 01:51:12 +01:00
struct brw_reg reg = stride(src1, 1, 4, 0);
i965/fs: Emit a single ADD instruction for SET_SAMPLE_ID on Gen8+. Gen8+ lifted the register region restriction that an instruction whose destination spans two registers must have sources that also span two registers. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2015-10-21 02:31:02 +01:00
if (devinfo->gen >= 8 || dispatch_width == 8) {
i965/brw_reg: Add a firsthalf function and use it in the generator Right now, this function is a no-op but it indicates that we intend to only use the first half of the 16-wide register. Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-13 20:23:47 +01:00
brw_ADD(p, dst, src0, reg);
} else if (dispatch_width == 16) {
i965/fs: Drop unnecessary write-enable-all from SET_SAMPLE_ID. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2015-10-21 02:29:42 +01:00
brw_push_insn_state(p);
brw_set_default_exec_size(p, BRW_EXECUTE_8);
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
i965/brw_reg: Add a firsthalf function and use it in the generator Right now, this function is a no-op but it indicates that we intend to only use the first half of the 16-wide register. Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-13 20:23:47 +01:00
brw_ADD(p, firsthalf(dst), firsthalf(src0), reg);
i965/fs: Drop unnecessary write-enable-all from SET_SAMPLE_ID. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2015-10-21 02:29:42 +01:00
brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
i965/brw_reg: Add a firsthalf function and use it in the generator Right now, this function is a no-op but it indicates that we intend to only use the first half of the 16-wide register. Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-13 20:23:47 +01:00
brw_ADD(p, sechalf(dst), sechalf(src0), suboffset(reg, 2));
i965/fs: Drop unnecessary write-enable-all from SET_SAMPLE_ID. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2015-10-21 02:29:42 +01:00
brw_pop_insn_state(p);
i965/brw_reg: Add a firsthalf function and use it in the generator Right now, this function is a no-op but it indicates that we intend to only use the first half of the 16-wide register. Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-13 20:23:47 +01:00
}
i965: Add FS backend for builtin gl_SampleID V2: - Update comments - Add compute_sample_id variables in brw_wm_prog_key - Add a special backend instruction to compute sample_id. V3: - Make changes to support simd16 mode. Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-10-25 00:17:08 +01:00
}
i965/fs/gen7: Emit code for GLSL 3.00 pack/unpack operations (v4) v2: Remove lewd comment. [for idr] v3: - Optimize away tmp register for packHalf2x16. [for anholt, paul] - Improve comments. [for anholt, paul] - Reduce near-duplicate code by removing vec4_visitor emit_pack/unpack methods. [for chadv] v4: Factor our UD/W register conversion into helper function. [for anholt] Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v2) Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
2013-01-09 19:46:42 +00:00
void
fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
struct brw_reg dst,
struct brw_reg x,
struct brw_reg y)
{
i965/fs: Add a devinfo field to the generator and use it for gen checks Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 01:45:40 +01:00
assert(devinfo->gen >= 7);
i965/fs/gen7: Emit code for GLSL 3.00 pack/unpack operations (v4) v2: Remove lewd comment. [for idr] v3: - Optimize away tmp register for packHalf2x16. [for anholt, paul] - Improve comments. [for anholt, paul] - Reduce near-duplicate code by removing vec4_visitor emit_pack/unpack methods. [for chadv] v4: Factor our UD/W register conversion into helper function. [for anholt] Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v2) Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
2013-01-09 19:46:42 +00:00
assert(dst.type == BRW_REGISTER_TYPE_UD);
i965: Fix assignment instead of comparison in asserts. Fixes side effect in assertion defects reported by Coverity. Note: This is a candidate for the 9.1 branch. Signed-off-by: Vinson Lee <vlee@freedesktop.org> Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
2013-01-26 07:27:50 +00:00
assert(x.type == BRW_REGISTER_TYPE_F);
assert(y.type == BRW_REGISTER_TYPE_F);
i965/fs/gen7: Emit code for GLSL 3.00 pack/unpack operations (v4) v2: Remove lewd comment. [for idr] v3: - Optimize away tmp register for packHalf2x16. [for anholt, paul] - Improve comments. [for anholt, paul] - Reduce near-duplicate code by removing vec4_visitor emit_pack/unpack methods. [for chadv] v4: Factor our UD/W register conversion into helper function. [for anholt] Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v2) Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
2013-01-09 19:46:42 +00:00
/* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
*
* Because this instruction does not have a 16-bit floating-point type,
* the destination data type must be Word (W).
*
* The destination must be DWord-aligned and specify a horizontal stride
* (HorzStride) of 2. The 16-bit result is stored in the lower word of
* each destination channel and the upper word is not modified.
*/
i965/fs: Replace ud_reg_to_w() with a more general helper function. Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-02-04 15:58:49 +00:00
struct brw_reg dst_w = spread(retype(dst, BRW_REGISTER_TYPE_W), 2);
i965/fs/gen7: Emit code for GLSL 3.00 pack/unpack operations (v4) v2: Remove lewd comment. [for idr] v3: - Optimize away tmp register for packHalf2x16. [for anholt, paul] - Improve comments. [for anholt, paul] - Reduce near-duplicate code by removing vec4_visitor emit_pack/unpack methods. [for chadv] v4: Factor our UD/W register conversion into helper function. [for anholt] Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v2) Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
2013-01-09 19:46:42 +00:00
i965/fs: Replace ud_reg_to_w() with a more general helper function. Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-02-04 15:58:49 +00:00
/* Give each 32-bit channel of dst the form below, where "." means
i965/fs/gen7: Emit code for GLSL 3.00 pack/unpack operations (v4) v2: Remove lewd comment. [for idr] v3: - Optimize away tmp register for packHalf2x16. [for anholt, paul] - Improve comments. [for anholt, paul] - Reduce near-duplicate code by removing vec4_visitor emit_pack/unpack methods. [for chadv] v4: Factor our UD/W register conversion into helper function. [for anholt] Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v2) Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
2013-01-09 19:46:42 +00:00
* unchanged.
* 0x....hhhh
*/
brw_F32TO16(p, dst_w, y);
/* Now the form:
* 0xhhhh0000
*/
brw_SHL(p, dst, dst, brw_imm_ud(16u));
/* And, finally the form of packHalf2x16's output:
* 0xhhhhllll
*/
brw_F32TO16(p, dst_w, x);
}
void
fs_generator::generate_unpack_half_2x16_split(fs_inst *inst,
struct brw_reg dst,
struct brw_reg src)
{
i965/fs: Add a devinfo field to the generator and use it for gen checks Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 01:45:40 +01:00
assert(devinfo->gen >= 7);
i965/fs/gen7: Emit code for GLSL 3.00 pack/unpack operations (v4) v2: Remove lewd comment. [for idr] v3: - Optimize away tmp register for packHalf2x16. [for anholt, paul] - Improve comments. [for anholt, paul] - Reduce near-duplicate code by removing vec4_visitor emit_pack/unpack methods. [for chadv] v4: Factor our UD/W register conversion into helper function. [for anholt] Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v2) Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
2013-01-09 19:46:42 +00:00
assert(dst.type == BRW_REGISTER_TYPE_F);
assert(src.type == BRW_REGISTER_TYPE_UD);
/* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
*
* Because this instruction does not have a 16-bit floating-point type,
* the source data type must be Word (W). The destination type must be
* F (Float).
*/
i965/fs: Replace ud_reg_to_w() with a more general helper function. Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-02-04 15:58:49 +00:00
struct brw_reg src_w = spread(retype(src, BRW_REGISTER_TYPE_W), 2);
i965/fs/gen7: Emit code for GLSL 3.00 pack/unpack operations (v4) v2: Remove lewd comment. [for idr] v3: - Optimize away tmp register for packHalf2x16. [for anholt, paul] - Improve comments. [for anholt, paul] - Reduce near-duplicate code by removing vec4_visitor emit_pack/unpack methods. [for chadv] v4: Factor our UD/W register conversion into helper function. [for anholt] Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v2) Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
2013-01-09 19:46:42 +00:00
/* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
* For the Y case, we wish to access only the upper word; therefore
* a 16-bit subregister offset is needed.
*/
assert(inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X ||
inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y);
if (inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y)
i965/fs/gen7: Fix fatal typo in unpackHalf2x16 s/src/src_w/ That little typo, which sneaked into v4 of the previous patch, generates incorrect fs code. Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
2013-01-25 05:48:40 +00:00
src_w.subnr += 2;
i965/fs/gen7: Emit code for GLSL 3.00 pack/unpack operations (v4) v2: Remove lewd comment. [for idr] v3: - Optimize away tmp register for packHalf2x16. [for anholt, paul] - Improve comments. [for anholt, paul] - Reduce near-duplicate code by removing vec4_visitor emit_pack/unpack methods. [for chadv] v4: Factor our UD/W register conversion into helper function. [for anholt] Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v2) Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
2013-01-09 19:46:42 +00:00
brw_F16TO32(p, dst, src_w);
}
i965/fs: Switch shader_time writes to using GRFs. This avoids conflicts between shader_time and FB writes, so we can include more of the program under our profiling. This does mean hiding more of the message setup from the optimizer, which doesn't have a way to handle multi-reg sends from GRFs. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-19 22:28:11 +00:00
void
fs_generator::generate_shader_time_add(fs_inst *inst,
struct brw_reg payload,
struct brw_reg offset,
struct brw_reg value)
{
i965/fs: Add a devinfo field to the generator and use it for gen checks Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 01:45:40 +01:00
assert(devinfo->gen >= 7);
i965/fs: Switch shader_time writes to using GRFs. This avoids conflicts between shader_time and FB writes, so we can include more of the program under our profiling. This does mean hiding more of the message setup from the optimizer, which doesn't have a way to handle multi-reg sends from GRFs. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-19 22:28:11 +00:00
brw_push_insn_state(p);
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_mask_control(p, true);
i965/fs: Switch shader_time writes to using GRFs. This avoids conflicts between shader_time and FB writes, so we can include more of the program under our profiling. This does mean hiding more of the message setup from the optimizer, which doesn't have a way to handle multi-reg sends from GRFs. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-19 22:28:11 +00:00
assert(payload.file == BRW_GENERAL_REGISTER_FILE);
struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0),
offset.type);
struct brw_reg payload_value = retype(brw_vec1_grf(payload.nr + 1, 0),
value.type);
assert(offset.file == BRW_IMMEDIATE_VALUE);
if (value.file == BRW_GENERAL_REGISTER_FILE) {
value.width = BRW_WIDTH_1;
value.hstride = BRW_HORIZONTAL_STRIDE_0;
value.vstride = BRW_VERTICAL_STRIDE_0;
} else {
assert(value.file == BRW_IMMEDIATE_VALUE);
}
/* Trying to deal with setup of the params from the IR is crazy in the FS8
* case, and we don't really care about squeezing every bit of performance
* out of this path, so we just emit the MOVs from here.
*/
brw_MOV(p, payload_offset, offset);
brw_MOV(p, payload_value, value);
i965: Make a brw_stage_prog_data for storing the SURF_INDEX information. It would be nice to be able to pack our binding table so that programs that use 1 render target don't upload an extra BRW_MAX_DRAW_BUFFERS - 1 binding table entries. To do that, we need the compiled program to have information on where its surfaces go. v2: Rename size to size_bytes to be more explicit. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-10-02 22:07:40 +01:00
brw_shader_time_add(p, payload,
i965/fs: Remove direct fs_generator brw_wm_prog_data dependence Instead we store a brw_stage_prog_data pointer, and cast it to brw_wm_prog_data for fragment shader specific code paths. Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-29 20:50:46 +01:00
prog_data->binding_table.shader_time_start);
i965/fs: Switch shader_time writes to using GRFs. This avoids conflicts between shader_time and FB writes, so we can include more of the program under our profiling. This does mean hiding more of the message setup from the optimizer, which doesn't have a way to handle multi-reg sends from GRFs. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-19 22:28:11 +00:00
brw_pop_insn_state(p);
i965/fs: Track the binding table size in brw_wm_prog_data. By tracking the maximum surface index used by the shader, we know just how small we can make the binding table. Since it depends entirely on the shader program, we can just compute it once at compile time, rather than at binding table emit time (which happens during drawing). v2: Store binding_table_size, rather than max_surface_index, for consistency with the VS (which needs to be able to represent 0 surfaces). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-08-15 03:49:33 +01:00
i965/fs: Remove direct fs_generator brw_wm_prog_data dependence Instead we store a brw_stage_prog_data pointer, and cast it to brw_wm_prog_data for fragment shader specific code paths. Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-29 20:50:46 +01:00
brw_mark_surface_used(prog_data,
prog_data->binding_table.shader_time_start);
i965/fs: Switch shader_time writes to using GRFs. This avoids conflicts between shader_time and FB writes, so we can include more of the program under our profiling. This does mean hiding more of the message setup from the optimizer, which doesn't have a way to handle multi-reg sends from GRFs. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-19 22:28:11 +00:00
}
i965: Set shader name for generator from call site fs_generator no longer knows what stage it's generating code for, so we have to set the debug name of the shader from the call site. Signed-off-by: Kristian Høgsberg <krh@bitplanet.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-10-28 02:40:47 +00:00
void
fs_generator::enable_debug(const char *shader_name)
{
debug_flag = true;
this->shader_name = shader_name;
}
i965: Refactor fs_generator API We split out SIMD8 and SIMD16 generation into seperate calls to new method generate_code(), which returns the start offset for the generated code. A new get_assembly() method returns the generated code. This avoids asserting MESA_SHADER_FRAGMENT and accessing wm_prog_data in the generator. Signed-off-by: Kristian Høgsberg <krh@bitplanet.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-11-14 00:28:08 +00:00
int
fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
{
i965: Refactor fs_generator API We split out SIMD8 and SIMD16 generation into seperate calls to new method generate_code(), which returns the start offset for the generated code. A new get_assembly() method returns the generated code. This avoids asserting MESA_SHADER_FRAGMENT and accessing wm_prog_data in the generator. Signed-off-by: Kristian Høgsberg <krh@bitplanet.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-11-14 00:28:08 +00:00
/* align to 64 byte boundary. */
while (p->next_insn_offset % 64)
brw_NOP(p);
this->dispatch_width = dispatch_width;
if (dispatch_width == 16)
brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
i965: Move annotation info into generate code. Suggested by Ken as a way to cut down lines of code. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-25 18:42:32 +01:00
int start_offset = p->next_insn_offset;
i965/fs: Print spills:fills and number of promoted constants. Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2015-03-16 19:18:31 +00:00
int spill_count = 0, fill_count = 0;
i965/vec4/fs: Count loops in shader debug Reviewed-by: Matt Turner <mattst88@gmail.com> Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
2014-08-06 09:27:58 +01:00
int loop_count = 0;
i965: Move annotation info into generate code. Suggested by Ken as a way to cut down lines of code. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-25 18:42:32 +01:00
struct annotation_info annotation;
memset(&annotation, 0, sizeof(annotation));
i965: Pass a cfg pointer to generate_{code,assembly}. The loop over all instructions is now two-fold, over all of the blocks and all of the instructions in each block. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-07-12 05:16:13 +01:00
foreach_block_and_inst (block, fs_inst, inst, cfg) {
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
struct brw_reg src[3], dst;
i965: Don't use brw_set_conditionalmod in the FS and vec4 compilers. brw_set_conditionalmod and brw_next_insn work together to set the conditional modifier for the next instruction, then turn it off. The Gen8+ generators don't implement this: we just set it for all future instructions, and whack it for each fs_inst/vec4_instruction. Both approaches work out because we only set conditional_mod on IR instructions like CMP, AND, and so on, which correspond to exactly one assembly instruction. The Gen8 generators would break if we had an IR instruction that generated multiple instructions, and the Gen4-7 EU emit layer would do...something. To safeguard against this, assert that we only generated one instruction if conditional_mod is set, and just set the flag directly on that instruction rather than altering default state. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-05-31 00:41:32 +01:00
unsigned int last_insn_offset = p->next_insn_offset;
i965/fs: Apply conditional mod specially to split MAD/LRP. Otherwise we'll apply the conditional mod to only one of SIMD8 instructions and trigger an assertion. NoDDClr/NoDDChk have the same problem but we never apply those to these instructions, so I'm leaving them for a later time. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-12-30 20:56:13 +00:00
bool multiple_instructions_emitted = false;
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
i965/fs: Don't follow pow with an instruction with two dest regs. Beginning with commit 7b208a73, Unigine Valley began hanging the GPU on Gen >= 8 platforms. Evidently that commit allowed the scheduler to make different choices that somehow finally ran afoul of a hardware bug in which POW and FDIV instructions may not be followed by an instruction with two destination registers (including compressed instructions). I presume the conditions are more complex than that, but the internal hardware bug report (BDWGFX bug_de 1696294) does not contain much more information. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94924 Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> [v1] Tested-by: Mark Janes <mark.a.janes@intel.com> [v1] Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2016-05-03 07:32:13 +01:00
/* From the Broadwell PRM, Volume 7, "3D-Media-GPGPU", in the
* "Register Region Restrictions" section: for BDW, SKL:
*
* "A POW/FDIV operation must not be followed by an instruction
* that requires two destination registers."
*
* The documentation is often lacking annotations for Atom parts,
* and empirically this affects CHV as well.
*/
if (devinfo->gen >= 8 &&
p->nr_insn > 1 &&
brw_inst_opcode(devinfo, brw_last_inst) == BRW_OPCODE_MATH &&
brw_inst_math_function(devinfo, brw_last_inst) == BRW_MATH_FUNCTION_POW &&
inst->dst.component_size(inst->exec_size) > REG_SIZE) {
brw_NOP(p);
last_insn_offset = p->next_insn_offset;
}
i965: Print disassembly after compaction. Reviewed-by: Eric Anholt <eric@anholt.net>
2014-05-19 18:20:37 +01:00
if (unlikely(debug_flag))
i965: Make the annotation code take a device_info instead of a context Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 23:01:25 +01:00
annotate(p->devinfo, &annotation, cfg, inst, p->next_insn_offset);
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
i965/fs: Use instruction execution sizes to set compression state Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-16 04:58:50 +01:00
switch (inst->exec_size) {
case 1:
case 2:
case 4:
Revert "i965/fs: Remove force_writemask_all assertion for execsize < 8." This reverts commit 0d8f27eab7b7e8b7a16e76aabd3f6a0ab4880497. "This doesn't seem to be necessary." <- I was wrong! Tested-by: Markus Wick <markus@selfnet.de> Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2015-02-24 20:11:21 +00:00
assert(inst->force_writemask_all);
i965/fs: Use instruction execution sizes to set compression state Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-16 04:58:50 +01:00
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
break;
case 8:
if (inst->force_sechalf) {
brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
} else {
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
}
break;
case 16:
i965/fs: Allow an execution size of 32. In a few commits, we'll start emitting an add(32) instruction on some platforms. Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-04-04 01:44:06 +01:00
case 32:
i965/fs: Rework compression control selection. The next commit uses an add(16) with a UW destination with a stride of 2, which needs compression control since it's writing two registers. The old code would have failed to set compression control correctly. Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-05-14 23:58:20 +01:00
/* If the instruction writes to more than one register, it needs to
* be a "compressed" instruction on Gen <= 5.
*/
i965/fs: Factor out universally broken calculation of the register component size. This in principle simple calculation was being open-coded in a number of places (in a series I haven't yet sent for review there will be a couple more), all of them were subtly broken in one way or another: None of them were handling the HW_REG case correctly as pointed out by Connor, and fs_inst::regs_read() was handling the stride=0 case rather naively. This patch solves both problems and factors out the calculation as a new fs_reg method. Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-07-14 13:43:44 +01:00
if (inst->dst.component_size(inst->exec_size) > REG_SIZE)
i965/fs: Set compression only if writing two registers. We don't want to set compression control on a SIMD16 instruction operating on words or smaller. Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-04-11 22:51:13 +01:00
brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
i965/fs: Rework compression control selection. The next commit uses an add(16) with a UW destination with a stride of 2, which needs compression control since it's writing two registers. The old code would have failed to set compression control correctly. Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-05-14 23:58:20 +01:00
else
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
i965/fs: Use instruction execution sizes to set compression state Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-16 04:58:50 +01:00
break;
default:
i965/generator: Get rid of the ! in the unreachable statement Reviewed-by: Mark Janes <mark.a.janes@intel.com>
2015-04-02 00:18:31 +01:00
unreachable("Invalid instruction width");
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
}
i965: Move compression decisions before brw_reg_from_fs_reg(). brw_reg_from_fs_reg() needs to know whether the instruction will be compressed or not. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95370 Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-05-16 23:09:17 +01:00
for (unsigned int i = 0; i < inst->sources; i++) {
i965: Make brw_reg_from_fs_reg() halve exec_size when compressed. In a5d7e144eaf43fee37e6ff9e2de194407087632b, Connor generalized the exec_size halving code to handle more cases. As part of this, he made it not halve anything if the region accessed falls completely in a single register. Unfortunately, it started producing some invalid regions: -add(16) g6<1>F g10<8,8,1>UW -g1<0,1,0>F { align1 compr }; -add(16) g8<1>F g12<8,8,1>UW -g1.1<0,1,0>F { align1 compr }; +add(16) g6<1>F g10<16,16,1>UW -g1<0,1,0>F { align1 compr }; +add(16) g8<1>F g12<16,16,1>UW -g1.1<0,1,0>F { align1 compr }; Here, the UW source region completely fits within a register. However, we have to use instruction compression because the destination region spans two registers. <16,16,1> is invalid because it's compressed. To handle this, skip the "everything fits in one register" case and fall through to the exec_size halving case when compressed. Fixes hundreds of Piglit regressions on GM965. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95370 Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-05-13 07:04:10 +01:00
src[i] = brw_reg_from_fs_reg(p, inst, &inst->src[i], devinfo->gen);
i965: Move compression decisions before brw_reg_from_fs_reg(). brw_reg_from_fs_reg() needs to know whether the instruction will be compressed or not. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95370 Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-05-16 23:09:17 +01:00
/* The accumulator result appears to get used for the
* conditional modifier generation. When negating a UD
* value, there is a 33rd bit generated for the sign in the
* accumulator value, so now you can't check, for example,
* equality with a 32-bit value. See piglit fs-op-neg-uvec4.
*/
assert(!inst->conditional_mod ||
inst->src[i].type != BRW_REGISTER_TYPE_UD ||
!inst->src[i].negate);
}
i965: Make brw_reg_from_fs_reg() halve exec_size when compressed. In a5d7e144eaf43fee37e6ff9e2de194407087632b, Connor generalized the exec_size halving code to handle more cases. As part of this, he made it not halve anything if the region accessed falls completely in a single register. Unfortunately, it started producing some invalid regions: -add(16) g6<1>F g10<8,8,1>UW -g1<0,1,0>F { align1 compr }; -add(16) g8<1>F g12<8,8,1>UW -g1.1<0,1,0>F { align1 compr }; +add(16) g6<1>F g10<16,16,1>UW -g1<0,1,0>F { align1 compr }; +add(16) g8<1>F g12<16,16,1>UW -g1.1<0,1,0>F { align1 compr }; Here, the UW source region completely fits within a register. However, we have to use instruction compression because the destination region spans two registers. <16,16,1> is invalid because it's compressed. To handle this, skip the "everything fits in one register" case and fall through to the exec_size halving case when compressed. Fixes hundreds of Piglit regressions on GM965. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95370 Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-05-13 07:04:10 +01:00
dst = brw_reg_from_fs_reg(p, inst, &inst->dst, devinfo->gen);
i965: Move compression decisions before brw_reg_from_fs_reg(). brw_reg_from_fs_reg() needs to know whether the instruction will be compressed or not. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95370 Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-05-16 23:09:17 +01:00
i965/fs: Set default access mode to Align1 for all instructions in the generator. Currently the generator code for most opcodes honours the default access mode (which should typically be Align1 in the scalar back-end), but generate_code() doesn't set it explicitly which means that the access mode from a previous instruction could leak into the following ones if you did something special and weren't careful enough to save and restore the previous access mode. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-05-19 02:41:28 +01:00
brw_set_default_access_mode(p, BRW_ALIGN_1);
i965: Move compression decisions before brw_reg_from_fs_reg(). brw_reg_from_fs_reg() needs to know whether the instruction will be compressed or not. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95370 Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-05-16 23:09:17 +01:00
brw_set_default_predicate_control(p, inst->predicate);
brw_set_default_predicate_inverse(p, inst->predicate_inverse);
brw_set_default_flag_reg(p, 0, inst->flag_subreg);
brw_set_default_saturate(p, inst->saturate);
brw_set_default_mask_control(p, inst->force_writemask_all);
brw_set_default_acc_write_control(p, inst->writes_accumulator);
brw_set_default_exec_size(p, cvt(inst->exec_size) - 1);
assert(inst->base_mrf + inst->mlen <= BRW_MAX_MRF(devinfo->gen));
assert(inst->mlen <= BRW_MAX_MSG_LENGTH);
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
switch (inst->opcode) {
case BRW_OPCODE_MOV:
brw_MOV(p, dst, src[0]);
break;
case BRW_OPCODE_ADD:
brw_ADD(p, dst, src[0], src[1]);
break;
case BRW_OPCODE_MUL:
brw_MUL(p, dst, src[0], src[1]);
break;
i965/fs: add support for BRW_OPCODE_AVG in fs_generator Needed for compiling blorp blit programs. Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-12-17 14:39:16 +00:00
case BRW_OPCODE_AVG:
brw_AVG(p, dst, src[0], src[1]);
break;
i965/fs: Fix 32-bit integer multiplication. The MUL opcode does a 16bit * 32bit multiply, and we need to do the MACH to get the top 16bit * 32bit added in. Fixes fs-op-mult-int-*, fs-op-mult-ivec* Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-16 06:36:18 +01:00
case BRW_OPCODE_MACH:
brw_MACH(p, dst, src[0], src[1]);
break;
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
i965/fs: Add support for generating the LINE instruction. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-04-02 01:25:12 +01:00
case BRW_OPCODE_LINE:
brw_LINE(p, dst, src[0], src[1]);
break;
i965/fs: Add support for generating MADs. Improves nexuiz performance 0.65% +/- .10% (n=5) on my gen6, and .39% +/- .11% (n=10) on gen7. No statistically significant performance difference on warsow (n=5, but only one shader has MADs). v2: Add support for MADs in 16-wide by using compression control. v3: Don't generate MADs when it will force an immediate to be moved to a temp. (it's not clear whether this is a win or not, but it should result in less questionable change to codegen compared to v2). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v2)
2012-02-06 23:59:11 +00:00
case BRW_OPCODE_MAD:
i965/fs: Add a devinfo field to the generator and use it for gen checks Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 01:45:40 +01:00
assert(devinfo->gen >= 6);
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_access_mode(p, BRW_ALIGN_16);
i965/fs: Drop lowering code for a few three-source instructions from the generator. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-05-18 03:51:50 +01:00
brw_MAD(p, dst, src[0], src[1], src[2]);
i965/fs: Add support for generating MADs. Improves nexuiz performance 0.65% +/- .10% (n=5) on my gen6, and .39% +/- .11% (n=10) on gen7. No statistically significant performance difference on warsow (n=5, but only one shader has MADs). v2: Add support for MADs in 16-wide by using compression control. v3: Don't generate MADs when it will force an immediate to be moved to a temp. (it's not clear whether this is a win or not, but it should result in less questionable change to codegen compared to v2). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v2)
2012-02-06 23:59:11 +00:00
break;
i965/fs: Use the LRP instruction for ir_triop_lrp when possible. v2 [mattst88]: - Add BRW_OPCODE_LRP to list of CSE-able expressions. - Fix op_var[] array size. - Rename arguments to emit_lrp to (x, y, a) to clear confusion. - Add LRP function to brw_fs.cpp/.h. - Corrected comment about LRP instruction arguments in emit_lrp. v3 [mattst88]: - Duplicate MAD code for LRP instead of using a function pointer. - Check for != GRF instead of == IMM in emit_lrp. - Lower LRP on gen < 6. Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> 1
2012-12-02 08:08:15 +00:00
case BRW_OPCODE_LRP:
i965/fs: Add a devinfo field to the generator and use it for gen checks Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 01:45:40 +01:00
assert(devinfo->gen >= 6);
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_access_mode(p, BRW_ALIGN_16);
i965/fs: Drop lowering code for a few three-source instructions from the generator. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-05-18 03:51:50 +01:00
brw_LRP(p, dst, src[0], src[1], src[2]);
i965/fs: Use the LRP instruction for ir_triop_lrp when possible. v2 [mattst88]: - Add BRW_OPCODE_LRP to list of CSE-able expressions. - Fix op_var[] array size. - Rename arguments to emit_lrp to (x, y, a) to clear confusion. - Add LRP function to brw_fs.cpp/.h. - Corrected comment about LRP instruction arguments in emit_lrp. v3 [mattst88]: - Duplicate MAD code for LRP instead of using a function pointer. - Check for != GRF instead of == IMM in emit_lrp. - Lower LRP on gen < 6. Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> 1
2012-12-02 08:08:15 +00:00
break;
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
case BRW_OPCODE_FRC:
brw_FRC(p, dst, src[0]);
break;
case BRW_OPCODE_RNDD:
brw_RNDD(p, dst, src[0]);
break;
case BRW_OPCODE_RNDE:
brw_RNDE(p, dst, src[0]);
break;
case BRW_OPCODE_RNDZ:
brw_RNDZ(p, dst, src[0]);
break;
case BRW_OPCODE_AND:
brw_AND(p, dst, src[0], src[1]);
break;
case BRW_OPCODE_OR:
brw_OR(p, dst, src[0], src[1]);
break;
case BRW_OPCODE_XOR:
brw_XOR(p, dst, src[0], src[1]);
break;
case BRW_OPCODE_NOT:
brw_NOT(p, dst, src[0]);
break;
case BRW_OPCODE_ASR:
brw_ASR(p, dst, src[0], src[1]);
break;
case BRW_OPCODE_SHR:
brw_SHR(p, dst, src[0], src[1]);
break;
case BRW_OPCODE_SHL:
brw_SHL(p, dst, src[0], src[1]);
break;
i965/fs/gen7: Emit code for GLSL 3.00 pack/unpack operations (v4) v2: Remove lewd comment. [for idr] v3: - Optimize away tmp register for packHalf2x16. [for anholt, paul] - Improve comments. [for anholt, paul] - Reduce near-duplicate code by removing vec4_visitor emit_pack/unpack methods. [for chadv] v4: Factor our UD/W register conversion into helper function. [for anholt] Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v2) Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
2013-01-09 19:46:42 +00:00
case BRW_OPCODE_F32TO16:
i965/fs: Add a devinfo field to the generator and use it for gen checks Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 01:45:40 +01:00
assert(devinfo->gen >= 7);
i965/fs/gen7: Emit code for GLSL 3.00 pack/unpack operations (v4) v2: Remove lewd comment. [for idr] v3: - Optimize away tmp register for packHalf2x16. [for anholt, paul] - Improve comments. [for anholt, paul] - Reduce near-duplicate code by removing vec4_visitor emit_pack/unpack methods. [for chadv] v4: Factor our UD/W register conversion into helper function. [for anholt] Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v2) Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
2013-01-09 19:46:42 +00:00
brw_F32TO16(p, dst, src[0]);
break;
case BRW_OPCODE_F16TO32:
i965/fs: Add a devinfo field to the generator and use it for gen checks Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 01:45:40 +01:00
assert(devinfo->gen >= 7);
i965/fs/gen7: Emit code for GLSL 3.00 pack/unpack operations (v4) v2: Remove lewd comment. [for idr] v3: - Optimize away tmp register for packHalf2x16. [for anholt, paul] - Improve comments. [for anholt, paul] - Reduce near-duplicate code by removing vec4_visitor emit_pack/unpack methods. [for chadv] v4: Factor our UD/W register conversion into helper function. [for anholt] Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v2) Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
2013-01-09 19:46:42 +00:00
brw_F16TO32(p, dst, src[0]);
break;
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
case BRW_OPCODE_CMP:
i965/fs: Drop Gen7 CMP SIMD unrolling workaround from the generator. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-05-18 03:59:18 +01:00
if (inst->exec_size >= 16 && devinfo->gen == 7 && !devinfo->is_haswell &&
dst.file == BRW_ARCHITECTURE_REGISTER_FILE) {
/* For unknown reasons the WaCMPInstFlagDepClearedEarly workaround
* implemented in the compiler is not sufficient. Overriding the
* type when the destination is the null register is necessary but
* not sufficient by itself.
*/
assert(dst.nr == BRW_ARF_NULL);
dst.type = BRW_REGISTER_TYPE_D;
i965/fs: Implement the WaCMPInstFlagDepClearedEarly work-around. Prevents piglit regressions from the next patch. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-02-04 01:38:49 +00:00
}
i965/fs: Drop Gen7 CMP SIMD unrolling workaround from the generator. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-05-18 03:59:18 +01:00
brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
break;
case BRW_OPCODE_SEL:
brw_SEL(p, dst, src[0], src[1]);
break;
i965/fs: Add support for bit instructions. Don't bother scalarizing ir_binop_bfm, since its results are identical for all channels. v2: Subtract result of FBH from 31 (unless an error) to convert MSB counts to LSB counts. v3: Use op0->clone() in ir_triop_bfi to prevent (var_ref channel_expressions) from appearing multiple times in the IR. Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v2]
2013-04-10 03:22:34 +01:00
case BRW_OPCODE_BFREV:
i965/fs: Add a devinfo field to the generator and use it for gen checks Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 01:45:40 +01:00
assert(devinfo->gen >= 7);
i965/fs: Add support for bit instructions. Don't bother scalarizing ir_binop_bfm, since its results are identical for all channels. v2: Subtract result of FBH from 31 (unless an error) to convert MSB counts to LSB counts. v3: Use op0->clone() in ir_triop_bfi to prevent (var_ref channel_expressions) from appearing multiple times in the IR. Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v2]
2013-04-10 03:22:34 +01:00
/* BFREV only supports UD type for src and dst. */
brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
retype(src[0], BRW_REGISTER_TYPE_UD));
break;
case BRW_OPCODE_FBH:
i965/fs: Add a devinfo field to the generator and use it for gen checks Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 01:45:40 +01:00
assert(devinfo->gen >= 7);
i965/fs: Add support for bit instructions. Don't bother scalarizing ir_binop_bfm, since its results are identical for all channels. v2: Subtract result of FBH from 31 (unless an error) to convert MSB counts to LSB counts. v3: Use op0->clone() in ir_triop_bfi to prevent (var_ref channel_expressions) from appearing multiple times in the IR. Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v2]
2013-04-10 03:22:34 +01:00
/* FBH only supports UD type for dst. */
brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
break;
case BRW_OPCODE_FBL:
i965/fs: Add a devinfo field to the generator and use it for gen checks Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 01:45:40 +01:00
assert(devinfo->gen >= 7);
i965/fs: Add support for bit instructions. Don't bother scalarizing ir_binop_bfm, since its results are identical for all channels. v2: Subtract result of FBH from 31 (unless an error) to convert MSB counts to LSB counts. v3: Use op0->clone() in ir_triop_bfi to prevent (var_ref channel_expressions) from appearing multiple times in the IR. Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v2]
2013-04-10 03:22:34 +01:00
/* FBL only supports UD type for dst. */
brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
break;
case BRW_OPCODE_CBIT:
i965/fs: Add a devinfo field to the generator and use it for gen checks Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 01:45:40 +01:00
assert(devinfo->gen >= 7);
i965/fs: Add support for bit instructions. Don't bother scalarizing ir_binop_bfm, since its results are identical for all channels. v2: Subtract result of FBH from 31 (unless an error) to convert MSB counts to LSB counts. v3: Use op0->clone() in ir_triop_bfi to prevent (var_ref channel_expressions) from appearing multiple times in the IR. Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v2]
2013-04-10 03:22:34 +01:00
/* CBIT only supports UD type for dst. */
brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
break;
i965: Generate code for ir_binop_carry and ir_binop_borrow. Using the ADDC and SUBB instructions on Gen7. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-09-19 21:01:08 +01:00
case BRW_OPCODE_ADDC:
i965/fs: Add a devinfo field to the generator and use it for gen checks Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 01:45:40 +01:00
assert(devinfo->gen >= 7);
i965: Generate code for ir_binop_carry and ir_binop_borrow. Using the ADDC and SUBB instructions on Gen7. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-09-19 21:01:08 +01:00
brw_ADDC(p, dst, src[0], src[1]);
break;
case BRW_OPCODE_SUBB:
i965/fs: Add a devinfo field to the generator and use it for gen checks Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 01:45:40 +01:00
assert(devinfo->gen >= 7);
i965: Generate code for ir_binop_carry and ir_binop_borrow. Using the ADDC and SUBB instructions on Gen7. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-09-19 21:01:08 +01:00
brw_SUBB(p, dst, src[0], src[1]);
break;
i965/fs: Add support for the MAC instruction. This allows us to generate the MAC (multiply-accumulate) instruction, which can be used to implement some expressions in fewer instructions than doing a series of MUL and ADDs. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
2014-03-28 13:28:32 +00:00
case BRW_OPCODE_MAC:
brw_MAC(p, dst, src[0], src[1]);
break;
i965/fs: Add support for bit instructions. Don't bother scalarizing ir_binop_bfm, since its results are identical for all channels. v2: Subtract result of FBH from 31 (unless an error) to convert MSB counts to LSB counts. v3: Use op0->clone() in ir_triop_bfi to prevent (var_ref channel_expressions) from appearing multiple times in the IR. Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v2]
2013-04-10 03:22:34 +01:00
case BRW_OPCODE_BFE:
i965/fs: Add a devinfo field to the generator and use it for gen checks Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 01:45:40 +01:00
assert(devinfo->gen >= 7);
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_access_mode(p, BRW_ALIGN_16);
i965/fs: Drop lowering code for a few three-source instructions from the generator. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-05-18 03:51:50 +01:00
brw_BFE(p, dst, src[0], src[1], src[2]);
i965/fs: Add support for bit instructions. Don't bother scalarizing ir_binop_bfm, since its results are identical for all channels. v2: Subtract result of FBH from 31 (unless an error) to convert MSB counts to LSB counts. v3: Use op0->clone() in ir_triop_bfi to prevent (var_ref channel_expressions) from appearing multiple times in the IR. Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v2]
2013-04-10 03:22:34 +01:00
break;
case BRW_OPCODE_BFI1:
i965/fs: Add a devinfo field to the generator and use it for gen checks Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 01:45:40 +01:00
assert(devinfo->gen >= 7);
i965/fs: Don't emit SIMD16 BFI instructions. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-16 21:16:50 +00:00
/* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
* should
*
* "Force BFI instructions to be executed always in SIMD8."
*/
i965/fs: Add a devinfo field to the generator and use it for gen checks Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 01:45:40 +01:00
if (dispatch_width == 16 && devinfo->is_haswell) {
i965: Replace guess_execution_size with something simpler. guess_execution_size() does two things: 1. Cope with small destination registers. 2. Cope with SIMD8 vs SIMD16 mode. This patch replaces the first with a simple if block in brw_set_dest: if the destination register width is less than 8, you probably want the execution size to match. (I didn't put this in the 3src block because it doesn't seem to matter.) Since only the FS compiler cares about SIMD16 mode, it's easy to just set the default execution size there. This pattern was already been proven in the Gen8+ generator, but we didn't port it back to the existing generator when we combined the two. This is based on a patch from Ken from about a year ago. I've rebased it and and fixed a few bugs. Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-04-14 20:40:34 +01:00
brw_set_default_exec_size(p, BRW_EXECUTE_8);
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
i965/brw_reg: Add a firsthalf function and use it in the generator Right now, this function is a no-op but it indicates that we intend to only use the first half of the 16-wide register. Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-13 20:23:47 +01:00
brw_BFI1(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]));
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
i965/fs: Don't emit SIMD16 BFI instructions. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-16 21:16:50 +00:00
brw_BFI1(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]));
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
i965/fs: Don't emit SIMD16 BFI instructions. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-16 21:16:50 +00:00
} else {
brw_BFI1(p, dst, src[0], src[1]);
}
i965/fs: Add support for bit instructions. Don't bother scalarizing ir_binop_bfm, since its results are identical for all channels. v2: Subtract result of FBH from 31 (unless an error) to convert MSB counts to LSB counts. v3: Use op0->clone() in ir_triop_bfi to prevent (var_ref channel_expressions) from appearing multiple times in the IR. Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v2]
2013-04-10 03:22:34 +01:00
break;
case BRW_OPCODE_BFI2:
i965/fs: Add a devinfo field to the generator and use it for gen checks Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 01:45:40 +01:00
assert(devinfo->gen >= 7);
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_access_mode(p, BRW_ALIGN_16);
i965/fs: Don't emit SIMD16 BFI instructions. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-16 21:16:50 +00:00
/* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
* should
*
* "Force BFI instructions to be executed always in SIMD8."
*
* Otherwise we would be able to emit compressed instructions like we
* do for the other three-source instructions.
*/
i965/fs: Drop lowering code for a few three-source instructions from the generator. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-05-18 03:51:50 +01:00
if (dispatch_width == 16 && devinfo->is_haswell) {
i965: Replace guess_execution_size with something simpler. guess_execution_size() does two things: 1. Cope with small destination registers. 2. Cope with SIMD8 vs SIMD16 mode. This patch replaces the first with a simple if block in brw_set_dest: if the destination register width is less than 8, you probably want the execution size to match. (I didn't put this in the 3src block because it doesn't seem to matter.) Since only the FS compiler cares about SIMD16 mode, it's easy to just set the default execution size there. This pattern was already been proven in the Gen8+ generator, but we didn't port it back to the existing generator when we combined the two. This is based on a patch from Ken from about a year ago. I've rebased it and and fixed a few bugs. Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-04-14 20:40:34 +01:00
brw_set_default_exec_size(p, BRW_EXECUTE_8);
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
i965/brw_reg: Add a firsthalf function and use it in the generator Right now, this function is a no-op but it indicates that we intend to only use the first half of the 16-wide register. Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-13 20:23:47 +01:00
brw_BFI2(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
i965/fs: Add support for bit instructions. Don't bother scalarizing ir_binop_bfm, since its results are identical for all channels. v2: Subtract result of FBH from 31 (unless an error) to convert MSB counts to LSB counts. v3: Use op0->clone() in ir_triop_bfi to prevent (var_ref channel_expressions) from appearing multiple times in the IR. Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v2]
2013-04-10 03:22:34 +01:00
brw_BFI2(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
i965/fs: Add support for bit instructions. Don't bother scalarizing ir_binop_bfm, since its results are identical for all channels. v2: Subtract result of FBH from 31 (unless an error) to convert MSB counts to LSB counts. v3: Use op0->clone() in ir_triop_bfi to prevent (var_ref channel_expressions) from appearing multiple times in the IR. Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v2]
2013-04-10 03:22:34 +01:00
} else {
brw_BFI2(p, dst, src[0], src[1], src[2]);
}
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_access_mode(p, BRW_ALIGN_1);
i965/fs: Add support for bit instructions. Don't bother scalarizing ir_binop_bfm, since its results are identical for all channels. v2: Subtract result of FBH from 31 (unless an error) to convert MSB counts to LSB counts. v3: Use op0->clone() in ir_triop_bfi to prevent (var_ref channel_expressions) from appearing multiple times in the IR. Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v2]
2013-04-10 03:22:34 +01:00
break;
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
case BRW_OPCODE_IF:
if (inst->src[0].file != BAD_FILE) {
/* The instruction has an embedded compare (only allowed on gen6) */
i965/fs: Add a devinfo field to the generator and use it for gen checks Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 01:45:40 +01:00
assert(devinfo->gen == 6);
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
gen6_IF(p, inst->conditional_mod, src[0], src[1]);
} else {
i965/fs: Move brw_wm_compile::dispatch_width into fs_visitor. Also, rather than having brw_wm_fs_emit poke at it directly, make it a parameter to the fs_visitor constructor. All other changes generated by search and replace (with occasional whitespace fixup). v2: Make dispatch_width const (as suggested by Paul); fix doxygen mistake (pointed out by Eric); update for rebase. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-11-20 21:50:52 +00:00
brw_IF(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
}
break;
case BRW_OPCODE_ELSE:
brw_ELSE(p);
break;
case BRW_OPCODE_ENDIF:
brw_ENDIF(p);
break;
case BRW_OPCODE_DO:
i965/gen4-5: Program the execution size correctly for DO/WHILE instructions. From the hardware docs for the DO instruction: "Execution size is ignored for this instruction." My observation on ILK hardware contradicts the spec though, channels over the execution size of a DO instruction won't enter the loop, and channels over the execution size of a WHILE instruction will exit the loop after the first iteration -- The latter is consistent with the spec though, there's no claim about the execution size being ignored for the WHILE instruction so it's not completely unexpected that it has an influence on the evaluation of EMask. The execute_size argument of brw_DO() shouldn't have any effect on Gen6 and newer hardware. On Gen4-5 WHILE instructions inherit the execution size from the matching DO, so this patch should fix them too. The execution size of BREAK and CONT instructions was already being set correctly. Fixes some 50 piglit tests on Gen4-5 when forced to run shaders with conditional and loop instructions 16-wide, e.g. shaders/glsl-fs-continue-inside-do-while. Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-07-06 17:11:54 +01:00
brw_DO(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
break;
case BRW_OPCODE_BREAK:
i965: Don't make consumers of brw_CONT/brw_WHILE track if depth in loop. The codegen backends all had this same tracking, so just do it at the EU level. Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
2011-12-06 20:44:41 +00:00
brw_BREAK(p);
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
break;
case BRW_OPCODE_CONTINUE:
i965/eu: Merge brw_CONT and gen6_CONT. The only difference is setting PopCount on Gen4-5. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-04 22:26:26 +01:00
brw_CONT(p);
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
break;
i965: Don't make consumers of brw_WHILE do pre-gen6 BREAK/CONT patching. The EU code itself can just do this work, since all the consumers were duplicating it. Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
2011-12-06 20:30:03 +00:00
case BRW_OPCODE_WHILE:
brw_WHILE(p);
i965/vec4/fs: Count loops in shader debug Reviewed-by: Matt Turner <mattst88@gmail.com> Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
2014-08-06 09:27:58 +01:00
loop_count++;
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
break;
i965: Rename math FS_OPCODE_* to SHADER_OPCODE_*. I want to just use the same enums in the VS.
2011-08-05 20:38:58 +01:00
case SHADER_OPCODE_RCP:
case SHADER_OPCODE_RSQ:
case SHADER_OPCODE_SQRT:
case SHADER_OPCODE_EXP2:
case SHADER_OPCODE_LOG2:
case SHADER_OPCODE_SIN:
case SHADER_OPCODE_COS:
i965: Assert that math instructions don't have conditional mod. The math function field is at the same location as conditional mod. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-11-21 20:34:22 +00:00
assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
i965/fs: Remove handcrafted math SIMD lowering from the generator. Most of this wouldn't have worked for SIMD32 and had various dispatch_width and compression control bugs. It's mostly dead now with SIMD lowering of math instructions turned on in the compiler. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-05-18 03:10:48 +01:00
if (devinfo->gen >= 6) {
assert(inst->mlen == 0);
assert(devinfo->gen >= 7 || inst->exec_size == 8);
gen6_math(p, dst, brw_math_function(inst->opcode),
src[0], brw_null_reg());
i965/fs: Split generate_math into gen4/gen6 and 1/2 operand variants. This mirrors the structure Eric used in the new VS backend, and seems simpler. In particular, the math1/math2 split will avoid having to figure out how many operands there are, as this is already known by the caller. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-08-18 19:55:42 +01:00
} else {
i965/fs: Remove handcrafted math SIMD lowering from the generator. Most of this wouldn't have worked for SIMD32 and had various dispatch_width and compression control bugs. It's mostly dead now with SIMD lowering of math instructions turned on in the compiler. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-05-18 03:10:48 +01:00
assert(inst->mlen >= 1);
assert(devinfo->gen == 5 || devinfo->is_g4x || inst->exec_size == 8);
gen4_math(p, dst,
brw_math_function(inst->opcode),
inst->base_mrf, src[0],
BRW_MATH_PRECISION_FULL);
i965/fs: Split generate_math into gen4/gen6 and 1/2 operand variants. This mirrors the structure Eric used in the new VS backend, and seems simpler. In particular, the math1/math2 split will avoid having to figure out how many operands there are, as this is already known by the caller. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-08-18 19:55:42 +01:00
}
break;
i965/fs: Implement integer quotient and remainder math operations. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Tested-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-09-29 01:37:54 +01:00
case SHADER_OPCODE_INT_QUOTIENT:
case SHADER_OPCODE_INT_REMAINDER:
i965/fs: Split generate_math into gen4/gen6 and 1/2 operand variants. This mirrors the structure Eric used in the new VS backend, and seems simpler. In particular, the math1/math2 split will avoid having to figure out how many operands there are, as this is already known by the caller. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-08-18 19:55:42 +01:00
case SHADER_OPCODE_POW:
i965: Assert that math instructions don't have conditional mod. The math function field is at the same location as conditional mod. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-11-21 20:34:22 +00:00
assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
i965/fs: Remove handcrafted math SIMD lowering from the generator. Most of this wouldn't have worked for SIMD32 and had various dispatch_width and compression control bugs. It's mostly dead now with SIMD lowering of math instructions turned on in the compiler. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-05-18 03:10:48 +01:00
if (devinfo->gen >= 6) {
assert(inst->mlen == 0);
assert((devinfo->gen >= 7 && inst->opcode == SHADER_OPCODE_POW) ||
inst->exec_size == 8);
i965/fs: Drop the generate_math[12]_gen7 methods. These functions are basically identical, so we should combine them. However, they're so trivial, we may as well just fold them into their only call sites. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-06-07 10:27:43 +01:00
gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
i965/fs: Remove handcrafted math SIMD lowering from the generator. Most of this wouldn't have worked for SIMD32 and had various dispatch_width and compression control bugs. It's mostly dead now with SIMD lowering of math instructions turned on in the compiler. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-05-18 03:10:48 +01:00
} else {
assert(inst->mlen >= 1);
assert(inst->exec_size == 8);
gen4_math(p, dst, brw_math_function(inst->opcode),
inst->base_mrf, src[0],
BRW_MATH_PRECISION_FULL);
i965/fs: Split generate_math into gen4/gen6 and 1/2 operand variants. This mirrors the structure Eric used in the new VS backend, and seems simpler. In particular, the math1/math2 split will avoid having to figure out how many operands there are, as this is already known by the caller. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-08-18 19:55:42 +01:00
}
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
break;
case FS_OPCODE_CINTERP:
brw_MOV(p, dst, src[0]);
break;
case FS_OPCODE_LINTERP:
generate_linterp(inst, dst, src);
break;
i965/fs: Combine pixel center calculation into one inst. The X and Y values come interleaved in g1 (.4-.11 inclusive), so we can calculate them together with a single add(32) instruction on some platforms like Broadwell and newer or in SIMD8 elsewhere. Note that I also moved the PIXEL_X/PIXEL_Y virtual opcodes from before LINTERP to after it. That's because the writes_accumulator_implicitly() function in backend_instruction tests for <= LINTERP for determining whether the instruction indeed writes the accumulator implicitly. The old FS_OPCODE_PIXEL_X/Y emitted ADD instructions, which did, but the new opcodes just emit MOVs, which don't. It doesn't matter, since we don't use these opcodes on Gen4/5 anymore, but in the case that we do... On Broadwell: total instructions in shared programs: 7192355 -> 7186224 (-0.09%) instructions in affected programs: 1190700 -> 1184569 (-0.51%) helped: 6131 On Haswell: total instructions in shared programs: 6155979 -> 6152800 (-0.05%) instructions in affected programs: 652362 -> 649183 (-0.49%) helped: 3179 Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-04-14 21:17:38 +01:00
case FS_OPCODE_PIXEL_X:
assert(src[0].type == BRW_REGISTER_TYPE_UW);
src[0].subnr = 0 * type_sz(src[0].type);
brw_MOV(p, dst, stride(src[0], 8, 4, 1));
break;
case FS_OPCODE_PIXEL_Y:
assert(src[0].type == BRW_REGISTER_TYPE_UW);
src[0].subnr = 4 * type_sz(src[0].type);
brw_MOV(p, dst, stride(src[0], 8, 4, 1));
break;
i965/fs: Implement FS_OPCODE_GET_BUFFER_SIZE Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com> Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2015-04-13 15:55:49 +01:00
case FS_OPCODE_GET_BUFFER_SIZE:
generate_get_buffer_size(inst, dst, src[0], src[1]);
break;
i965: Rename texturing ops from FS_OPCODE to SHADER_OPCODE, except TXB. We'll be reusing most of these for the VS shortly. The one exception is TXB (texturing with LOD bias), which is explicitly forbidden in the VS. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-10-26 20:58:37 +01:00
case SHADER_OPCODE_TEX:
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
case FS_OPCODE_TXB:
i965: Rename texturing ops from FS_OPCODE to SHADER_OPCODE, except TXB. We'll be reusing most of these for the VS shortly. The one exception is TXB (texturing with LOD bias), which is explicitly forbidden in the VS. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-10-26 20:58:37 +01:00
case SHADER_OPCODE_TXD:
case SHADER_OPCODE_TXF:
i965: Add infrastucture for sample lod-zero operations. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-05-04 23:46:45 +01:00
case SHADER_OPCODE_TXF_LZ:
i965: rename tex_ms to tex_cms Prepares for the introduction of non-compressed multi-sampled lookup used in the blorp programs. v2: now also taking into account gen8 Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-12-10 14:36:31 +00:00
case SHADER_OPCODE_TXF_CMS:
i965/fs/skl+: Use ld2dms_w instead of ld2dms In order to support 16x MSAA, skl+ has a wider version of ld2dms that takes two parameters for the MCS data. The MCS data retrieved from the ld_mcs instruction already returns 4 or 8 registers and is documented to return zeroes for the mcsh value when the sample count is less than 16. v2: Use get_lowered_simd_width to fall back to SIMD8 instructions when the message length would be too long in SIMD16. Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
2015-09-08 15:52:09 +01:00
case SHADER_OPCODE_TXF_CMS_W:
i965/fs: introduce non-compressed equivalent of tex_cms v2: introduces 'SHADER_OPCODE_TXF_UMS' also for gen8 Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-12-10 14:38:15 +00:00
case SHADER_OPCODE_TXF_UMS:
i965: Add shader opcode for sampling MCS surface Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Paul Berry <stereotype441@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-29 21:32:16 +00:00
case SHADER_OPCODE_TXF_MCS:
i965: Rename texturing ops from FS_OPCODE to SHADER_OPCODE, except TXB. We'll be reusing most of these for the VS shortly. The one exception is TXB (texturing with LOD bias), which is explicitly forbidden in the VS. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-10-26 20:58:37 +01:00
case SHADER_OPCODE_TXL:
i965: Add infrastucture for sample lod-zero operations. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-05-04 23:46:45 +01:00
case SHADER_OPCODE_TXL_LZ:
i965: Rename texturing ops from FS_OPCODE to SHADER_OPCODE, except TXB. We'll be reusing most of these for the VS shortly. The one exception is TXB (texturing with LOD bias), which is explicitly forbidden in the VS. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-10-26 20:58:37 +01:00
case SHADER_OPCODE_TXS:
i965/fs: Generate LOD sampler message from ir_lod. v2: Support Ironlake as well. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-06 22:47:01 +00:00
case SHADER_OPCODE_LOD:
i965: add SHADER_OPCODE_TG4 Adds the Gen7 message IDs, a new SHADER_OPCODE_TG4 pseudo-op, and low-level support for emitting it via generate_tex(). V3: Updated for changes in master. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-31 09:31:12 +01:00
case SHADER_OPCODE_TG4:
i965: Add SHADER_OPCODE_TG4_OFFSET for gather with nonconstant offsets. The generator code ends up clearer this way than if we had to sniff via the message length. Implemented via the gather4_po message in hardware, which is present in Gen7 and later. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-10-08 09:42:10 +01:00
case SHADER_OPCODE_TG4_OFFSET:
i965: add support for textureSamples function Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> [v2: kayden-supplied code in fs_nir replacing need for logical opcode] Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-08-12 01:37:32 +01:00
case SHADER_OPCODE_SAMPLEINFO:
i965/fs: Plumb separate surfaces and samplers through from NIR Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-02-06 02:24:02 +00:00
generate_tex(inst, dst, src[0], src[1], src[2]);
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
break;
i965/fs: Handle derivative quality decisions in the front-end. Kristian noted that there's very little use of brw_wm_prog_key in the generator, and that it basically just generates what it's told, without caring about what stage it's handling. One exception to this is derivative handling. When handling dFdxCoarse and dFdxFine, we packed an enum value in a second source register, explicitly telling the generator what to do. For dFdx, we specified an enum value of "please use the hint", then checked the program key in the generator level code. A natural method is to define separate FS_OPCODE_DD[XY]_{COARSE,FINE} opcodes, and have the front-end (which already decides what IR to generate based on the program key) decide which dPdx/dPdy should correspond to. This consolidates the decision making in one place. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-11-08 09:39:14 +00:00
case FS_OPCODE_DDX_COARSE:
case FS_OPCODE_DDX_FINE:
generate_ddx(inst->opcode, dst, src[0]);
break;
case FS_OPCODE_DDY_COARSE:
case FS_OPCODE_DDY_FINE:
i965, anv: Use NIR FragCoord re-center and y-transform passes. This handles gl_FragCoord transformations and other window system vs. user FBO coordinate system flipping by multiplying/adding uniform values, rather than recompiles. This is much better because we have no decent way to guess whether the application is going to use a shader with the window system FBO or a user FBO, much less the drawable height. This led to a lot of recompiles in many applications. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-05-17 09:52:16 +01:00
generate_ddy(inst->opcode, dst, src[0]);
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
break;
i965: Merge together opcodes for SHADER_OPCODE_GEN4_SCRATCH_READ/WRITE I'm going to be introducing gen7 variants, and the previous naming was going to get confusing. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-10-16 19:45:06 +01:00
case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
generate_scratch_write(inst, src[0]);
i965/fs: Print spills:fills and number of promoted constants. Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2015-03-16 19:18:31 +00:00
spill_count++;
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
break;
i965: Merge together opcodes for SHADER_OPCODE_GEN4_SCRATCH_READ/WRITE I'm going to be introducing gen7 variants, and the previous naming was going to get confusing. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-10-16 19:45:06 +01:00
case SHADER_OPCODE_GEN4_SCRATCH_READ:
generate_scratch_read(inst, dst);
i965/fs: Print spills:fills and number of promoted constants. Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2015-03-16 19:18:31 +00:00
fill_count++;
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
break;
i965/fs: Use the gen7 scratch read opcode when possible. This avoids a lot of message setup we had to do otherwise. Improves GLB2.7 performance with register spilling force enabled by 1.6442% +/- 0.553218% (n=4). v2: Use BRW_PREDICATE_NONE, improve a comment (by Paul). Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-10-16 19:51:22 +01:00
case SHADER_OPCODE_GEN7_SCRATCH_READ:
generate_scratch_read_gen7(inst, dst);
i965/fs: Print spills:fills and number of promoted constants. Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2015-03-16 19:18:31 +00:00
fill_count++;
i965/fs: Use the gen7 scratch read opcode when possible. This avoids a lot of message setup we had to do otherwise. Improves GLB2.7 performance with register spilling force enabled by 1.6442% +/- 0.553218% (n=4). v2: Use BRW_PREDICATE_NONE, improve a comment (by Paul). Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-10-16 19:51:22 +01:00
break;
i965: Introduce a MOV_INDIRECT opcode. The geometry and tessellation control shader stages both read from multiple URB entries (one per vertex). The thread payload contains several URB handles which reference these separate memory segments. In GLSL, these inputs are represented as per-vertex arrays; the outermost array index selects which vertex's inputs to read. This array index does not necessarily need to be constant. To handle that, we need to use indirect addressing on GRFs to select which of the thread payload registers has the appropriate URB handle. (This is before we can even think about applying the pull model!) This patch introduces a new opcode which performs a MOV from a source using VxH indirect addressing (which allows each of the 8 SIMD channels to select distinct data.) Based on a patch by Jason Ekstrand. v2: Rename from INDIRECT_THREAD_PAYLOAD_MOV to MOV_INDIRECT; make it a bit more generic. Use regs_read() instead of hacking up the register allocator. (Suggested by Jason Ekstrand.) v3: Fix regs_read() to be more accurate for small unaligned regions. Also rebase on Matt's work. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com> [v3] Reviewed-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com> [v1]
2015-11-08 02:58:34 +00:00
case SHADER_OPCODE_MOV_INDIRECT:
generate_mov_indirect(inst, dst, src[0], src[1]);
break;
i965: Introduce a new SHADER_OPCODE_URB_READ_SIMD8 opcode. In scalar mode, geometry shader inputs can easily take up hundreds of registers. This makes pushing VUE entries impractical; we'll need to resort to the pull model in some cases. To support this, we introduce a new opcode corresponding to the "URB Read SIMD8" message. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2015-09-29 22:32:02 +01:00
case SHADER_OPCODE_URB_READ_SIMD8:
i965: Add a SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT opcode. We need to use per-slot offsets when there's non-uniform indexing, as each SIMD channel could have a different index. We want to use them for any non-constant index (even if uniform), as it lives in the message header instead of the descriptor, allowing us to set offsets in GRFs rather than immediates. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
2015-11-07 09:37:33 +00:00
case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
i965: Introduce a new SHADER_OPCODE_URB_READ_SIMD8 opcode. In scalar mode, geometry shader inputs can easily take up hundreds of registers. This makes pushing VUE entries impractical; we'll need to resort to the pull model in some cases. To support this, we introduce a new opcode corresponding to the "URB Read SIMD8" message. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2015-09-29 22:32:02 +01:00
generate_urb_read(inst, dst, src[0]);
break;
i965: Add SIMD8 URB write low-level IR instruction This is all we need from the generator for SIMD8 vertex shaders. This opcode is just the send instruction, all the hard work will happen in the visitor using LOAD_PAYLOAD. Signed-off-by: Kristian Høgsberg <krh@bitplanet.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-10-21 07:00:50 +01:00
case SHADER_OPCODE_URB_WRITE_SIMD8:
i965: Introduce new SHADER_OPCODE_URB_WRITE_SIMD8_MASKED/PER_SLOT opcodes. In the vec4 backend, we have a vec4_instruction::urb_write_flags field. There are many kinds of flags for SIMD4x2 messages. However, there are really only two (per-slot offset, use channel masks) for SIMD8 messages. Rather than adding a boolean flag for per-slot offsets (polluting all instructions), I decided to just make three new opcodes. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2015-05-06 08:04:10 +01:00
case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
i965: Add SIMD8 URB write low-level IR instruction This is all we need from the generator for SIMD8 vertex shaders. This opcode is just the send instruction, all the hard work will happen in the visitor using LOAD_PAYLOAD. Signed-off-by: Kristian Høgsberg <krh@bitplanet.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-10-21 07:00:50 +01:00
generate_urb_write(inst, src[0]);
break;
i965/fs: Rename the existing pull constant load opcode. We're going to use another send message for handling loads with a varying per-fragment array index.
2012-11-07 18:42:34 +00:00
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
i965/fs: Mark UBO uniform pull constant loads as force_writemask_all. This lets the rest of the backend know that the uniform pull constant load opcodes don't respect channel enables -- Without this the register allocator has no way to know that the return payload of a pull constant load is not per-channel and spills of the destination will be broken under non-uniform control flow. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-05-23 22:07:23 +01:00
assert(inst->force_writemask_all);
i965/fs: Rename the existing pull constant load opcode. We're going to use another send message for handling loads with a varying per-fragment array index.
2012-11-07 18:42:34 +00:00
generate_uniform_pull_constant_load(inst, dst, src[0], src[1]);
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
break;
i965/fs: Set up gen7 UBO loads as sends from GRFs. This gives the instruction scheduler a chance to schedule between the loads, whereas before it was restricted due to the dependencies between the MRFs for setting them up. For one shader in gles3conform, it goes from getting stuck in register allocation for as long as anybody's bothered to leave it running down to 23 seconds, thanks to the LIFO scheduling. Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-05 08:06:30 +00:00
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
i965/fs: Mark UBO uniform pull constant loads as force_writemask_all. This lets the rest of the backend know that the uniform pull constant load opcodes don't respect channel enables -- Without this the register allocator has no way to know that the return payload of a pull constant load is not per-channel and spills of the destination will be broken under non-uniform control flow. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-05-23 22:07:23 +01:00
assert(inst->force_writemask_all);
i965/fs: Set up gen7 UBO loads as sends from GRFs. This gives the instruction scheduler a chance to schedule between the loads, whereas before it was restricted due to the dependencies between the MRFs for setting them up. For one shader in gles3conform, it goes from getting stuck in register allocation for as long as anybody's bothered to leave it running down to 23 seconds, thanks to the LIFO scheduling. Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-05 08:06:30 +00:00
generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]);
break;
i965/fs: Rename Gen4 physical varying pull constant load opcode. For consistency with the Gen7 variant. I'm not doing the same to the uniform pull constant message at this point because the non-GEN7 one is still overloaded to be either an expression-like logical instruction or a Gen4-specific physical send message. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-05-20 21:03:31 +01:00
case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
generate_varying_pull_constant_load_gen4(inst, dst, src[0]);
i965/fs: Add instruction emit for varying-index reads of uniforms. The gen7 send-from-GRF path is sufficiently different from the perspective of IR generation and optimization that I just made it a separate opcode. v2: fix whitespace, rebase on Ken's recent refactor.
2012-11-07 19:18:34 +00:00
break;
case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
generate_varying_pull_constant_load_gen7(inst, dst, src[0], src[1]);
break;
i965: Add optimization pass to let us use the replicate data message The data port has a SIMD16 'replicate data' message, which lets us write the same color for all 16 pixels by sending the four floats in the lower half of a register instead of sending 4 times 16 identical component values in 8 registers. The message comes with a lot of restrictions and could be made generally useful by recognizing when those restriction are satisfied. For now, this lets us enable the optimization when we know it's safe, but we don't enable it by default. The optimization works for simple color clear shaders only, but does recognized and support multiple render targets. Signed-off-by: Kristian Høgsberg <krh@bitplanet.net> Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2014-07-07 23:27:17 +01:00
case FS_OPCODE_REP_FB_WRITE:
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
case FS_OPCODE_FB_WRITE:
i965/fs: Add a an optional source to the FS_OPCODE_FB_WRITE instruction Previously, we were use the base_mrf parameter of fs_inst to store the MRF location. In preparation for doing FB writes from the GRF, we now also allow you to set inst->base_mrf to -1 and provide a source register. Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-09-16 23:16:20 +01:00
generate_fb_write(inst, src[0]);
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
break;
i965/fs: Add FS_OPCODE_MOV_DISPATCH_TO_FLAGS to fragment shader backend. In order to compute centroid varyings correctly, the fragment shader needs to be able to load the current pixel/sample mask into a flag register. This patch adds an opcode to the fragment shader back-end to do this; the opcode gets translated into the instruction mov(1) f0<1>UW g1.14<0,1,0>UW { align1 WE_all } Since this instruction clobbers f0, instruction scheduling has to treat it the same as instructions that have a conditional modifier. Reviewed-by: Eric Anholt <eric@anholt.net>
2012-06-18 22:50:04 +01:00
case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
i965/fs: Add an instruction flag for choosing the flag subregister. We're going to redo discard handling to track discards in the other flag subregister, saving instructions in the discard and allowing predicated jumps out to the end of the shader. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-06 18:36:11 +00:00
generate_mov_dispatch_to_flags(inst);
i965/fs: Add FS_OPCODE_MOV_DISPATCH_TO_FLAGS to fragment shader backend. In order to compute centroid varyings correctly, the fragment shader needs to be able to load the current pixel/sample mask into a flag register. This patch adds an opcode to the fragment shader back-end to do this; the opcode gets translated into the instruction mov(1) f0<1>UW g1.14<0,1,0>UW { align1 WE_all } Since this instruction clobbers f0, instruction scheduling has to treat it the same as instructions that have a conditional modifier. Reviewed-by: Eric Anholt <eric@anholt.net>
2012-06-18 22:50:04 +01:00
break;
i965/fs: Improve performance of shaders that start out with a discard. I had tried this in the past, but ran into trouble with applications that sample from undiscarded pixels in the same subspan. To fix that issue, only jump to the end for an entire subspan at a time. Improves GLbenchmark 2.7 (1024x768) performance by 7.9 +/- 1.5% (n=8). v2: Drop the br variable in the jump instruction -- if I ever do jumps pre-gen6, it'll be a different code block anyway since we don't have HALT until gen6. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-06 18:15:08 +00:00
case FS_OPCODE_DISCARD_JUMP:
generate_discard_jump(inst);
break;
i965: Add a debug flag for counting cycles spent in each compiled shader. This can be used for two purposes: Using hand-coded shaders to determine per-instruction timings, or figuring out which shader to optimize in a whole application. Note that this doesn't cover the instructions that set up the message to the URB/FB write -- we'd need to convert the MRF usage in these instructions to GRFs so that our offsets/times don't overwrite our shader outputs. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1) v2: Check the timestamp reset flag in the VS, which is apparently getting set fairly regularly in the range we watch, resulting in negative numbers getting added to our 32-bit counter, and thus large values added to our uint64_t. v3: Rebase on reladdr changes, removing a new safety check that proved impossible to satisfy. Add a comment to the AOP defs from Ken's review, and put them in a slightly more sensible spot. v4: Check timestamp reset in the FS as well.
2012-11-27 22:10:52 +00:00
case SHADER_OPCODE_SHADER_TIME_ADD:
i965/fs: Switch shader_time writes to using GRFs. This avoids conflicts between shader_time and FB writes, so we can include more of the program under our profiling. This does mean hiding more of the message setup from the optimizer, which doesn't have a way to handle multi-reg sends from GRFs. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-19 22:28:11 +00:00
generate_shader_time_add(inst, src[0], src[1], src[2]);
i965: Add a debug flag for counting cycles spent in each compiled shader. This can be used for two purposes: Using hand-coded shaders to determine per-instruction timings, or figuring out which shader to optimize in a whole application. Note that this doesn't cover the instructions that set up the message to the URB/FB write -- we'd need to convert the MRF usage in these instructions to GRFs so that our offsets/times don't overwrite our shader outputs. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1) v2: Check the timestamp reset flag in the VS, which is apparently getting set fairly regularly in the range we watch, resulting in negative numbers getting added to our 32-bit counter, and thus large values added to our uint64_t. v3: Rebase on reladdr changes, removing a new safety check that proved impossible to satisfy. Add a comment to the AOP defs from Ken's review, and put them in a slightly more sensible spot. v4: Check timestamp reset in the FS as well.
2012-11-27 22:10:52 +00:00
break;
i965/gen7: Implement code generation for untyped atomic instructions. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-09-11 22:01:50 +01:00
case SHADER_OPCODE_UNTYPED_ATOMIC:
i965: Lift the constness restriction on surface indices passed to untyped ops. v2: Update NIR atomic intrinsic handling too (Ken). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-07-20 15:38:15 +01:00
assert(src[2].file == BRW_IMMEDIATE_VALUE);
i965: Make 'dw1' and 'bits' unnamed structures in brw_reg. Generated by sed -i -e 's/\.bits\././g' *.c *.h *.cpp sed -i -e 's/dw1\.//g' *.c *.h *.cpp and then reverting changes to comments in gen7_blorp.cpp and brw_fs_generator.cpp. There wasn't any utility offered by forcing the programmer to list these to access their fields. Removing them will reduce churn in future commits. This is C11 (and gcc has apparently supported it for sometime "compatibility with other compilers") See https://gcc.gnu.org/onlinedocs/gcc/Unnamed-Fields.html Reviewed-by: Emil Velikov <emil.velikov@collabora.co.uk> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-10-23 03:41:30 +01:00
brw_untyped_atomic(p, dst, src[0], src[1], src[2].ud,
i965: Don't request untyped atomic writeback message if the destination is null. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2015-02-26 15:41:46 +00:00
inst->mlen, !inst->dst.is_null());
i965/gen7: Implement code generation for untyped atomic instructions. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-09-11 22:01:50 +01:00
break;
i965/gen7: Implement code generation for untyped surface read instructions.
2013-09-11 22:03:13 +01:00
case SHADER_OPCODE_UNTYPED_SURFACE_READ:
i965: Lift the constness restriction on surface indices passed to untyped ops. v2: Update NIR atomic intrinsic handling too (Ken). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-07-20 15:38:15 +01:00
assert(src[2].file == BRW_IMMEDIATE_VALUE);
i965: Simplify generator code for untyped surface messages. The generate_untyped_*() methods do nothing useful other than calling the corresponding function from brw_eu_emit.c. The calls to brw_mark_surface_used() will go away too in a future commit. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2015-04-22 19:10:43 +01:00
brw_untyped_surface_read(p, dst, src[0], src[1],
i965: Make 'dw1' and 'bits' unnamed structures in brw_reg. Generated by sed -i -e 's/\.bits\././g' *.c *.h *.cpp sed -i -e 's/dw1\.//g' *.c *.h *.cpp and then reverting changes to comments in gen7_blorp.cpp and brw_fs_generator.cpp. There wasn't any utility offered by forcing the programmer to list these to access their fields. Removing them will reduce churn in future commits. This is C11 (and gcc has apparently supported it for sometime "compatibility with other compilers") See https://gcc.gnu.org/onlinedocs/gcc/Unnamed-Fields.html Reviewed-by: Emil Velikov <emil.velikov@collabora.co.uk> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-10-23 03:41:30 +01:00
inst->mlen, src[2].ud);
i965/gen7: Implement code generation for untyped surface read instructions.
2013-09-11 22:03:13 +01:00
break;
i965: Add untyped surface write opcode. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2015-04-23 12:24:14 +01:00
case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
assert(src[2].file == BRW_IMMEDIATE_VALUE);
brw_untyped_surface_write(p, src[0], src[1],
i965: Make 'dw1' and 'bits' unnamed structures in brw_reg. Generated by sed -i -e 's/\.bits\././g' *.c *.h *.cpp sed -i -e 's/dw1\.//g' *.c *.h *.cpp and then reverting changes to comments in gen7_blorp.cpp and brw_fs_generator.cpp. There wasn't any utility offered by forcing the programmer to list these to access their fields. Removing them will reduce churn in future commits. This is C11 (and gcc has apparently supported it for sometime "compatibility with other compilers") See https://gcc.gnu.org/onlinedocs/gcc/Unnamed-Fields.html Reviewed-by: Emil Velikov <emil.velikov@collabora.co.uk> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-10-23 03:41:30 +01:00
inst->mlen, src[2].ud);
i965: Add untyped surface write opcode. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2015-04-23 12:24:14 +01:00
break;
i965: Add typed surface access opcodes. Acked-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2015-04-23 12:28:25 +01:00
case SHADER_OPCODE_TYPED_ATOMIC:
assert(src[2].file == BRW_IMMEDIATE_VALUE);
brw_typed_atomic(p, dst, src[0], src[1],
i965: Make 'dw1' and 'bits' unnamed structures in brw_reg. Generated by sed -i -e 's/\.bits\././g' *.c *.h *.cpp sed -i -e 's/dw1\.//g' *.c *.h *.cpp and then reverting changes to comments in gen7_blorp.cpp and brw_fs_generator.cpp. There wasn't any utility offered by forcing the programmer to list these to access their fields. Removing them will reduce churn in future commits. This is C11 (and gcc has apparently supported it for sometime "compatibility with other compilers") See https://gcc.gnu.org/onlinedocs/gcc/Unnamed-Fields.html Reviewed-by: Emil Velikov <emil.velikov@collabora.co.uk> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-10-23 03:41:30 +01:00
src[2].ud, inst->mlen, !inst->dst.is_null());
i965: Add typed surface access opcodes. Acked-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2015-04-23 12:28:25 +01:00
break;
case SHADER_OPCODE_TYPED_SURFACE_READ:
assert(src[2].file == BRW_IMMEDIATE_VALUE);
brw_typed_surface_read(p, dst, src[0], src[1],
i965: Make 'dw1' and 'bits' unnamed structures in brw_reg. Generated by sed -i -e 's/\.bits\././g' *.c *.h *.cpp sed -i -e 's/dw1\.//g' *.c *.h *.cpp and then reverting changes to comments in gen7_blorp.cpp and brw_fs_generator.cpp. There wasn't any utility offered by forcing the programmer to list these to access their fields. Removing them will reduce churn in future commits. This is C11 (and gcc has apparently supported it for sometime "compatibility with other compilers") See https://gcc.gnu.org/onlinedocs/gcc/Unnamed-Fields.html Reviewed-by: Emil Velikov <emil.velikov@collabora.co.uk> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-10-23 03:41:30 +01:00
inst->mlen, src[2].ud);
i965: Add typed surface access opcodes. Acked-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2015-04-23 12:28:25 +01:00
break;
case SHADER_OPCODE_TYPED_SURFACE_WRITE:
assert(src[2].file == BRW_IMMEDIATE_VALUE);
i965: Make 'dw1' and 'bits' unnamed structures in brw_reg. Generated by sed -i -e 's/\.bits\././g' *.c *.h *.cpp sed -i -e 's/dw1\.//g' *.c *.h *.cpp and then reverting changes to comments in gen7_blorp.cpp and brw_fs_generator.cpp. There wasn't any utility offered by forcing the programmer to list these to access their fields. Removing them will reduce churn in future commits. This is C11 (and gcc has apparently supported it for sometime "compatibility with other compilers") See https://gcc.gnu.org/onlinedocs/gcc/Unnamed-Fields.html Reviewed-by: Emil Velikov <emil.velikov@collabora.co.uk> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-10-23 03:41:30 +01:00
brw_typed_surface_write(p, src[0], src[1], inst->mlen, src[2].ud);
i965: Add typed surface access opcodes. Acked-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2015-04-23 12:28:25 +01:00
break;
i965: Add memory fence opcode. Acked-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2015-04-23 12:30:28 +01:00
case SHADER_OPCODE_MEMORY_FENCE:
brw_memory_fence(p, dst);
break;
i965/fs: Switch to using sampler LD messages for uniform pull constants. When forcing the compiler to always generate pull constants instead of push constants (in order to have an easy to use testcase), improves performance of my old GLSL demo 23.3553% +/- 1.42968% (n=7). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60866 Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-06 22:47:22 +00:00
case FS_OPCODE_SET_SIMD4X2_OFFSET:
generate_set_simd4x2_offset(inst, dst, src[0]);
i965/fs: Set up gen7 UBO loads as sends from GRFs. This gives the instruction scheduler a chance to schedule between the loads, whereas before it was restricted due to the dependencies between the MRFs for setting them up. For one shader in gles3conform, it goes from getting stuck in register allocation for as long as anybody's bothered to leave it running down to 23 seconds, thanks to the LIFO scheduling. Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-05 08:06:30 +00:00
break;
i965: Introduce the FIND_LIVE_CHANNEL pseudo-opcode. This instruction calculates the index of an arbitrary channel enabled in the current execution mask. It's expected to be used as input for the BROADCAST opcode, but it's implemented as a separate instruction rather than being baked into BROADCAST because FIND_LIVE_CHANNEL has no dependencies so it can always be CSE'ed with other instances of the same instruction within a basic block. v2: Whitespace fixes. Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-23 12:42:53 +01:00
case SHADER_OPCODE_FIND_LIVE_CHANNEL:
brw_find_live_channel(p, dst);
break;
i965: Introduce the BROADCAST pseudo-opcode. The BROADCAST instruction picks the channel from its first source given by an index passed in as second source. This will be used in situations where all channels from the same SIMD thread have to agree on the value of something, e.g. a surface binding table index. This is in particular the case for UBO, sampler and image arrays, which can be indexed dynamically with the restriction that all active SIMD channels access the same index, provided to the shared unit as part of a single scalar field of the message descriptor. Simply taking the index value from the first channel as we were doing until now is incorrect, because it might contain an uninitialized value if the channel had previously been disabled by non-uniform control flow. v2: Minor style fixes. Improve commit message. Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-02-20 18:14:24 +00:00
case SHADER_OPCODE_BROADCAST:
brw_broadcast(p, dst, src[0], src[1]);
break;
i965/fs: Implement support for extract_word. The vec4 backend will lower it. Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-01-21 02:56:37 +00:00
case SHADER_OPCODE_EXTRACT_BYTE: {
assert(src[0].type == BRW_REGISTER_TYPE_D ||
src[0].type == BRW_REGISTER_TYPE_UD);
enum brw_reg_type type =
src[0].type == BRW_REGISTER_TYPE_D ? BRW_REGISTER_TYPE_B
: BRW_REGISTER_TYPE_UB;
brw_MOV(p, dst, spread(suboffset(retype(src[0], type), src[1].ud), 4));
break;
}
case SHADER_OPCODE_EXTRACT_WORD: {
assert(src[0].type == BRW_REGISTER_TYPE_D ||
src[0].type == BRW_REGISTER_TYPE_UD);
enum brw_reg_type type =
src[0].type == BRW_REGISTER_TYPE_D ? BRW_REGISTER_TYPE_W
: BRW_REGISTER_TYPE_UW;
brw_MOV(p, dst, spread(suboffset(retype(src[0], type), src[1].ud), 2));
break;
}
i965: Add FS backend for builtin gl_SampleID V2: - Update comments - Add compute_sample_id variables in brw_wm_prog_key - Add a special backend instruction to compute sample_id. V3: - Make changes to support simd16 mode. Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-10-25 00:17:08 +01:00
case FS_OPCODE_SET_SAMPLE_ID:
generate_set_sample_id(inst, dst, src[0], src[1]);
break;
i965/fs/gen7: Emit code for GLSL 3.00 pack/unpack operations (v4) v2: Remove lewd comment. [for idr] v3: - Optimize away tmp register for packHalf2x16. [for anholt, paul] - Improve comments. [for anholt, paul] - Reduce near-duplicate code by removing vec4_visitor emit_pack/unpack methods. [for chadv] v4: Factor our UD/W register conversion into helper function. [for anholt] Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v2) Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
2013-01-09 19:46:42 +00:00
case FS_OPCODE_PACK_HALF_2x16_SPLIT:
generate_pack_half_2x16_split(inst, dst, src[0], src[1]);
break;
case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
generate_unpack_half_2x16_split(inst, dst, src[0]);
break;
i965: Fix INTEL_DEBUG=shader_time for fragment shaders with discards. "discard" instructions generate HALT instructions which jump to a final HALT near the end of the shader. Previously, fs_generator created this final jump target when it saw the first FS_OPCODE_FB_WRITE, causing it to jump right before the FB write epilogue. This is normally good. However, INTEL_DEBUG=shader_time also has an epilogue section which records the final timestamp. The frontend emits IR for this just before FS_OPCODE_FB_WRITE. Unfortunately, this led to the following ordering: 1. Shader Time Epilogue 2. Final HALT (where discards jump) 3. Framebuffer Write Epilogue This meant that discarded pixels completely skipped the shader time epilogue, causing no ending timestamp to be written. This obviously led to inaccurate results. This patch adds a new FS_OPCODE_PLACEHOLDER_HALT in the IR stream just before any epilogue sections. This is where the final HALT should be generated, and makes it easy to ensure the correct ordering: 1. Final HALT 2. Shader Time Epilogue 3. Framebuffer Write Epilogue For shaders that don't discard, this opcode compiles away to nothing. The scheduler adds barrier dependencies to make sure that it doesn't get moved above any FS_OPCODE_DISCARD_JUMP instructions. One 8-wide shader in GLBenchmark 2.7 dropped from 2291.67 Gcycles to a mere 5.13 Gcycles. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-03-28 06:19:39 +00:00
case FS_OPCODE_PLACEHOLDER_HALT:
/* This is the place where the final HALT needs to be inserted if
* we've emitted any discards. If not, this will emit no code.
*/
i965: Print disassembly after compaction. Reviewed-by: Eric Anholt <eric@anholt.net>
2014-05-19 18:20:37 +01:00
if (!patch_discard_jumps_to_fb_writes()) {
i965/fs: Don't modify ann_count if not debugging. If we make ann_count non-zero, annotation_finalize() won't bail. Not modifying it seems to make the code more clear than would modifying annotation_finalize().
2014-05-25 18:30:13 +01:00
if (unlikely(debug_flag)) {
i965: Move annotation info into generate code. Suggested by Ken as a way to cut down lines of code. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-25 18:42:32 +01:00
annotation.ann_count--;
i965/fs: Don't modify ann_count if not debugging. If we make ann_count non-zero, annotation_finalize() won't bail. Not modifying it seems to make the code more clear than would modifying annotation_finalize().
2014-05-25 18:30:13 +01:00
}
i965: Print disassembly after compaction. Reviewed-by: Eric Anholt <eric@anholt.net>
2014-05-19 18:20:37 +01:00
}
i965: Fix INTEL_DEBUG=shader_time for fragment shaders with discards. "discard" instructions generate HALT instructions which jump to a final HALT near the end of the shader. Previously, fs_generator created this final jump target when it saw the first FS_OPCODE_FB_WRITE, causing it to jump right before the FB write epilogue. This is normally good. However, INTEL_DEBUG=shader_time also has an epilogue section which records the final timestamp. The frontend emits IR for this just before FS_OPCODE_FB_WRITE. Unfortunately, this led to the following ordering: 1. Shader Time Epilogue 2. Final HALT (where discards jump) 3. Framebuffer Write Epilogue This meant that discarded pixels completely skipped the shader time epilogue, causing no ending timestamp to be written. This obviously led to inaccurate results. This patch adds a new FS_OPCODE_PLACEHOLDER_HALT in the IR stream just before any epilogue sections. This is where the final HALT should be generated, and makes it easy to ensure the correct ordering: 1. Final HALT 2. Shader Time Epilogue 3. Framebuffer Write Epilogue For shaders that don't discard, this opcode compiles away to nothing. The scheduler adds barrier dependencies to make sure that it doesn't get moved above any FS_OPCODE_DISCARD_JUMP instructions. One 8-wide shader in GLBenchmark 2.7 dropped from 2291.67 Gcycles to a mere 5.13 Gcycles. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-03-28 06:19:39 +00:00
break;
i965/fs: add generator support for pixel interpolator query V5: - Split into separate opcodes - Pass message data in src1 immediate - Put noperspective bit in fs_inst rather than adding any junk to backend_instruction Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-18 08:13:13 +00:00
case FS_OPCODE_INTERPOLATE_AT_CENTROID:
generate_pixel_interpolator_query(inst, dst, src[0], src[1],
GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID);
break;
case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
generate_pixel_interpolator_query(inst, dst, src[0], src[1],
GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE);
break;
case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
generate_pixel_interpolator_query(inst, dst, src[0], src[1],
GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET);
break;
case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
generate_pixel_interpolator_query(inst, dst, src[0], src[1],
GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET);
break;
i965/cs: Add generator support for CS_OPCODE_CS_TERMINATE v2: * Don't rely on brw_eu* to generate the send instruction. We now generate the send here, and drop the "i965/cs: Add support for the SEND message that terminates a CS thread" brw_eu* patch. Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-27 19:33:25 +01:00
case CS_OPCODE_CS_TERMINATE:
generate_cs_terminate(inst, src[0]);
break;
i965/fs: Implement support for ir_barrier Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-08-27 19:32:08 +01:00
case SHADER_OPCODE_BARRIER:
generate_barrier(inst, src[0]);
break;
i965: Implement ARB_shader_stencil_export (gen9+) v2: remove useless source_stencil_to_render_target (Ken) Squash in the actual packing function, which also got to v2: Move the definition of the OPCODE outside of FB_WRITE opcodes (Matt) Reorder the regioning to be in VWH order (Matt) Don't retype src in the backend, just assert instead (Matt) Rename the debug prints to something better (Matt) Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-10-20 22:29:39 +01:00
case FS_OPCODE_PACK_STENCIL_REF:
generate_stencil_ref_packing(inst, dst, src[0]);
break;
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
default:
i965/fs: Remove the GL context from the generator Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 22:51:18 +01:00
unreachable("Unsupported opcode");
i965/fs: Add SHADER_OPCODE_LOAD_PAYLOAD. Will be used to simplify the handling of large virtual GRFs in SSA form. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-05-28 02:47:40 +01:00
case SHADER_OPCODE_LOAD_PAYLOAD:
i965: Use unreachable() instead of unconditional assert(). Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-06-29 22:54:01 +01:00
unreachable("Should be lowered by lower_load_payload()");
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
}
i965: Don't use brw_set_conditionalmod in the FS and vec4 compilers. brw_set_conditionalmod and brw_next_insn work together to set the conditional modifier for the next instruction, then turn it off. The Gen8+ generators don't implement this: we just set it for all future instructions, and whack it for each fs_inst/vec4_instruction. Both approaches work out because we only set conditional_mod on IR instructions like CMP, AND, and so on, which correspond to exactly one assembly instruction. The Gen8 generators would break if we had an IR instruction that generated multiple instructions, and the Gen4-7 EU emit layer would do...something. To safeguard against this, assert that we only generated one instruction if conditional_mod is set, and just set the flag directly on that instruction rather than altering default state. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-05-31 00:41:32 +01:00
i965/fs: Apply conditional mod specially to split MAD/LRP. Otherwise we'll apply the conditional mod to only one of SIMD8 instructions and trigger an assertion. NoDDClr/NoDDChk have the same problem but we never apply those to these instructions, so I'm leaving them for a later time. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-12-30 20:56:13 +00:00
if (multiple_instructions_emitted)
continue;
i965/fs: Add no_dd_{clear,check} fields to fs_inst. And plumb them through. Also make the assert in the generator look like the vec4 one. Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2014-06-29 07:31:04 +01:00
if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
assert(p->next_insn_offset == last_insn_offset + 16 ||
!"conditional_mod, no_dd_check, or no_dd_clear set for IR "
"emitting more than 1 instruction");
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 22:29:25 +01:00
brw_inst *last = &p->store[last_insn_offset / 16];
i965/fs: Add no_dd_{clear,check} fields to fs_inst. And plumb them through. Also make the assert in the generator look like the vec4 one. Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2014-06-29 07:31:04 +01:00
i965: Don't overwrite the math function with conditional mod. Ben was asking about the undocumented restriction that the math instruction cannot use the dependency control hints. I went to reconfirm and disabled the is_math() check in opt_set_dependency_control() and saw that the disassembled math instructions with dependency hints had a bogus math function. We were mistakenly overwriting it by setting an empty conditional mod. Unfortunately, this wasn't the cause of the aforementioned problem (I reproduced it). This bug is benign, since we don't set dependeny hints on math instructions -- but maybe some day. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-11-21 20:20:53 +00:00
if (inst->conditional_mod)
i965: Make the brw_inst helpers take a device_info instead of a context Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 02:00:06 +01:00
brw_inst_set_cond_modifier(p->devinfo, last, inst->conditional_mod);
brw_inst_set_no_dd_clear(p->devinfo, last, inst->no_dd_clear);
brw_inst_set_no_dd_check(p->devinfo, last, inst->no_dd_check);
i965: Don't use brw_set_conditionalmod in the FS and vec4 compilers. brw_set_conditionalmod and brw_next_insn work together to set the conditional modifier for the next instruction, then turn it off. The Gen8+ generators don't implement this: we just set it for all future instructions, and whack it for each fs_inst/vec4_instruction. Both approaches work out because we only set conditional_mod on IR instructions like CMP, AND, and so on, which correspond to exactly one assembly instruction. The Gen8 generators would break if we had an IR instruction that generated multiple instructions, and the Gen4-7 EU emit layer would do...something. To safeguard against this, assert that we only generated one instruction if conditional_mod is set, and just set the flag directly on that instruction rather than altering default state. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-05-31 00:41:32 +01:00
}
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
}
brw_set_uip_jip(p);
i965: Move annotation info into generate code. Suggested by Ken as a way to cut down lines of code. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-25 18:42:32 +01:00
annotation_finalize(&annotation, p->next_insn_offset);
i965: Add initial assembly validation pass. Initially just checks that sources are non-NULL, which would have alerted us to the problem fixed by commit 6c846dc5. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-06-29 22:08:51 +01:00
#ifndef NDEBUG
bool validated = brw_validate_instructions(p, start_offset, &annotation);
#else
if (unlikely(debug_flag))
brw_validate_instructions(p, start_offset, &annotation);
#endif
i965: Emit compaction stats without walking the assembly. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-25 22:56:41 +01:00
int before_size = p->next_insn_offset - start_offset;
i965: Move annotation info into generate code. Suggested by Ken as a way to cut down lines of code. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-25 18:42:32 +01:00
brw_compact_instructions(p, start_offset, annotation.ann_count,
annotation.ann);
i965: Emit compaction stats without walking the assembly. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-25 22:56:41 +01:00
int after_size = p->next_insn_offset - start_offset;
i965: Move annotation info into generate code. Suggested by Ken as a way to cut down lines of code. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-25 18:42:32 +01:00
if (unlikely(debug_flag)) {
i965: Set shader name for generator from call site fs_generator no longer knows what stage it's generating code for, so we have to set the debug name of the shader from the call site. Signed-off-by: Kristian Høgsberg <krh@bitplanet.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-10-28 02:40:47 +00:00
fprintf(stderr, "Native code for %s\n"
i965: dump scheduling cycle estimates The heuristic we're using is rather lame, since it assumes everything is non-uniform and loops execute 10 times, but it should be enough for measuring improvements in the scheduler that don't result in a change in the number of instructions. v2: - Switch loops and cycle counts to be compatible with older shader-db. - Make loop heuristic 10x to match with spilling code. Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-06-06 15:55:21 +01:00
"SIMD%d shader: %d instructions. %d loops. %u cycles. %d:%d spills:fills. Promoted %u constants. Compacted %d to %d"
i965: Set shader name for generator from call site fs_generator no longer knows what stage it's generating code for, so we have to set the debug name of the shader from the call site. Signed-off-by: Kristian Høgsberg <krh@bitplanet.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-10-28 02:40:47 +00:00
" bytes (%.0f%%)\n",
i965: dump scheduling cycle estimates The heuristic we're using is rather lame, since it assumes everything is non-uniform and loops execute 10 times, but it should be enough for measuring improvements in the scheduler that don't result in a change in the number of instructions. v2: - Switch loops and cycle counts to be compatible with older shader-db. - Make loop heuristic 10x to match with spilling code. Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-06-06 15:55:21 +01:00
shader_name, dispatch_width, before_size / 16, loop_count, cfg->cycle_count,
i965/fs: Print spills:fills and number of promoted constants. Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2015-03-16 19:18:31 +00:00
spill_count, fill_count, promoted_constants, before_size, after_size,
i965: Emit compaction stats without walking the assembly. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-25 22:56:41 +01:00
100.0f * (before_size - after_size) / before_size);
i965: Move program header printing to end of generate_code(). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-25 18:46:55 +01:00
i965: Make the annotation code take a device_info instead of a context Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-04-15 23:01:25 +01:00
dump_assembly(p->store, annotation.ann_count, annotation.ann,
i965/asm: Explicitly use a nir_instr for IR annotations Now that everything goes through NIR, we don't need this to be a void pointer anymore. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2015-10-05 23:49:34 +01:00
p->devinfo);
i965: Set annotation_info's mem_ctx. It was being memset to 0 previously. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2015-06-29 22:05:27 +01:00
ralloc_free(annotation.mem_ctx);
i965: Move annotation info into generate code. Suggested by Ken as a way to cut down lines of code. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-25 18:42:32 +01:00
}
i965: Add initial assembly validation pass. Initially just checks that sources are non-NULL, which would have alerted us to the problem fixed by commit 6c846dc5. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-06-29 22:08:51 +01:00
assert(validated);
i965: Refactor fs_generator API We split out SIMD8 and SIMD16 generation into seperate calls to new method generate_code(), which returns the start offset for the generated code. A new get_assembly() method returns the generated code. This avoids asserting MESA_SHADER_FRAGMENT and accessing wm_prog_data in the generator. Signed-off-by: Kristian Høgsberg <krh@bitplanet.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-11-14 00:28:08 +00:00
i965: Plumb compiler debug logging through a function pointer in brw_compiler v2 (Ken): Make shader_debug_log a printf-like function. v3 (Jason): Add a void * to pass the brw_context through Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-04-16 22:13:52 +01:00
compiler->shader_debug_log(log_data,
i965: dump scheduling cycle estimates The heuristic we're using is rather lame, since it assumes everything is non-uniform and loops execute 10 times, but it should be enough for measuring improvements in the scheduler that don't result in a change in the number of instructions. v2: - Switch loops and cycle counts to be compatible with older shader-db. - Make loop heuristic 10x to match with spilling code. Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-06-06 15:55:21 +01:00
"%s SIMD%d shader: %d inst, %d loops, %u cycles, "
i965: Plumb compiler debug logging through a function pointer in brw_compiler v2 (Ken): Make shader_debug_log a printf-like function. v3 (Jason): Add a void * to pass the brw_context through Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-04-16 22:13:52 +01:00
"%d:%d spills:fills, Promoted %u constants, "
i965: Drop extra newline from shader compile messages. Ilia changed shader-db's run.c to not expect messages to contain a newline in shader-db commit 51bbc8035.
2016-01-14 00:17:26 +00:00
"compacted %d to %d bytes.",
i965/fs/generator: Take an actual shader stage rather than a string Cc: "11.1" <mesa-stable@lists.freedesktop.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-01-15 04:27:51 +00:00
_mesa_shader_stage_to_abbrev(stage),
dispatch_width, before_size / 16,
i965: dump scheduling cycle estimates The heuristic we're using is rather lame, since it assumes everything is non-uniform and loops execute 10 times, but it should be enough for measuring improvements in the scheduler that don't result in a change in the number of instructions. v2: - Switch loops and cycle counts to be compatible with older shader-db. - Make loop heuristic 10x to match with spilling code. Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-06-06 15:55:21 +01:00
loop_count, cfg->cycle_count, spill_count,
fill_count, promoted_constants, before_size,
after_size);
i965: Give compile stats through KHR_debug. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-11-14 20:46:44 +00:00
i965: Refactor fs_generator API We split out SIMD8 and SIMD16 generation into seperate calls to new method generate_code(), which returns the start offset for the generated code. A new get_assembly() method returns the generated code. This avoids asserting MESA_SHADER_FRAGMENT and accessing wm_prog_data in the generator. Signed-off-by: Kristian Høgsberg <krh@bitplanet.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-11-14 00:28:08 +00:00
return start_offset;
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
}
i965/fs: Split final assembly code generation out of fs_visitor. Compiling shaders requires several main steps: 1. Generating FS IR from either GLSL IR or Mesa IR 2. Optimizing the IR 3. Register allocation 4. Generating assembly code This patch splits out step 4 into a separate class named "fs_generator." There are several reasons for doing so: 1. Future hardware has a different instruction encoding. Splitting this out will allow us to replace fs_generator (which relies heavily on the brw_eu_emit.c code and struct brw_instruction) with a new code generator that writes the new format. 2. It reduces the size of the fs_visitor monolith. (Arguably, a lot more should be split out, but that's left for "future work.") 3. Separate namespaces allow us to make helper functions for generating instructions in both classes: ADD() can exist in fs_visitor and create IR, while ADD() in fs_generator() can create brw_instructions. (Patches for this upcoming.) Furthermore, this patch changes the order of operations slightly. Rather than doing steps 1-4 for SIMD8, then 1-4 for SIMD16, we now: - Do steps 1-3 for SIMD8, then repeat 1-3 for SIMD16 - Generate final assembly code for both modes together This is because the frontend work can be done independently, but final assembly generation needs to pack both into a single program store to feed the GPU. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-11-09 09:05:47 +00:00
const unsigned *
i965: Refactor fs_generator API We split out SIMD8 and SIMD16 generation into seperate calls to new method generate_code(), which returns the start offset for the generated code. A new get_assembly() method returns the generated code. This avoids asserting MESA_SHADER_FRAGMENT and accessing wm_prog_data in the generator. Signed-off-by: Kristian Høgsberg <krh@bitplanet.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-11-14 00:28:08 +00:00
fs_generator::get_assembly(unsigned int *assembly_size)
i965/fs: Split final assembly code generation out of fs_visitor. Compiling shaders requires several main steps: 1. Generating FS IR from either GLSL IR or Mesa IR 2. Optimizing the IR 3. Register allocation 4. Generating assembly code This patch splits out step 4 into a separate class named "fs_generator." There are several reasons for doing so: 1. Future hardware has a different instruction encoding. Splitting this out will allow us to replace fs_generator (which relies heavily on the brw_eu_emit.c code and struct brw_instruction) with a new code generator that writes the new format. 2. It reduces the size of the fs_visitor monolith. (Arguably, a lot more should be split out, but that's left for "future work.") 3. Separate namespaces allow us to make helper functions for generating instructions in both classes: ADD() can exist in fs_visitor and create IR, while ADD() in fs_generator() can create brw_instructions. (Patches for this upcoming.) Furthermore, this patch changes the order of operations slightly. Rather than doing steps 1-4 for SIMD8, then 1-4 for SIMD16, we now: - Do steps 1-3 for SIMD8, then repeat 1-3 for SIMD16 - Generate final assembly code for both modes together This is because the frontend work can be done independently, but final assembly generation needs to pack both into a single program store to feed the GPU. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-11-09 09:05:47 +00:00
{
return brw_get_program(p, assembly_size);
}