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i965: Retype pre-Gen6 varying pull load destination to UW. 

This sets up the proper execution mask for sends in SIMD16 mode.

Fixes Piglit's glsl-fs-normalmatrix, glsl-fs-uniform-array-2,
glsl-fs-uniform-array-6, and glsl-fs-uniform-array-7 on Ironlake,
which regressed when I enabled SIMD16 pull parameter support in
commit b207e88b25.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
This commit is contained in:
Kenneth Graunke 2014-04-16 20:15:23 -07:00
parent ee10e893cb
commit 71846a943f
1 changed files with 1 additions and 1 deletions
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2
src/mesa/drivers/dri/i965/brw_fs_generator.cpp
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@ -912,7 +912,7 @@ fs_generator::generate_varying_pull_constant_load(fs_inst *inst,
struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
send->header.compression_control = BRW_COMPRESSION_NONE;
brw_set_dest(p, send, dst);
brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
brw_set_src0(p, send, header);
if (brw->gen < 6)
send->header.destreg__conditionalmod = inst->base_mrf;