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mesa/src/mesa/drivers/dri/i965/brw_fs_generator.cpp

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i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
/*
* Copyright © 2010 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*/
i965: Rename brw_{fs,vec4}_emit.cpp to brw_{fs,vec4}_generator.cpp. The previous names were really confusing to talk about: - brw_fs_visitor() contained methods named emit_whatever(). - brw_fs_generator() contained methods named generate_whatever(), but lived in brw_fs_emit.cpp. So when someone said "the emit layer", or "emit code", we weren't sure whether they meant the visitor's emit() functions or the generator in brw_fs_emit.cpp. By renaming these files, the method names, class names, and file names all match, which is much less confusing. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Eric Anholt <eric@anholt.net>
2013-09-18 07:32:10 +01:00
/** @file brw_fs_generator.cpp
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
*
i965: Rename brw_{fs,vec4}_emit.cpp to brw_{fs,vec4}_generator.cpp. The previous names were really confusing to talk about: - brw_fs_visitor() contained methods named emit_whatever(). - brw_fs_generator() contained methods named generate_whatever(), but lived in brw_fs_emit.cpp. So when someone said "the emit layer", or "emit code", we weren't sure whether they meant the visitor's emit() functions or the generator in brw_fs_emit.cpp. By renaming these files, the method names, class names, and file names all match, which is much less confusing. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Eric Anholt <eric@anholt.net>
2013-09-18 07:32:10 +01:00
* This file supports generating code from the FS LIR to the actual
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
* native instructions.
*/
extern "C" {
#include "main/macros.h"
#include "brw_context.h"
#include "brw_eu.h"
} /* extern "C" */
#include "brw_fs.h"
i965: Move brw_fs_cfg.* to brw_cfg.*. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-10-03 21:03:12 +01:00
#include "brw_cfg.h"
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
i965/fs: Split final assembly code generation out of fs_visitor. Compiling shaders requires several main steps: 1. Generating FS IR from either GLSL IR or Mesa IR 2. Optimizing the IR 3. Register allocation 4. Generating assembly code This patch splits out step 4 into a separate class named "fs_generator." There are several reasons for doing so: 1. Future hardware has a different instruction encoding. Splitting this out will allow us to replace fs_generator (which relies heavily on the brw_eu_emit.c code and struct brw_instruction) with a new code generator that writes the new format. 2. It reduces the size of the fs_visitor monolith. (Arguably, a lot more should be split out, but that's left for "future work.") 3. Separate namespaces allow us to make helper functions for generating instructions in both classes: ADD() can exist in fs_visitor and create IR, while ADD() in fs_generator() can create brw_instructions. (Patches for this upcoming.) Furthermore, this patch changes the order of operations slightly. Rather than doing steps 1-4 for SIMD8, then 1-4 for SIMD16, we now: - Do steps 1-3 for SIMD8, then repeat 1-3 for SIMD16 - Generate final assembly code for both modes together This is because the frontend work can be done independently, but final assembly generation needs to pack both into a single program store to feed the GPU. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-11-09 09:05:47 +00:00
fs_generator::fs_generator(struct brw_context *brw,
i965/fs: Plumb a mem_ctx all the way through the FS compile. 'c' is going away, but we still need a memory context that lives for the duration of the compile. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-05-14 09:21:02 +01:00
void *mem_ctx,
i965/fs: Rip struct brw_wm_compile out of the visitors and generators. Instead, just pass the key and prog_data as separate parameters. This moves it up a level - one step further toward getting rid of it. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-05-14 08:41:41 +01:00
const struct brw_wm_prog_key *key,
struct brw_wm_prog_data *prog_data,
i965/fs: Split final assembly code generation out of fs_visitor. Compiling shaders requires several main steps: 1. Generating FS IR from either GLSL IR or Mesa IR 2. Optimizing the IR 3. Register allocation 4. Generating assembly code This patch splits out step 4 into a separate class named "fs_generator." There are several reasons for doing so: 1. Future hardware has a different instruction encoding. Splitting this out will allow us to replace fs_generator (which relies heavily on the brw_eu_emit.c code and struct brw_instruction) with a new code generator that writes the new format. 2. It reduces the size of the fs_visitor monolith. (Arguably, a lot more should be split out, but that's left for "future work.") 3. Separate namespaces allow us to make helper functions for generating instructions in both classes: ADD() can exist in fs_visitor and create IR, while ADD() in fs_generator() can create brw_instructions. (Patches for this upcoming.) Furthermore, this patch changes the order of operations slightly. Rather than doing steps 1-4 for SIMD8, then 1-4 for SIMD16, we now: - Do steps 1-3 for SIMD8, then repeat 1-3 for SIMD16 - Generate final assembly code for both modes together This is because the frontend work can be done independently, but final assembly generation needs to pack both into a single program store to feed the GPU. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-11-09 09:05:47 +00:00
struct gl_shader_program *prog,
struct gl_fragment_program *fp,
i965/fs: Don't hardcode DEBUG_WM in generic fs code. Similar to Paul's commit e9fa3a944 except brw_fs_generator's debug_flag is for DEBUG_WM and DEBUG_BLORP. Reviewed-by: Eric Anholt <eric@anholt.net>
2014-05-14 23:05:09 +01:00
bool dual_source_output,
i965/fs: Let the gen < 8 generator know about runtime_check_aads_emit In gen < 6 we need to produce conditional code based on this flag when doing framebuffer writes. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-05 14:03:06 +01:00
bool runtime_check_aads_emit,
i965/fs: Don't hardcode DEBUG_WM in generic fs code. Similar to Paul's commit e9fa3a944 except brw_fs_generator's debug_flag is for DEBUG_WM and DEBUG_BLORP. Reviewed-by: Eric Anholt <eric@anholt.net>
2014-05-14 23:05:09 +01:00
bool debug_flag)
i965/fs: Split final assembly code generation out of fs_visitor. Compiling shaders requires several main steps: 1. Generating FS IR from either GLSL IR or Mesa IR 2. Optimizing the IR 3. Register allocation 4. Generating assembly code This patch splits out step 4 into a separate class named "fs_generator." There are several reasons for doing so: 1. Future hardware has a different instruction encoding. Splitting this out will allow us to replace fs_generator (which relies heavily on the brw_eu_emit.c code and struct brw_instruction) with a new code generator that writes the new format. 2. It reduces the size of the fs_visitor monolith. (Arguably, a lot more should be split out, but that's left for "future work.") 3. Separate namespaces allow us to make helper functions for generating instructions in both classes: ADD() can exist in fs_visitor and create IR, while ADD() in fs_generator() can create brw_instructions. (Patches for this upcoming.) Furthermore, this patch changes the order of operations slightly. Rather than doing steps 1-4 for SIMD8, then 1-4 for SIMD16, we now: - Do steps 1-3 for SIMD8, then repeat 1-3 for SIMD16 - Generate final assembly code for both modes together This is because the frontend work can be done independently, but final assembly generation needs to pack both into a single program store to feed the GPU. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-11-09 09:05:47 +00:00
i965/fs: Rip struct brw_wm_compile out of the visitors and generators. Instead, just pass the key and prog_data as separate parameters. This moves it up a level - one step further toward getting rid of it. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-05-14 08:41:41 +01:00
: brw(brw), key(key), prog_data(prog_data), prog(prog), fp(fp),
i965/fs: Let the gen < 8 generator know about runtime_check_aads_emit In gen < 6 we need to produce conditional code based on this flag when doing framebuffer writes. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-05 14:03:06 +01:00
dual_source_output(dual_source_output),
runtime_check_aads_emit(runtime_check_aads_emit), debug_flag(debug_flag),
i965/fs: Don't hardcode DEBUG_WM in generic fs code. Similar to Paul's commit e9fa3a944 except brw_fs_generator's debug_flag is for DEBUG_WM and DEBUG_BLORP. Reviewed-by: Eric Anholt <eric@anholt.net>
2014-05-14 23:05:09 +01:00
mem_ctx(mem_ctx)
i965/fs: Split final assembly code generation out of fs_visitor. Compiling shaders requires several main steps: 1. Generating FS IR from either GLSL IR or Mesa IR 2. Optimizing the IR 3. Register allocation 4. Generating assembly code This patch splits out step 4 into a separate class named "fs_generator." There are several reasons for doing so: 1. Future hardware has a different instruction encoding. Splitting this out will allow us to replace fs_generator (which relies heavily on the brw_eu_emit.c code and struct brw_instruction) with a new code generator that writes the new format. 2. It reduces the size of the fs_visitor monolith. (Arguably, a lot more should be split out, but that's left for "future work.") 3. Separate namespaces allow us to make helper functions for generating instructions in both classes: ADD() can exist in fs_visitor and create IR, while ADD() in fs_generator() can create brw_instructions. (Patches for this upcoming.) Furthermore, this patch changes the order of operations slightly. Rather than doing steps 1-4 for SIMD8, then 1-4 for SIMD16, we now: - Do steps 1-3 for SIMD8, then repeat 1-3 for SIMD16 - Generate final assembly code for both modes together This is because the frontend work can be done independently, but final assembly generation needs to pack both into a single program store to feed the GPU. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-11-09 09:05:47 +00:00
{
i965: Delete intel_context entirely. This makes brw_context inherit directly from gl_context; that was the only thing left in intel_context. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 08:46:38 +01:00
ctx = &brw->ctx;
i965/fs: Split final assembly code generation out of fs_visitor. Compiling shaders requires several main steps: 1. Generating FS IR from either GLSL IR or Mesa IR 2. Optimizing the IR 3. Register allocation 4. Generating assembly code This patch splits out step 4 into a separate class named "fs_generator." There are several reasons for doing so: 1. Future hardware has a different instruction encoding. Splitting this out will allow us to replace fs_generator (which relies heavily on the brw_eu_emit.c code and struct brw_instruction) with a new code generator that writes the new format. 2. It reduces the size of the fs_visitor monolith. (Arguably, a lot more should be split out, but that's left for "future work.") 3. Separate namespaces allow us to make helper functions for generating instructions in both classes: ADD() can exist in fs_visitor and create IR, while ADD() in fs_generator() can create brw_instructions. (Patches for this upcoming.) Furthermore, this patch changes the order of operations slightly. Rather than doing steps 1-4 for SIMD8, then 1-4 for SIMD16, we now: - Do steps 1-3 for SIMD8, then repeat 1-3 for SIMD16 - Generate final assembly code for both modes together This is because the frontend work can be done independently, but final assembly generation needs to pack both into a single program store to feed the GPU. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-11-09 09:05:47 +00:00
i965/fs: Move struct brw_compile (p) entirely inside fs_generator. The brw_compile structure contains the brw_instruction store and the brw_eu_emit.c state tracking fields. These are only useful for the final assembly generation pass; the earlier compilation stages doesn't need them. This also means that the code generator for future hardware won't have access to the brw_compile structure, which is extremely desirable because it prevents accidental generation of Gen4-7 code. v2: rzalloc p, as suggested by Eric. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-11-21 03:26:52 +00:00
p = rzalloc(mem_ctx, struct brw_compile);
brw_init_compile(brw, p, mem_ctx);
i965/fs: Split final assembly code generation out of fs_visitor. Compiling shaders requires several main steps: 1. Generating FS IR from either GLSL IR or Mesa IR 2. Optimizing the IR 3. Register allocation 4. Generating assembly code This patch splits out step 4 into a separate class named "fs_generator." There are several reasons for doing so: 1. Future hardware has a different instruction encoding. Splitting this out will allow us to replace fs_generator (which relies heavily on the brw_eu_emit.c code and struct brw_instruction) with a new code generator that writes the new format. 2. It reduces the size of the fs_visitor monolith. (Arguably, a lot more should be split out, but that's left for "future work.") 3. Separate namespaces allow us to make helper functions for generating instructions in both classes: ADD() can exist in fs_visitor and create IR, while ADD() in fs_generator() can create brw_instructions. (Patches for this upcoming.) Furthermore, this patch changes the order of operations slightly. Rather than doing steps 1-4 for SIMD8, then 1-4 for SIMD16, we now: - Do steps 1-3 for SIMD8, then repeat 1-3 for SIMD16 - Generate final assembly code for both modes together This is because the frontend work can be done independently, but final assembly generation needs to pack both into a single program store to feed the GPU. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-11-09 09:05:47 +00:00
}
fs_generator::~fs_generator()
{
}
i965/fs: Make patch_discard_jumps_to_fb_writes return bool. ... to tell us whether it emitted any code. Will be used to determine whether we need to skip an annotation for it. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
2014-05-16 21:06:45 +01:00
bool
i965/fs: Improve performance of shaders that start out with a discard. I had tried this in the past, but ran into trouble with applications that sample from undiscarded pixels in the same subspan. To fix that issue, only jump to the end for an entire subspan at a time. Improves GLbenchmark 2.7 (1024x768) performance by 7.9 +/- 1.5% (n=8). v2: Drop the br variable in the jump instruction -- if I ever do jumps pre-gen6, it'll be a different code block anyway since we don't have HALT until gen6. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-06 18:15:08 +00:00
fs_generator::patch_discard_jumps_to_fb_writes()
{
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 08:36:46 +01:00
if (brw->gen < 6 || this->discard_halt_patches.is_empty())
i965/fs: Make patch_discard_jumps_to_fb_writes return bool. ... to tell us whether it emitted any code. Will be used to determine whether we need to skip an annotation for it. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
2014-05-16 21:06:45 +01:00
return false;
i965/fs: Improve performance of shaders that start out with a discard. I had tried this in the past, but ran into trouble with applications that sample from undiscarded pixels in the same subspan. To fix that issue, only jump to the end for an entire subspan at a time. Improves GLbenchmark 2.7 (1024x768) performance by 7.9 +/- 1.5% (n=8). v2: Drop the br variable in the jump instruction -- if I ever do jumps pre-gen6, it'll be a different code block anyway since we don't have HALT until gen6. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-06 18:15:08 +00:00
/* There is a somewhat strange undocumented requirement of using
* HALT, according to the simulator. If some channel has HALTed to
* a particular UIP, then by the end of the program, every channel
* must have HALTed to that UIP. Furthermore, the tracking is a
* stack, so you can't do the final halt of a UIP after starting
* halting to a new UIP.
*
* Symptoms of not emitting this instruction on actual hardware
* included GPU hangs and sparkly rendering on the piglit discard
* tests.
*/
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 22:29:25 +01:00
brw_inst *last_halt = gen6_HALT(p);
i965: Convert fs_generator to the new brw_inst API. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-08 06:44:24 +01:00
brw_inst_set_uip(brw, last_halt, 2);
brw_inst_set_jip(brw, last_halt, 2);
i965/fs: Improve performance of shaders that start out with a discard. I had tried this in the past, but ran into trouble with applications that sample from undiscarded pixels in the same subspan. To fix that issue, only jump to the end for an entire subspan at a time. Improves GLbenchmark 2.7 (1024x768) performance by 7.9 +/- 1.5% (n=8). v2: Drop the br variable in the jump instruction -- if I ever do jumps pre-gen6, it'll be a different code block anyway since we don't have HALT until gen6. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-06 18:15:08 +00:00
int ip = p->nr_insn;
foreach_list(node, &this->discard_halt_patches) {
ip_record *patch_ip = (ip_record *)node;
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 22:29:25 +01:00
brw_inst *patch = &p->store[patch_ip->ip];
i965/fs: Improve performance of shaders that start out with a discard. I had tried this in the past, but ran into trouble with applications that sample from undiscarded pixels in the same subspan. To fix that issue, only jump to the end for an entire subspan at a time. Improves GLbenchmark 2.7 (1024x768) performance by 7.9 +/- 1.5% (n=8). v2: Drop the br variable in the jump instruction -- if I ever do jumps pre-gen6, it'll be a different code block anyway since we don't have HALT until gen6. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-06 18:15:08 +00:00
i965: Convert fs_generator to the new brw_inst API. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-08 06:44:24 +01:00
assert(brw_inst_opcode(brw, patch) == BRW_OPCODE_HALT);
i965/fs: Improve performance of shaders that start out with a discard. I had tried this in the past, but ran into trouble with applications that sample from undiscarded pixels in the same subspan. To fix that issue, only jump to the end for an entire subspan at a time. Improves GLbenchmark 2.7 (1024x768) performance by 7.9 +/- 1.5% (n=8). v2: Drop the br variable in the jump instruction -- if I ever do jumps pre-gen6, it'll be a different code block anyway since we don't have HALT until gen6. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-06 18:15:08 +00:00
/* HALT takes a half-instruction distance from the pre-incremented IP. */
i965: Convert fs_generator to the new brw_inst API. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-08 06:44:24 +01:00
brw_inst_set_uip(brw, patch, (ip - patch_ip->ip) * 2);
i965/fs: Improve performance of shaders that start out with a discard. I had tried this in the past, but ran into trouble with applications that sample from undiscarded pixels in the same subspan. To fix that issue, only jump to the end for an entire subspan at a time. Improves GLbenchmark 2.7 (1024x768) performance by 7.9 +/- 1.5% (n=8). v2: Drop the br variable in the jump instruction -- if I ever do jumps pre-gen6, it'll be a different code block anyway since we don't have HALT until gen6. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-06 18:15:08 +00:00
}
this->discard_halt_patches.make_empty();
i965/fs: Make patch_discard_jumps_to_fb_writes return bool. ... to tell us whether it emitted any code. Will be used to determine whether we need to skip an annotation for it. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
2014-05-16 21:06:45 +01:00
return true;
i965/fs: Improve performance of shaders that start out with a discard. I had tried this in the past, but ran into trouble with applications that sample from undiscarded pixels in the same subspan. To fix that issue, only jump to the end for an entire subspan at a time. Improves GLbenchmark 2.7 (1024x768) performance by 7.9 +/- 1.5% (n=8). v2: Drop the br variable in the jump instruction -- if I ever do jumps pre-gen6, it'll be a different code block anyway since we don't have HALT until gen6. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-06 18:15:08 +00:00
}
i965/fs: Add Gen < 6 runtime checks for line antialiasing. In Gen < 6 the hardware generates a runtime bit that indicates whether AA data has to be sent as part of the framebuffer write SEND message. This affects the specific case where we have setup antialiased line rendering and we render polygons which have one face setup in GL_LINE mode (line antialiasing will be used) and the other one in GL_FILL mode (no line antialiasing needed). Currently we are not doing this runtime test and instead we always send AA data, which produces incorrect rendering of the GL_FILL face of the polygon in in the aforementioned scenario (verified in ironlake and gm45). In Gen4 this is, likely, a regression introduced with commit 098acf6c843. In Gen5 this has never worked properly. Gen > 5 are not affected by this. The patch fixes the problem by adding the appropriate runtime check and adjusting the framebuffer write message accordingly in the conflictive scenario. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78679 Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-05 14:03:08 +01:00
void
fs_generator::fire_fb_write(fs_inst *inst,
GLuint base_reg,
struct brw_reg implied_header,
GLuint nr)
{
uint32_t msg_control;
if (brw->gen < 6) {
i965: Fix Haswell discard regressions since Gen4-5 line AA fix. In commit dc2d3a7f5c217a7cee92380fbf503924a9591bea, Iago accidentally moved fire_fb_write() above the brw_pop_insn_state(), which caused the SEND to lose its predication and change from WE_normal to WE_all. Haswell uses predicated SENDs for discards, so this broke Piglit's tests for discards. We want the Gen4-5 MOV to be uncompressed, unpredicated, and unmasked, but the actual FB write itself should respect those. So, pop state first, and force it again around the single MOV. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=79903
2014-06-11 02:50:03 +01:00
brw_push_insn_state(p);
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
i965/fs: Add Gen < 6 runtime checks for line antialiasing. In Gen < 6 the hardware generates a runtime bit that indicates whether AA data has to be sent as part of the framebuffer write SEND message. This affects the specific case where we have setup antialiased line rendering and we render polygons which have one face setup in GL_LINE mode (line antialiasing will be used) and the other one in GL_FILL mode (no line antialiasing needed). Currently we are not doing this runtime test and instead we always send AA data, which produces incorrect rendering of the GL_FILL face of the polygon in in the aforementioned scenario (verified in ironlake and gm45). In Gen4 this is, likely, a regression introduced with commit 098acf6c843. In Gen5 this has never worked properly. Gen > 5 are not affected by this. The patch fixes the problem by adding the appropriate runtime check and adjusting the framebuffer write message accordingly in the conflictive scenario. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78679 Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-05 14:03:08 +01:00
brw_MOV(p,
brw_message_reg(base_reg + 1),
brw_vec8_grf(1, 0));
i965: Fix Haswell discard regressions since Gen4-5 line AA fix. In commit dc2d3a7f5c217a7cee92380fbf503924a9591bea, Iago accidentally moved fire_fb_write() above the brw_pop_insn_state(), which caused the SEND to lose its predication and change from WE_normal to WE_all. Haswell uses predicated SENDs for discards, so this broke Piglit's tests for discards. We want the Gen4-5 MOV to be uncompressed, unpredicated, and unmasked, but the actual FB write itself should respect those. So, pop state first, and force it again around the single MOV. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=79903
2014-06-11 02:50:03 +01:00
brw_pop_insn_state(p);
i965/fs: Add Gen < 6 runtime checks for line antialiasing. In Gen < 6 the hardware generates a runtime bit that indicates whether AA data has to be sent as part of the framebuffer write SEND message. This affects the specific case where we have setup antialiased line rendering and we render polygons which have one face setup in GL_LINE mode (line antialiasing will be used) and the other one in GL_FILL mode (no line antialiasing needed). Currently we are not doing this runtime test and instead we always send AA data, which produces incorrect rendering of the GL_FILL face of the polygon in in the aforementioned scenario (verified in ironlake and gm45). In Gen4 this is, likely, a regression introduced with commit 098acf6c843. In Gen5 this has never worked properly. Gen > 5 are not affected by this. The patch fixes the problem by adding the appropriate runtime check and adjusting the framebuffer write message accordingly in the conflictive scenario. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78679 Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-05 14:03:08 +01:00
}
if (this->dual_source_output)
msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
else if (dispatch_width == 16)
msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
else
msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
uint32_t surf_index =
prog_data->binding_table.render_target_start + inst->target;
brw_fb_WRITE(p,
dispatch_width,
base_reg,
implied_header,
msg_control,
surf_index,
nr,
0,
inst->eot,
inst->header_present);
brw_mark_surface_used(&prog_data->base, surf_index);
}
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
void
i965/fs: Split final assembly code generation out of fs_visitor. Compiling shaders requires several main steps: 1. Generating FS IR from either GLSL IR or Mesa IR 2. Optimizing the IR 3. Register allocation 4. Generating assembly code This patch splits out step 4 into a separate class named "fs_generator." There are several reasons for doing so: 1. Future hardware has a different instruction encoding. Splitting this out will allow us to replace fs_generator (which relies heavily on the brw_eu_emit.c code and struct brw_instruction) with a new code generator that writes the new format. 2. It reduces the size of the fs_visitor monolith. (Arguably, a lot more should be split out, but that's left for "future work.") 3. Separate namespaces allow us to make helper functions for generating instructions in both classes: ADD() can exist in fs_visitor and create IR, while ADD() in fs_generator() can create brw_instructions. (Patches for this upcoming.) Furthermore, this patch changes the order of operations slightly. Rather than doing steps 1-4 for SIMD8, then 1-4 for SIMD16, we now: - Do steps 1-3 for SIMD8, then repeat 1-3 for SIMD16 - Generate final assembly code for both modes together This is because the frontend work can be done independently, but final assembly generation needs to pack both into a single program store to feed the GPU. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-11-09 09:05:47 +00:00
fs_generator::generate_fb_write(fs_inst *inst)
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
{
struct brw_reg implied_header;
/* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
* move, here's g1.
*/
i965/fs: Use conditional sends to do FB writes on HSW+. This drops the MOVs for header setup, which are totally mis-scheduled. total instructions in shared programs: 1590047 -> 1589331 (-0.05%) instructions in affected programs: 43729 -> 43013 (-1.64%) GAINED: 0 LOST: 0 glb27-trex: x before + after +-----------------------------------------------------------------------------+ | + x xx + + + | | ++ + xxx ++x xx + ** *x+ + + + x * | |+x xx x* x+++xx*x*xx+++*+*xx++** *x* x+***x*+xx+* + * + + *| | |__|__________MA___A___________|___| | +-----------------------------------------------------------------------------+ N Min Max Median Avg Stddev x 49 62.33 65.41 63.49 63.53449 0.62757822 + 50 62.28 65.4 63.7 63.6982 0.656564 No difference proven at 95.0% confidence Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-02-14 05:37:50 +00:00
if (inst->header_present) {
i965/fs: Move FB write default state mashing in a level. We only need to alter the default state if we're emitting MOVs for header related fields. So, we can simply move the push/pop of state in to the if (header_present) block, bypassing it in the common case. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=79903
2014-06-11 02:54:09 +01:00
brw_push_insn_state(p);
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
i965/fs: Use conditional sends to do FB writes on HSW+. This drops the MOVs for header setup, which are totally mis-scheduled. total instructions in shared programs: 1590047 -> 1589331 (-0.05%) instructions in affected programs: 43729 -> 43013 (-1.64%) GAINED: 0 LOST: 0 glb27-trex: x before + after +-----------------------------------------------------------------------------+ | + x xx + + + | | ++ + xxx ++x xx + ** *x+ + + + x * | |+x xx x* x+++xx*x*xx+++*+*xx++** *x* x+***x*+xx+* + * + + *| | |__|__________MA___A___________|___| | +-----------------------------------------------------------------------------+ N Min Max Median Avg Stddev x 49 62.33 65.41 63.49 63.53449 0.62757822 + 50 62.28 65.4 63.7 63.6982 0.656564 No difference proven at 95.0% confidence Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-02-14 05:37:50 +00:00
/* On HSW, the GPU will use the predicate on SENDC, unless the header is
* present.
*/
i965/fs: Replace c->key with a direct reference in the generators. 'c' is going away. This is also a bit shorter. Marking the key pointer as const will also deter people from changing it in these classes, as that's absolutely not OK. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-05-14 08:24:50 +01:00
if ((fp && fp->UsesKill) || key->alpha_test_func) {
i965/fs: Use conditional sends to do FB writes on HSW+. This drops the MOVs for header setup, which are totally mis-scheduled. total instructions in shared programs: 1590047 -> 1589331 (-0.05%) instructions in affected programs: 43729 -> 43013 (-1.64%) GAINED: 0 LOST: 0 glb27-trex: x before + after +-----------------------------------------------------------------------------+ | + x xx + + + | | ++ + xxx ++x xx + ** *x+ + + + x * | |+x xx x* x+++xx*x*xx+++*+*xx++** *x* x+***x*+xx+* + * + + *| | |__|__________MA___A___________|___| | +-----------------------------------------------------------------------------+ N Min Max Median Avg Stddev x 49 62.33 65.41 63.49 63.53449 0.62757822 + 50 62.28 65.4 63.7 63.6982 0.656564 No difference proven at 95.0% confidence Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-02-14 05:37:50 +00:00
struct brw_reg pixel_mask;
i965/fs: Rewrite discards to use a flag subreg to track discarded pixels. This makes much more sense on gen6+, and will also prove useful for early exit of shaders on discard. v2: fix up a stale comment from before converting gen4-5. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-06 20:15:13 +00:00
i965/fs: Use conditional sends to do FB writes on HSW+. This drops the MOVs for header setup, which are totally mis-scheduled. total instructions in shared programs: 1590047 -> 1589331 (-0.05%) instructions in affected programs: 43729 -> 43013 (-1.64%) GAINED: 0 LOST: 0 glb27-trex: x before + after +-----------------------------------------------------------------------------+ | + x xx + + + | | ++ + xxx ++x xx + ** *x+ + + + x * | |+x xx x* x+++xx*x*xx+++*+*xx++** *x* x+***x*+xx+* + * + + *| | |__|__________MA___A___________|___| | +-----------------------------------------------------------------------------+ N Min Max Median Avg Stddev x 49 62.33 65.41 63.49 63.53449 0.62757822 + 50 62.28 65.4 63.7 63.6982 0.656564 No difference proven at 95.0% confidence Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-02-14 05:37:50 +00:00
if (brw->gen >= 6)
pixel_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
else
pixel_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
i965/fs: Rewrite discards to use a flag subreg to track discarded pixels. This makes much more sense on gen6+, and will also prove useful for early exit of shaders on discard. v2: fix up a stale comment from before converting gen4-5. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-06 20:15:13 +00:00
i965/fs: Use conditional sends to do FB writes on HSW+. This drops the MOVs for header setup, which are totally mis-scheduled. total instructions in shared programs: 1590047 -> 1589331 (-0.05%) instructions in affected programs: 43729 -> 43013 (-1.64%) GAINED: 0 LOST: 0 glb27-trex: x before + after +-----------------------------------------------------------------------------+ | + x xx + + + | | ++ + xxx ++x xx + ** *x+ + + + x * | |+x xx x* x+++xx*x*xx+++*+*xx++** *x* x+***x*+xx+* + * + + *| | |__|__________MA___A___________|___| | +-----------------------------------------------------------------------------+ N Min Max Median Avg Stddev x 49 62.33 65.41 63.49 63.53449 0.62757822 + 50 62.28 65.4 63.7 63.6982 0.656564 No difference proven at 95.0% confidence Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-02-14 05:37:50 +00:00
brw_MOV(p, pixel_mask, brw_flag_reg(0, 1));
}
i965/fs: Rewrite discards to use a flag subreg to track discarded pixels. This makes much more sense on gen6+, and will also prove useful for early exit of shaders on discard. v2: fix up a stale comment from before converting gen4-5. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-06 20:15:13 +00:00
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 08:36:46 +01:00
if (brw->gen >= 6) {
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
brw_MOV(p,
retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD),
retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
i965/fs: Replace c->key with a direct reference in the generators. 'c' is going away. This is also a bit shorter. Marking the key pointer as const will also deter people from changing it in these classes, as that's absolutely not OK. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-05-14 08:24:50 +01:00
if (inst->target > 0 && key->replicate_alpha) {
i965/msaa: Add sample-alpha-to-coverage support for multiple render targets Render Target Write message should include source zero alpha value when sample-alpha-to-coverage is enabled for an FBO with multiple render targets. Source zero alpha value is used as fragment coverage for all the render targets. This patch makes piglit tests draw-buffers-alpha-to-coverage and alpha-to-coverage-no-draw-buffer-zero to pass on Sandybridge. No regressions are observed with piglit all.tests. V2: Revert all the changes made in emit_color_write() function to include src0 alpha for targets > 0. Now handling this case in a if block. V3: Correctly calculate the instruction length for buffer zero. Properly handle the case of dual_src_blend when alpha-to-coverage is enabled. Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-08-02 00:32:06 +01:00
/* Set "Source0 Alpha Present to RenderTarget" bit in message
* header.
*/
brw_OR(p,
vec1(retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD)),
vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
brw_imm_ud(0x1 << 11));
}
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
if (inst->target > 0) {
/* Set the render target index for choosing BLEND_STATE. */
i965/fs: Fix MRT drawing since the m0->m2 move for shader debug. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2011-07-25 23:39:03 +01:00
brw_MOV(p, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE,
inst->base_mrf, 2),
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
BRW_REGISTER_TYPE_UD),
brw_imm_ud(inst->target));
}
implied_header = brw_null_reg();
} else {
implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
}
i965/fs: Move FB write default state mashing in a level. We only need to alter the default state if we're emitting MOVs for header related fields. So, we can simply move the push/pop of state in to the if (header_present) block, bypassing it in the common case. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=79903
2014-06-11 02:54:09 +01:00
brw_pop_insn_state(p);
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
} else {
implied_header = brw_null_reg();
}
i965/fs: Add Gen < 6 runtime checks for line antialiasing. In Gen < 6 the hardware generates a runtime bit that indicates whether AA data has to be sent as part of the framebuffer write SEND message. This affects the specific case where we have setup antialiased line rendering and we render polygons which have one face setup in GL_LINE mode (line antialiasing will be used) and the other one in GL_FILL mode (no line antialiasing needed). Currently we are not doing this runtime test and instead we always send AA data, which produces incorrect rendering of the GL_FILL face of the polygon in in the aforementioned scenario (verified in ironlake and gm45). In Gen4 this is, likely, a regression introduced with commit 098acf6c843. In Gen5 this has never worked properly. Gen > 5 are not affected by this. The patch fixes the problem by adding the appropriate runtime check and adjusting the framebuffer write message accordingly in the conflictive scenario. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78679 Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-05 14:03:08 +01:00
if (!runtime_check_aads_emit) {
fire_fb_write(inst, inst->base_mrf, implied_header, inst->mlen);
} else {
/* This can only happen in gen < 6 */
assert(brw->gen < 6);
struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
/* Check runtime bit to detect if we have to send AA data or not */
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
brw_AND(p,
v1_null_ud,
retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD),
brw_imm_ud(1<<26));
i965: Convert fs_generator to the new brw_inst API. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-08 06:44:24 +01:00
brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_NZ);
i965/fs: Add Gen < 6 runtime checks for line antialiasing. In Gen < 6 the hardware generates a runtime bit that indicates whether AA data has to be sent as part of the framebuffer write SEND message. This affects the specific case where we have setup antialiased line rendering and we render polygons which have one face setup in GL_LINE mode (line antialiasing will be used) and the other one in GL_FILL mode (no line antialiasing needed). Currently we are not doing this runtime test and instead we always send AA data, which produces incorrect rendering of the GL_FILL face of the polygon in in the aforementioned scenario (verified in ironlake and gm45). In Gen4 this is, likely, a regression introduced with commit 098acf6c843. In Gen5 this has never worked properly. Gen > 5 are not affected by this. The patch fixes the problem by adding the appropriate runtime check and adjusting the framebuffer write message accordingly in the conflictive scenario. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78679 Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-05 14:03:08 +01:00
int jmp = brw_JMPI(p, brw_imm_ud(0), BRW_PREDICATE_NORMAL) - p->store;
i965: Convert fs_generator to the new brw_inst API. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-08 06:44:24 +01:00
brw_inst_set_exec_size(brw, brw_last_inst, BRW_EXECUTE_1);
i965/fs: Add Gen < 6 runtime checks for line antialiasing. In Gen < 6 the hardware generates a runtime bit that indicates whether AA data has to be sent as part of the framebuffer write SEND message. This affects the specific case where we have setup antialiased line rendering and we render polygons which have one face setup in GL_LINE mode (line antialiasing will be used) and the other one in GL_FILL mode (no line antialiasing needed). Currently we are not doing this runtime test and instead we always send AA data, which produces incorrect rendering of the GL_FILL face of the polygon in in the aforementioned scenario (verified in ironlake and gm45). In Gen4 this is, likely, a regression introduced with commit 098acf6c843. In Gen5 this has never worked properly. Gen > 5 are not affected by this. The patch fixes the problem by adding the appropriate runtime check and adjusting the framebuffer write message accordingly in the conflictive scenario. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78679 Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-05 14:03:08 +01:00
{
/* Don't send AA data */
fire_fb_write(inst, inst->base_mrf+1, implied_header, inst->mlen-1);
}
brw_land_fwd_jump(p, jmp);
fire_fb_write(inst, inst->base_mrf, implied_header, inst->mlen);
}
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
}
i965/fs: introduce blorp specific rt-write for fs_generator The compiler for blorp programs likes to emit instructions for the message construction itself meaning that the generator needs to skip any such when blorp programs are translated for the hw. In addition, the binding table control is special for blorp programs and the generator does not need to update the binding tables associated with the compiler bookkeeping (this in fact gets thrown away as the blorp compiler sets the program data in its own way). v2 (Paul): do not hardcode the binding table index but use fs_inst::target instead. Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-12-17 12:00:50 +00:00
void
fs_generator::generate_blorp_fb_write(fs_inst *inst)
{
brw_fb_WRITE(p,
16 /* dispatch_width */,
inst->base_mrf,
brw_reg_from_fs_reg(&inst->src[0]),
BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE,
inst->target,
inst->mlen,
0,
true,
inst->header_present);
}
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
/* Computes the integer pixel x,y values from the origin.
*
* This is the basis of gl_FragCoord computation, but is also used
* pre-gen6 for computing the deltas from v0 for computing
* interpolation.
*/
void
i965/fs: Split final assembly code generation out of fs_visitor. Compiling shaders requires several main steps: 1. Generating FS IR from either GLSL IR or Mesa IR 2. Optimizing the IR 3. Register allocation 4. Generating assembly code This patch splits out step 4 into a separate class named "fs_generator." There are several reasons for doing so: 1. Future hardware has a different instruction encoding. Splitting this out will allow us to replace fs_generator (which relies heavily on the brw_eu_emit.c code and struct brw_instruction) with a new code generator that writes the new format. 2. It reduces the size of the fs_visitor monolith. (Arguably, a lot more should be split out, but that's left for "future work.") 3. Separate namespaces allow us to make helper functions for generating instructions in both classes: ADD() can exist in fs_visitor and create IR, while ADD() in fs_generator() can create brw_instructions. (Patches for this upcoming.) Furthermore, this patch changes the order of operations slightly. Rather than doing steps 1-4 for SIMD8, then 1-4 for SIMD16, we now: - Do steps 1-3 for SIMD8, then repeat 1-3 for SIMD16 - Generate final assembly code for both modes together This is because the frontend work can be done independently, but final assembly generation needs to pack both into a single program store to feed the GPU. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-11-09 09:05:47 +00:00
fs_generator::generate_pixel_xy(struct brw_reg dst, bool is_x)
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
{
struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
struct brw_reg src;
struct brw_reg deltas;
if (is_x) {
src = stride(suboffset(g1_uw, 4), 2, 4, 0);
deltas = brw_imm_v(0x10101010);
} else {
src = stride(suboffset(g1_uw, 5), 2, 4, 0);
deltas = brw_imm_v(0x11001100);
}
i965/fs: Move brw_wm_compile::dispatch_width into fs_visitor. Also, rather than having brw_wm_fs_emit poke at it directly, make it a parameter to the fs_visitor constructor. All other changes generated by search and replace (with occasional whitespace fixup). v2: Make dispatch_width const (as suggested by Paul); fix doxygen mistake (pointed out by Eric); update for rebase. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-11-20 21:50:52 +00:00
if (dispatch_width == 16) {
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
dst = vec16(dst);
}
i965: Replace 8-wide and 16-wide with SIMD8 and SIMD16. Those are the terms used in the docs, and think "n-wide" was something I just happened to say. Note that shader-db needs updating for the INTEL_DEBUG=fs parsing. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-11-12 23:33:27 +00:00
/* We do this SIMD8 or SIMD16, but since the destination is UW we
* don't do compression in the SIMD16 case.
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
*/
brw_push_insn_state(p);
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
brw_ADD(p, dst, src, deltas);
brw_pop_insn_state(p);
}
void
i965/fs: Split final assembly code generation out of fs_visitor. Compiling shaders requires several main steps: 1. Generating FS IR from either GLSL IR or Mesa IR 2. Optimizing the IR 3. Register allocation 4. Generating assembly code This patch splits out step 4 into a separate class named "fs_generator." There are several reasons for doing so: 1. Future hardware has a different instruction encoding. Splitting this out will allow us to replace fs_generator (which relies heavily on the brw_eu_emit.c code and struct brw_instruction) with a new code generator that writes the new format. 2. It reduces the size of the fs_visitor monolith. (Arguably, a lot more should be split out, but that's left for "future work.") 3. Separate namespaces allow us to make helper functions for generating instructions in both classes: ADD() can exist in fs_visitor and create IR, while ADD() in fs_generator() can create brw_instructions. (Patches for this upcoming.) Furthermore, this patch changes the order of operations slightly. Rather than doing steps 1-4 for SIMD8, then 1-4 for SIMD16, we now: - Do steps 1-3 for SIMD8, then repeat 1-3 for SIMD16 - Generate final assembly code for both modes together This is because the frontend work can be done independently, but final assembly generation needs to pack both into a single program store to feed the GPU. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-11-09 09:05:47 +00:00
fs_generator::generate_linterp(fs_inst *inst,
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
struct brw_reg dst, struct brw_reg *src)
{
struct brw_reg delta_x = src[0];
struct brw_reg delta_y = src[1];
struct brw_reg interp = src[2];
if (brw->has_pln &&
delta_y.nr == delta_x.nr + 1 &&
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 08:36:46 +01:00
(brw->gen >= 6 || (delta_x.nr & 1) == 0)) {
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
brw_PLN(p, dst, interp, delta_x);
} else {
brw_LINE(p, brw_null_reg(), interp, delta_x);
brw_MAC(p, dst, suboffset(interp, 1), delta_y);
}
}
void
i965/fs: Combine generate_math[12]_gen6 methods. These used to call different math emitters (brw_math vs. brw_math2). Now that they both call gen6_math, they're virtually identical. When unrolling SIMD16 to multiple SIMD8 operations, we should take care not to apply sechalf to brw_null_reg for src1. Otherwise, we'd end up with BRW_ARF_NULL + 1 as the register number, and I'm not sure if that's valid. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-06-07 10:21:47 +01:00
fs_generator::generate_math_gen6(fs_inst *inst,
struct brw_reg dst,
struct brw_reg src0,
struct brw_reg src1)
i965/fs: Split generate_math into gen4/gen6 and 1/2 operand variants. This mirrors the structure Eric used in the new VS backend, and seems simpler. In particular, the math1/math2 split will avoid having to figure out how many operands there are, as this is already known by the caller. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-08-18 19:55:42 +01:00
{
int op = brw_math_function(inst->opcode);
i965/fs: Combine generate_math[12]_gen6 methods. These used to call different math emitters (brw_math vs. brw_math2). Now that they both call gen6_math, they're virtually identical. When unrolling SIMD16 to multiple SIMD8 operations, we should take care not to apply sechalf to brw_null_reg for src1. Otherwise, we'd end up with BRW_ARF_NULL + 1 as the register number, and I'm not sure if that's valid. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-06-07 10:21:47 +01:00
bool binop = src1.file == BRW_GENERAL_REGISTER_FILE;
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
i965: Split Gen4-5 and Gen6+ MATH instruction emitters. Our existing functions, brw_math and brw_math2, had unclear roles: Gen4-5 used brw_math for both unary and binary math functions; it never used brw_math2. Since operands are already in message registers, this is reasonable. Gen6+ used brw_math for unary math functions, and brw_math2 for binary math functions, duplicating a lot of code. The only real difference was that brw_math used brw_null_reg() for src1. This patch improves brw_math2's assertions to allow both unary and binary operations, renames it to gen6_math(), and drops the Gen6+ code out of brw_math(). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-06-07 09:56:12 +01:00
gen6_math(p, dst, op, src0, src1);
i965/fs: Split generate_math into gen4/gen6 and 1/2 operand variants. This mirrors the structure Eric used in the new VS backend, and seems simpler. In particular, the math1/math2 split will avoid having to figure out how many operands there are, as this is already known by the caller. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-08-18 19:55:42 +01:00
i965/fs: Move brw_wm_compile::dispatch_width into fs_visitor. Also, rather than having brw_wm_fs_emit poke at it directly, make it a parameter to the fs_visitor constructor. All other changes generated by search and replace (with occasional whitespace fixup). v2: Make dispatch_width const (as suggested by Paul); fix doxygen mistake (pointed out by Eric); update for rebase. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-11-20 21:50:52 +00:00
if (dispatch_width == 16) {
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
i965/fs: Combine generate_math[12]_gen6 methods. These used to call different math emitters (brw_math vs. brw_math2). Now that they both call gen6_math, they're virtually identical. When unrolling SIMD16 to multiple SIMD8 operations, we should take care not to apply sechalf to brw_null_reg for src1. Otherwise, we'd end up with BRW_ARF_NULL + 1 as the register number, and I'm not sure if that's valid. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-06-07 10:21:47 +01:00
gen6_math(p, sechalf(dst), op, sechalf(src0),
binop ? sechalf(src1) : brw_null_reg());
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
i965/fs: Split generate_math into gen4/gen6 and 1/2 operand variants. This mirrors the structure Eric used in the new VS backend, and seems simpler. In particular, the math1/math2 split will avoid having to figure out how many operands there are, as this is already known by the caller. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-08-18 19:55:42 +01:00
}
}
void
i965/fs: Split final assembly code generation out of fs_visitor. Compiling shaders requires several main steps: 1. Generating FS IR from either GLSL IR or Mesa IR 2. Optimizing the IR 3. Register allocation 4. Generating assembly code This patch splits out step 4 into a separate class named "fs_generator." There are several reasons for doing so: 1. Future hardware has a different instruction encoding. Splitting this out will allow us to replace fs_generator (which relies heavily on the brw_eu_emit.c code and struct brw_instruction) with a new code generator that writes the new format. 2. It reduces the size of the fs_visitor monolith. (Arguably, a lot more should be split out, but that's left for "future work.") 3. Separate namespaces allow us to make helper functions for generating instructions in both classes: ADD() can exist in fs_visitor and create IR, while ADD() in fs_generator() can create brw_instructions. (Patches for this upcoming.) Furthermore, this patch changes the order of operations slightly. Rather than doing steps 1-4 for SIMD8, then 1-4 for SIMD16, we now: - Do steps 1-3 for SIMD8, then repeat 1-3 for SIMD16 - Generate final assembly code for both modes together This is because the frontend work can be done independently, but final assembly generation needs to pack both into a single program store to feed the GPU. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-11-09 09:05:47 +00:00
fs_generator::generate_math_gen4(fs_inst *inst,
i965/fs: Split generate_math into gen4/gen6 and 1/2 operand variants. This mirrors the structure Eric used in the new VS backend, and seems simpler. In particular, the math1/math2 split will avoid having to figure out how many operands there are, as this is already known by the caller. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-08-18 19:55:42 +01:00
struct brw_reg dst,
struct brw_reg src)
{
int op = brw_math_function(inst->opcode);
assert(inst->mlen >= 1);
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
i965: Rename brw_math to gen4_math. Usually, I try to use "brw" for functions that apply to all generations, and "gen4" for dead end/legacy code that is only used on Gen4-5. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-06-07 10:12:46 +01:00
gen4_math(p, dst,
op,
inst->base_mrf, src,
BRW_MATH_DATA_VECTOR,
BRW_MATH_PRECISION_FULL);
i965/fs: Split generate_math into gen4/gen6 and 1/2 operand variants. This mirrors the structure Eric used in the new VS backend, and seems simpler. In particular, the math1/math2 split will avoid having to figure out how many operands there are, as this is already known by the caller. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-08-18 19:55:42 +01:00
i965/fs: Move brw_wm_compile::dispatch_width into fs_visitor. Also, rather than having brw_wm_fs_emit poke at it directly, make it a parameter to the fs_visitor constructor. All other changes generated by search and replace (with occasional whitespace fixup). v2: Make dispatch_width const (as suggested by Paul); fix doxygen mistake (pointed out by Eric); update for rebase. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-11-20 21:50:52 +00:00
if (dispatch_width == 16) {
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
i965: Rename brw_math to gen4_math. Usually, I try to use "brw" for functions that apply to all generations, and "gen4" for dead end/legacy code that is only used on Gen4-5. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-06-07 10:12:46 +01:00
gen4_math(p, sechalf(dst),
op,
inst->base_mrf + 1, sechalf(src),
BRW_MATH_DATA_VECTOR,
BRW_MATH_PRECISION_FULL);
i965/fs: Split generate_math into gen4/gen6 and 1/2 operand variants. This mirrors the structure Eric used in the new VS backend, and seems simpler. In particular, the math1/math2 split will avoid having to figure out how many operands there are, as this is already known by the caller. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-08-18 19:55:42 +01:00
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
}
}
i965: Implement 16-wide math on G45 and Ironlake. [chrisf:] Improves performance in CS:S video stress test by about 2%. No piglit regressions on Ironlake. Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2013-03-30 07:15:54 +00:00
void
fs_generator::generate_math_g45(fs_inst *inst,
struct brw_reg dst,
struct brw_reg src)
{
if (inst->opcode == SHADER_OPCODE_POW ||
inst->opcode == SHADER_OPCODE_INT_QUOTIENT ||
inst->opcode == SHADER_OPCODE_INT_REMAINDER) {
generate_math_gen4(inst, dst, src);
return;
}
int op = brw_math_function(inst->opcode);
assert(inst->mlen >= 1);
i965: Rename brw_math to gen4_math. Usually, I try to use "brw" for functions that apply to all generations, and "gen4" for dead end/legacy code that is only used on Gen4-5. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-06-07 10:12:46 +01:00
gen4_math(p, dst,
op,
inst->base_mrf, src,
BRW_MATH_DATA_VECTOR,
BRW_MATH_PRECISION_FULL);
i965: Implement 16-wide math on G45 and Ironlake. [chrisf:] Improves performance in CS:S video stress test by about 2%. No piglit regressions on Ironlake. Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2013-03-30 07:15:54 +00:00
}
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
void
i965/fs: Split final assembly code generation out of fs_visitor. Compiling shaders requires several main steps: 1. Generating FS IR from either GLSL IR or Mesa IR 2. Optimizing the IR 3. Register allocation 4. Generating assembly code This patch splits out step 4 into a separate class named "fs_generator." There are several reasons for doing so: 1. Future hardware has a different instruction encoding. Splitting this out will allow us to replace fs_generator (which relies heavily on the brw_eu_emit.c code and struct brw_instruction) with a new code generator that writes the new format. 2. It reduces the size of the fs_visitor monolith. (Arguably, a lot more should be split out, but that's left for "future work.") 3. Separate namespaces allow us to make helper functions for generating instructions in both classes: ADD() can exist in fs_visitor and create IR, while ADD() in fs_generator() can create brw_instructions. (Patches for this upcoming.) Furthermore, this patch changes the order of operations slightly. Rather than doing steps 1-4 for SIMD8, then 1-4 for SIMD16, we now: - Do steps 1-3 for SIMD8, then repeat 1-3 for SIMD16 - Generate final assembly code for both modes together This is because the frontend work can be done independently, but final assembly generation needs to pack both into a single program store to feed the GPU. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-11-09 09:05:47 +00:00
fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
{
int msg_type = -1;
int rlen = 4;
uint32_t simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
i965/gen4: Fix sampling from integer textures. On original gen4, the surface format didn't determine the return data type from sampling like it does on g45 and later. Fixes GL_EXT_texture_integer/texture_integer_glsl130 Reviewed-by: Paul Berry <stereotype441@gmail.com>
2011-11-10 00:07:57 +00:00
uint32_t return_format;
switch (dst.type) {
case BRW_REGISTER_TYPE_D:
return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
break;
case BRW_REGISTER_TYPE_UD:
return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
break;
default:
return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
break;
}
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
i965: allow SIMD8 sampler messages in SIMD16 mode When the instruction to send the sampler message is forced uncompressed or sechalf, send SIMD8 one even in SIMD16 mode. Signed-off-by: Chia-I Wu <olv@lunarg.com> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-09-30 07:12:19 +01:00
if (dispatch_width == 16 &&
!inst->force_uncompressed && !inst->force_sechalf)
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 08:36:46 +01:00
if (brw->gen >= 5) {
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
switch (inst->opcode) {
i965: Rename texturing ops from FS_OPCODE to SHADER_OPCODE, except TXB. We'll be reusing most of these for the VS shortly. The one exception is TXB (texturing with LOD bias), which is explicitly forbidden in the VS. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-10-26 20:58:37 +01:00
case SHADER_OPCODE_TEX:
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
if (inst->shadow_compare) {
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
} else {
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
}
break;
case FS_OPCODE_TXB:
if (inst->shadow_compare) {
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
} else {
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
}
break;
i965: Rename texturing ops from FS_OPCODE to SHADER_OPCODE, except TXB. We'll be reusing most of these for the VS shortly. The one exception is TXB (texturing with LOD bias), which is explicitly forbidden in the VS. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-10-26 20:58:37 +01:00
case SHADER_OPCODE_TXL:
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
if (inst->shadow_compare) {
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
} else {
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
}
break;
i965: Rename texturing ops from FS_OPCODE to SHADER_OPCODE, except TXB. We'll be reusing most of these for the VS shortly. The one exception is TXB (texturing with LOD bias), which is explicitly forbidden in the VS. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-10-26 20:58:37 +01:00
case SHADER_OPCODE_TXS:
i965/fs: Implement textureSize (TXS) on Gen5+. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2011-06-19 09:47:50 +01:00
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
break;
i965: Rename texturing ops from FS_OPCODE to SHADER_OPCODE, except TXB. We'll be reusing most of these for the VS shortly. The one exception is TXB (texturing with LOD bias), which is explicitly forbidden in the VS. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-10-26 20:58:37 +01:00
case SHADER_OPCODE_TXD:
i965: Use Haswell's sample_d_c for textureGrad with shadow samplers. The new hardware actually just supports this now. Reviewed-by: Eric Anholt <eric@anholt.net>
2013-01-04 15:53:09 +00:00
if (inst->shadow_compare) {
/* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
i965: Extend is_haswell checks to gen >= 8 in Gen4-7 generators. We're going to use fs_generator/vec4_generator for Gen8+ code soon, thanks to the new brw_instruction API. When we do, we'll generally want to take the Haswell paths on Gen8+ as well. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-08 07:52:37 +01:00
assert(brw->gen >= 8 || brw->is_haswell);
i965: Use Haswell's sample_d_c for textureGrad with shadow samplers. The new hardware actually just supports this now. Reviewed-by: Eric Anholt <eric@anholt.net>
2013-01-04 15:53:09 +00:00
msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
} else {
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
}
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
break;
i965: Rename texturing ops from FS_OPCODE to SHADER_OPCODE, except TXB. We'll be reusing most of these for the VS shortly. The one exception is TXB (texturing with LOD bias), which is explicitly forbidden in the VS. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-10-26 20:58:37 +01:00
case SHADER_OPCODE_TXF:
i965/fs: Implement texelFetch() on Ironlake and Sandybridge. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-08-26 01:13:37 +01:00
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
break;
i965: rename tex_ms to tex_cms Prepares for the introduction of non-compressed multi-sampled lookup used in the blorp programs. v2: now also taking into account gen8 Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-12-10 14:36:31 +00:00
case SHADER_OPCODE_TXF_CMS:
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 08:36:46 +01:00
if (brw->gen >= 7)
i965: add a new virtual opcode: SHADER_OPCODE_TXF_MS This is very similar to the TXF opcode, but lowers to `ld2dms` rather than `ld` on Gen7. V4: - add SHADER_OPCODE_TXF_MS to is_tex() functions, so regalloc thinks it actually writes the correct number of registers. Otherwise in nontrivial shaders some of the registers tend to get clobbered, producing bad results. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-01-24 08:35:15 +00:00
msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
else
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
break;
i965/fs: introduce non-compressed equivalent of tex_cms v2: introduces 'SHADER_OPCODE_TXF_UMS' also for gen8 Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-12-10 14:38:15 +00:00
case SHADER_OPCODE_TXF_UMS:
assert(brw->gen >= 7);
msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
break;
i965: Add shader opcode for sampling MCS surface Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Paul Berry <stereotype441@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-29 21:32:16 +00:00
case SHADER_OPCODE_TXF_MCS:
assert(brw->gen >= 7);
msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
break;
i965/fs: Generate LOD sampler message from ir_lod. v2: Support Ironlake as well. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-06 22:47:01 +00:00
case SHADER_OPCODE_LOD:
msg_type = GEN5_SAMPLER_MESSAGE_LOD;
break;
i965: add SHADER_OPCODE_TG4 Adds the Gen7 message IDs, a new SHADER_OPCODE_TG4 pseudo-op, and low-level support for emitting it via generate_tex(). V3: Updated for changes in master. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-31 09:31:12 +01:00
case SHADER_OPCODE_TG4:
i965/fs: Add support for shadow comparitors with gather4 Note that gather4_po_c's parameters are too long for SIMD16. It might be worth emitting 2xSIMD8 messages in this case at some point. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-10-10 07:57:29 +01:00
if (inst->shadow_compare) {
assert(brw->gen >= 7);
msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
} else {
assert(brw->gen >= 6);
msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
}
i965: add SHADER_OPCODE_TG4 Adds the Gen7 message IDs, a new SHADER_OPCODE_TG4 pseudo-op, and low-level support for emitting it via generate_tex(). V3: Updated for changes in master. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-31 09:31:12 +01:00
break;
i965: Add SHADER_OPCODE_TG4_OFFSET for gather with nonconstant offsets. The generator code ends up clearer this way than if we had to sniff via the message length. Implemented via the gather4_po message in hardware, which is present in Gen7 and later. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-10-08 09:42:10 +01:00
case SHADER_OPCODE_TG4_OFFSET:
assert(brw->gen >= 7);
i965/fs: Add support for shadow comparitors with gather4 Note that gather4_po_c's parameters are too long for SIMD16. It might be worth emitting 2xSIMD8 messages in this case at some point. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-10-10 07:57:29 +01:00
if (inst->shadow_compare) {
msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
} else {
msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
}
i965: Add SHADER_OPCODE_TG4_OFFSET for gather with nonconstant offsets. The generator code ends up clearer this way than if we had to sniff via the message length. Implemented via the gather4_po message in hardware, which is present in Gen7 and later. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-10-08 09:42:10 +01:00
break;
i965: Create a shared enum for hardware and compiler-internal opcodes. This should make gdbing more pleasant, and it might be used in sharing part of the codegen between the VS and FS backends.
2011-05-03 18:55:50 +01:00
default:
assert(!"not reached");
break;
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
}
} else {
switch (inst->opcode) {
i965: Rename texturing ops from FS_OPCODE to SHADER_OPCODE, except TXB. We'll be reusing most of these for the VS shortly. The one exception is TXB (texturing with LOD bias), which is explicitly forbidden in the VS. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-10-26 20:58:37 +01:00
case SHADER_OPCODE_TEX:
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
/* Note that G45 and older determines shadow compare and dispatch width
* from message length for most messages.
*/
i965/fs: Move brw_wm_compile::dispatch_width into fs_visitor. Also, rather than having brw_wm_fs_emit poke at it directly, make it a parameter to the fs_visitor constructor. All other changes generated by search and replace (with occasional whitespace fixup). v2: Make dispatch_width const (as suggested by Paul); fix doxygen mistake (pointed out by Eric); update for rebase. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-11-20 21:50:52 +00:00
assert(dispatch_width == 8);
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
if (inst->shadow_compare) {
assert(inst->mlen == 6);
} else {
assert(inst->mlen <= 4);
}
break;
case FS_OPCODE_TXB:
if (inst->shadow_compare) {
assert(inst->mlen == 6);
msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
} else {
assert(inst->mlen == 9);
msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
}
break;
i965: Rename texturing ops from FS_OPCODE to SHADER_OPCODE, except TXB. We'll be reusing most of these for the VS shortly. The one exception is TXB (texturing with LOD bias), which is explicitly forbidden in the VS. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-10-26 20:58:37 +01:00
case SHADER_OPCODE_TXL:
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
if (inst->shadow_compare) {
assert(inst->mlen == 6);
msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
} else {
assert(inst->mlen == 9);
msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
}
break;
i965: Rename texturing ops from FS_OPCODE to SHADER_OPCODE, except TXB. We'll be reusing most of these for the VS shortly. The one exception is TXB (texturing with LOD bias), which is explicitly forbidden in the VS. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-10-26 20:58:37 +01:00
case SHADER_OPCODE_TXD:
i965/fs: Add support for TXD with shadow comparisons. Our hardware doesn't have a sample_d_c message, so we have to do a regular sample_d and emit instructions to manually perform the comparison. This requires a state dependent recompile whenever the sampler's compare mode or function change. This adds the per-sampler comparison functions to brw_wm_prog_key, but only sets them when the sampler's compare mode is GL_COMPARE_R_TO_TEXTURE (i.e. only for shadow sampling). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-06-10 22:48:46 +01:00
/* There is no sample_d_c message; comparisons are done manually */
i965/fs: Add support for non-shadow textureGrad (TXD) on gen4. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-06-09 00:05:34 +01:00
assert(inst->mlen == 7 || inst->mlen == 10);
msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
break;
i965: Rename texturing ops from FS_OPCODE to SHADER_OPCODE, except TXB. We'll be reusing most of these for the VS shortly. The one exception is TXB (texturing with LOD bias), which is explicitly forbidden in the VS. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-10-26 20:58:37 +01:00
case SHADER_OPCODE_TXF:
i965/fs: Implement texelFetch() on Gen4. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-09-07 00:39:01 +01:00
assert(inst->mlen == 9);
msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
break;
i965: Rename texturing ops from FS_OPCODE to SHADER_OPCODE, except TXB. We'll be reusing most of these for the VS shortly. The one exception is TXB (texturing with LOD bias), which is explicitly forbidden in the VS. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-10-26 20:58:37 +01:00
case SHADER_OPCODE_TXS:
i965: Implement textureSize (TXS) on Gen4. Also, remove the BRW_SAMPLER_MESSAGE_SIMD8_RESINFO #define because there totally isn't a SIMD8 variant. Unfortunately, resinfo returns FLOAT32 on Broadwater/Crestline, unlike G45 which returns a proper UINT32. This turns out to be simple, however: when we emit MOVs to select the desired half of the SIMD16 result, we can simply override the register type to be float so it's converted to an integer. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2011-08-17 18:45:47 +01:00
assert(inst->mlen == 3);
msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO;
simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
break;
i965: Create a shared enum for hardware and compiler-internal opcodes. This should make gdbing more pleasant, and it might be used in sharing part of the codegen between the VS and FS backends.
2011-05-03 18:55:50 +01:00
default:
assert(!"not reached");
break;
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
}
}
assert(msg_type != -1);
if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
rlen = 8;
dst = vec16(dst);
}
i965/fs: Convert gen7 to using GRFs for texture messages. Looking at Lightsmark's shaders, the way we used MRFs (or in gen7's case, GRFs) was bad in a couple of ways. One was that it prevented compute-to-MRF for the common case of a texcoord that gets used exactly once, but where the texcoord setup all gets emitted before the texture calls (such as when it's a bare fragment shader input, which gets interpolated before processing main()). Another was that it introduced a bunch of dependencies that constrained scheduling, and forced waits for texture operations to be done before they are required. For example, we can now move the compute-to-MRF interpolation for the second texture send down after the first send. The downside is that this generally prevents remove_duplicate_mrf_writes() from doing anything, whereas previously it avoided work for the case of sampling from the same texcoord twice. However, I suspect that most of the win that originally justified that code was in avoiding the WAR stall on the first send, which this patch also avoids, rather than the small cost of the extra instruction. We see instruction count regressions in shaders in unigine, yofrankie, savage2, hon, and gstreamer. Improves GLB2.7 performance by 0.633628% +/- 0.491809% (n=121/125, avg of ~66fps, outliers below 61 dropped). Improves openarena performance by 1.01092% +/- 0.66897% (n=425). No significant difference on Lightsmark (n=44). v2: Squash in the fix for register unspilling for send-from-GRF, fixing a segfault in lightsmark. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Matt Turner <mattst88@gmail.com>
2013-10-10 01:17:59 +01:00
if (brw->gen >= 7 && inst->header_present && dispatch_width == 16) {
i965: Replace 8-wide and 16-wide with SIMD8 and SIMD16. Those are the terms used in the docs, and think "n-wide" was something I just happened to say. Note that shader-db needs updating for the INTEL_DEBUG=fs parsing. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-11-12 23:33:27 +00:00
/* The send-from-GRF for SIMD16 texturing with a header has an extra
i965/fs: Convert gen7 to using GRFs for texture messages. Looking at Lightsmark's shaders, the way we used MRFs (or in gen7's case, GRFs) was bad in a couple of ways. One was that it prevented compute-to-MRF for the common case of a texcoord that gets used exactly once, but where the texcoord setup all gets emitted before the texture calls (such as when it's a bare fragment shader input, which gets interpolated before processing main()). Another was that it introduced a bunch of dependencies that constrained scheduling, and forced waits for texture operations to be done before they are required. For example, we can now move the compute-to-MRF interpolation for the second texture send down after the first send. The downside is that this generally prevents remove_duplicate_mrf_writes() from doing anything, whereas previously it avoided work for the case of sampling from the same texcoord twice. However, I suspect that most of the win that originally justified that code was in avoiding the WAR stall on the first send, which this patch also avoids, rather than the small cost of the extra instruction. We see instruction count regressions in shaders in unigine, yofrankie, savage2, hon, and gstreamer. Improves GLB2.7 performance by 0.633628% +/- 0.491809% (n=121/125, avg of ~66fps, outliers below 61 dropped). Improves openarena performance by 1.01092% +/- 0.66897% (n=425). No significant difference on Lightsmark (n=44). v2: Squash in the fix for register unspilling for send-from-GRF, fixing a segfault in lightsmark. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Matt Turner <mattst88@gmail.com>
2013-10-10 01:17:59 +01:00
* hardware register allocated to it, which we need to skip over (since
* our coordinates in the payload are in the even-numbered registers,
* and the header comes right before the first one).
*/
assert(src.file == BRW_GENERAL_REGISTER_FILE);
src.nr++;
}
i965/fs: Move message header and texture offset setup to generate_tex(). Setting the texture offset bits in the message header involves very specific hardware register descriptions. As such, I feel it's better suited for the lower level "generate" layer that has direct access to the weird register layouts, rather than at the fs_inst abstraction layer. This also parallels the approach I took in the VS backend. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2012-08-05 04:33:13 +01:00
/* Load the message header if present. If there's a texture offset,
* we need to set it up explicitly and load the offset bitfield.
* Otherwise, we can use an implied move from g0 to the first message reg.
*/
i965/fs: Refactor sampler message header to duplicate less code. Previously, the code to copy g0 to the message header existed in two places - one for the texture offset case, and one for any other case. By treating texture_offset as a special case of header_present, we can remove this duplication and shorten the code. Future patches which add new header fields also won't have to add additional duplication. This also clarifies a confusing construct. The old code contained: } else if (inst->header_present) { if (brw->gen >= 7) { ...explicit copy from g0 to the message header... } else { /* Set up an implied move from g0 to the MRF. */ } } This looks like it might set up an implied move on Sandybridge, which doesn't support those. However, Sandybridge only uses a message header for texture offsets, so it would never hit this code path. The new code avoids this implicit knowledge by only setting up an implied move on Gen4-5. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-01-18 20:48:18 +00:00
if (inst->header_present) {
if (brw->gen < 6 && !inst->texture_offset) {
/* Set up an implied move from g0 to the MRF. */
src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
i965/fs: Convert gen7 to using GRFs for texture messages. Looking at Lightsmark's shaders, the way we used MRFs (or in gen7's case, GRFs) was bad in a couple of ways. One was that it prevented compute-to-MRF for the common case of a texcoord that gets used exactly once, but where the texcoord setup all gets emitted before the texture calls (such as when it's a bare fragment shader input, which gets interpolated before processing main()). Another was that it introduced a bunch of dependencies that constrained scheduling, and forced waits for texture operations to be done before they are required. For example, we can now move the compute-to-MRF interpolation for the second texture send down after the first send. The downside is that this generally prevents remove_duplicate_mrf_writes() from doing anything, whereas previously it avoided work for the case of sampling from the same texcoord twice. However, I suspect that most of the win that originally justified that code was in avoiding the WAR stall on the first send, which this patch also avoids, rather than the small cost of the extra instruction. We see instruction count regressions in shaders in unigine, yofrankie, savage2, hon, and gstreamer. Improves GLB2.7 performance by 0.633628% +/- 0.491809% (n=121/125, avg of ~66fps, outliers below 61 dropped). Improves openarena performance by 1.01092% +/- 0.66897% (n=425). No significant difference on Lightsmark (n=44). v2: Squash in the fix for register unspilling for send-from-GRF, fixing a segfault in lightsmark. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Matt Turner <mattst88@gmail.com>
2013-10-10 01:17:59 +01:00
} else {
i965/fs: Refactor sampler message header to duplicate less code. Previously, the code to copy g0 to the message header existed in two places - one for the texture offset case, and one for any other case. By treating texture_offset as a special case of header_present, we can remove this duplication and shorten the code. Future patches which add new header fields also won't have to add additional duplication. This also clarifies a confusing construct. The old code contained: } else if (inst->header_present) { if (brw->gen >= 7) { ...explicit copy from g0 to the message header... } else { /* Set up an implied move from g0 to the MRF. */ } } This looks like it might set up an implied move on Sandybridge, which doesn't support those. However, Sandybridge only uses a message header for texture offsets, so it would never hit this code path. The new code avoids this implicit knowledge by only setting up an implied move on Gen4-5. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-01-18 20:48:18 +00:00
struct brw_reg header_reg;
if (brw->gen >= 7) {
header_reg = src;
} else {
assert(inst->base_mrf != -1);
header_reg = brw_message_reg(inst->base_mrf);
}
i965/fs: Fix handling of sampler messages with header but zero offset Gather unconditionally uses a header, but in some cases the texture_offset value will be zero. V2: Don't introduce a bogus conversion. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-10-13 00:20:03 +01:00
brw_push_insn_state(p);
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
i965/fs: Refactor sampler message header to duplicate less code. Previously, the code to copy g0 to the message header existed in two places - one for the texture offset case, and one for any other case. By treating texture_offset as a special case of header_present, we can remove this duplication and shorten the code. Future patches which add new header fields also won't have to add additional duplication. This also clarifies a confusing construct. The old code contained: } else if (inst->header_present) { if (brw->gen >= 7) { ...explicit copy from g0 to the message header... } else { /* Set up an implied move from g0 to the MRF. */ } } This looks like it might set up an implied move on Sandybridge, which doesn't support those. However, Sandybridge only uses a message header for texture offsets, so it would never hit this code path. The new code avoids this implicit knowledge by only setting up an implied move on Gen4-5. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-01-18 20:48:18 +00:00
/* Explicitly set up the message header by copying g0 to the MRF. */
brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
if (inst->texture_offset) {
/* Set the offset bits in DWord 2. */
brw_MOV(p, get_element_ud(header_reg, 2),
brw_imm_ud(inst->texture_offset));
}
i965/fs: Support arbitrarily large sampler state indices on Haswell+. The message descriptor's "Sampler Index" field is only 4 bits (on all generations of hardware), so it can only represent indices 0 through 15. Haswell introduced a new field in the message header - "Sampler State Pointer". Normally, this is copied straight from g0, but we can also add a byte offset (as long as it's a multiple of 32). This patch uses a "Sampler State Pointer" offset to select a group of 16 sampler states, and then uses the "Sampler Index" field to select the state within that group. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-01-18 21:29:39 +00:00
if (inst->sampler >= 16) {
/* The "Sampler Index" field can only store values between 0 and 15.
* However, we can add an offset to the "Sampler State Pointer"
* field, effectively selecting a different set of 16 samplers.
*
* The "Sampler State Pointer" needs to be aligned to a 32-byte
* offset, and each sampler state is only 16-bytes, so we can't
* exclusively use the offset - we have to use both.
*/
i965: Extend is_haswell checks to gen >= 8 in Gen4-7 generators. We're going to use fs_generator/vec4_generator for Gen8+ code soon, thanks to the new brw_instruction API. When we do, we'll generally want to take the Haswell paths on Gen8+ as well. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-08 07:52:37 +01:00
assert(brw->gen >= 8 || brw->is_haswell);
i965/fs: Support arbitrarily large sampler state indices on Haswell+. The message descriptor's "Sampler Index" field is only 4 bits (on all generations of hardware), so it can only represent indices 0 through 15. Haswell introduced a new field in the message header - "Sampler State Pointer". Normally, this is copied straight from g0, but we can also add a byte offset (as long as it's a multiple of 32). This patch uses a "Sampler State Pointer" offset to select a group of 16 sampler states, and then uses the "Sampler Index" field to select the state within that group. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-01-18 21:29:39 +00:00
brw_ADD(p,
get_element_ud(header_reg, 3),
get_element_ud(brw_vec8_grf(0, 0), 3),
brw_imm_ud(16 * (inst->sampler / 16) *
sizeof(gen7_sampler_state)));
}
i965/fs: Fix handling of sampler messages with header but zero offset Gather unconditionally uses a header, but in some cases the texture_offset value will be zero. V2: Don't introduce a bogus conversion. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-10-13 00:20:03 +01:00
brw_pop_insn_state(p);
}
i965/fs: Move message header and texture offset setup to generate_tex(). Setting the texture offset bits in the message header involves very specific hardware register descriptions. As such, I feel it's better suited for the lower level "generate" layer that has direct access to the weird register layouts, rather than at the fs_inst abstraction layer. This also parallels the approach I took in the VS backend. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2012-08-05 04:33:13 +01:00
}
i965: Add SHADER_OPCODE_TG4_OFFSET for gather with nonconstant offsets. The generator code ends up clearer this way than if we had to sniff via the message length. Implemented via the gather4_po message in hardware, which is present in Gen7 and later. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-10-08 09:42:10 +01:00
uint32_t surface_index = ((inst->opcode == SHADER_OPCODE_TG4 ||
inst->opcode == SHADER_OPCODE_TG4_OFFSET)
i965/fs: Replace c->prog_data with a direct reference in the generators. 'c' is going away. This is also a bit shorter. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-05-14 08:20:24 +01:00
? prog_data->base.binding_table.gather_texture_start
: prog_data->base.binding_table.texture_start) + inst->sampler;
i965: use gather slots in the binding table for gather4. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-09-15 07:23:14 +01:00
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
brw_SAMPLE(p,
retype(dst, BRW_REGISTER_TYPE_UW),
inst->base_mrf,
src,
i965: use gather slots in the binding table for gather4. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-09-15 07:23:14 +01:00
surface_index,
i965/fs: Support arbitrarily large sampler state indices on Haswell+. The message descriptor's "Sampler Index" field is only 4 bits (on all generations of hardware), so it can only represent indices 0 through 15. Haswell introduced a new field in the message header - "Sampler State Pointer". Normally, this is copied straight from g0, but we can also add a byte offset (as long as it's a multiple of 32). This patch uses a "Sampler State Pointer" offset to select a group of 16 sampler states, and then uses the "Sampler Index" field to select the state within that group. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-01-18 21:29:39 +00:00
inst->sampler % 16,
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
msg_type,
rlen,
inst->mlen,
inst->header_present,
i965/gen4: Fix sampling from integer textures. On original gen4, the surface format didn't determine the return data type from sampling like it does on g45 and later. Fixes GL_EXT_texture_integer/texture_integer_glsl130 Reviewed-by: Paul Berry <stereotype441@gmail.com>
2011-11-10 00:07:57 +00:00
simd_mode,
return_format);
i965/fs: Track the binding table size in brw_wm_prog_data. By tracking the maximum surface index used by the shader, we know just how small we can make the binding table. Since it depends entirely on the shader program, we can just compute it once at compile time, rather than at binding table emit time (which happens during drawing). v2: Store binding_table_size, rather than max_surface_index, for consistency with the VS (which needs to be able to represent 0 surfaces). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-08-15 03:49:33 +01:00
i965/fs: Replace c->prog_data with a direct reference in the generators. 'c' is going away. This is also a bit shorter. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-05-14 08:20:24 +01:00
brw_mark_surface_used(&prog_data->base, surface_index);
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
}
/* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
* looking like:
*
* arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
*
i965: compute DDX in a subspan based only on top row Consider only the top-left and top-right pixels to approximate DDX in a 2x2 subspan, unless the application requests a more accurate approximation via GL_FRAGMENT_SHADER_DERIVATIVE_HINT or this optimization is disabled from the new driconf option disable_derivative_optimization. This results in a less accurate approximation. However, it improves the performance of Xonotic with Ultra settings by 24.3879% +/- 0.832202% (at 95.0% confidence) on Haswell. No noticeable image quality difference observed. The improvement comes from faster sample_d. It seems, on Haswell, some optimizations are introduced to allow faster sample_d when all pixels in a subspan have the same derivative. I considered SAMPLE_STATE too, which allows one to control the quality of sample_d on Haswell. But it gave much worse image quality without giving better performance comparing to this change. No piglit quick.tests regression on Haswell (tested with v1). v2: better guess for precompile program key Signed-off-by: Chia-I Wu <olv@lunarg.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2013-09-12 06:00:52 +01:00
* Ideally, we want to produce:
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
*
* DDX DDY
* dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
* (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
* (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
* (ss0.br - ss0.bl) (ss0.tr - ss0.br)
* (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
* (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
* (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
* (ss1.br - ss1.bl) (ss1.tr - ss1.br)
*
* and add another set of two more subspans if in 16-pixel dispatch mode.
*
* For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
* for each pair, and vertstride = 2 jumps us 2 elements after processing a
i965: compute DDX in a subspan based only on top row Consider only the top-left and top-right pixels to approximate DDX in a 2x2 subspan, unless the application requests a more accurate approximation via GL_FRAGMENT_SHADER_DERIVATIVE_HINT or this optimization is disabled from the new driconf option disable_derivative_optimization. This results in a less accurate approximation. However, it improves the performance of Xonotic with Ultra settings by 24.3879% +/- 0.832202% (at 95.0% confidence) on Haswell. No noticeable image quality difference observed. The improvement comes from faster sample_d. It seems, on Haswell, some optimizations are introduced to allow faster sample_d when all pixels in a subspan have the same derivative. I considered SAMPLE_STATE too, which allows one to control the quality of sample_d on Haswell. But it gave much worse image quality without giving better performance comparing to this change. No piglit quick.tests regression on Haswell (tested with v1). v2: better guess for precompile program key Signed-off-by: Chia-I Wu <olv@lunarg.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2013-09-12 06:00:52 +01:00
* pair. But the ideal approximation may impose a huge performance cost on
* sample_d. On at least Haswell, sample_d instruction does some
* optimizations if the same LOD is used for all pixels in the subspan.
*
i965/fs: Improve accuracy of dFdy() to match dFdx(). Previously, we computed dFdy() using the following instruction: add(8) dst<1>F src<4,4,0)F -src.2<4,4,0>F { align1 1Q } That had the disadvantage that it computed the same value for all 4 pixels of a 2x2 subspan, which meant that it was less accurate than dFdx(). This patch changes it to the following instruction when c->key.high_quality_derivatives is set: add(8) dst<1>F src<4,4,1>.xyxyF -src<4,4,1>.zwzwF { align16 1Q } This gives it comparable accuracy to dFdx(). Unfortunately, align16 instructions can't be compressed, so in SIMD16 shaders, instead of emitting this instruction: add(16) dst<1>F src<4,4,1>.xyxyF -src<4,4,1>.zwzwF { align16 1H } We need to unroll to two instructions: add(8) dst<1>F src<4,4,1>.xyxyF -src<4,4,1>.zwzwF { align16 1Q } add(8) (dst+1)<1>F (src+1)<4,4,1>.xyxyF -(src+1)<4,4,1>.zwzwF { align16 2Q } Fixes piglit test spec/glsl-1.10/execution/fs-dfdy-accuracy. Acked-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-09-20 17:04:31 +01:00
* For DDY, we need to use ALIGN16 mode since it's capable of doing the
* appropriate swizzling.
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
*/
void
i965/fs: Split final assembly code generation out of fs_visitor. Compiling shaders requires several main steps: 1. Generating FS IR from either GLSL IR or Mesa IR 2. Optimizing the IR 3. Register allocation 4. Generating assembly code This patch splits out step 4 into a separate class named "fs_generator." There are several reasons for doing so: 1. Future hardware has a different instruction encoding. Splitting this out will allow us to replace fs_generator (which relies heavily on the brw_eu_emit.c code and struct brw_instruction) with a new code generator that writes the new format. 2. It reduces the size of the fs_visitor monolith. (Arguably, a lot more should be split out, but that's left for "future work.") 3. Separate namespaces allow us to make helper functions for generating instructions in both classes: ADD() can exist in fs_visitor and create IR, while ADD() in fs_generator() can create brw_instructions. (Patches for this upcoming.) Furthermore, this patch changes the order of operations slightly. Rather than doing steps 1-4 for SIMD8, then 1-4 for SIMD16, we now: - Do steps 1-3 for SIMD8, then repeat 1-3 for SIMD16 - Generate final assembly code for both modes together This is because the frontend work can be done independently, but final assembly generation needs to pack both into a single program store to feed the GPU. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-11-09 09:05:47 +00:00
fs_generator::generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
{
i965: compute DDX in a subspan based only on top row Consider only the top-left and top-right pixels to approximate DDX in a 2x2 subspan, unless the application requests a more accurate approximation via GL_FRAGMENT_SHADER_DERIVATIVE_HINT or this optimization is disabled from the new driconf option disable_derivative_optimization. This results in a less accurate approximation. However, it improves the performance of Xonotic with Ultra settings by 24.3879% +/- 0.832202% (at 95.0% confidence) on Haswell. No noticeable image quality difference observed. The improvement comes from faster sample_d. It seems, on Haswell, some optimizations are introduced to allow faster sample_d when all pixels in a subspan have the same derivative. I considered SAMPLE_STATE too, which allows one to control the quality of sample_d on Haswell. But it gave much worse image quality without giving better performance comparing to this change. No piglit quick.tests regression on Haswell (tested with v1). v2: better guess for precompile program key Signed-off-by: Chia-I Wu <olv@lunarg.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2013-09-12 06:00:52 +01:00
unsigned vstride, width;
i965/fs: Replace c->key with a direct reference in the generators. 'c' is going away. This is also a bit shorter. Marking the key pointer as const will also deter people from changing it in these classes, as that's absolutely not OK. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-05-14 08:24:50 +01:00
if (key->high_quality_derivatives) {
i965: compute DDX in a subspan based only on top row Consider only the top-left and top-right pixels to approximate DDX in a 2x2 subspan, unless the application requests a more accurate approximation via GL_FRAGMENT_SHADER_DERIVATIVE_HINT or this optimization is disabled from the new driconf option disable_derivative_optimization. This results in a less accurate approximation. However, it improves the performance of Xonotic with Ultra settings by 24.3879% +/- 0.832202% (at 95.0% confidence) on Haswell. No noticeable image quality difference observed. The improvement comes from faster sample_d. It seems, on Haswell, some optimizations are introduced to allow faster sample_d when all pixels in a subspan have the same derivative. I considered SAMPLE_STATE too, which allows one to control the quality of sample_d on Haswell. But it gave much worse image quality without giving better performance comparing to this change. No piglit quick.tests regression on Haswell (tested with v1). v2: better guess for precompile program key Signed-off-by: Chia-I Wu <olv@lunarg.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2013-09-12 06:00:52 +01:00
/* produce accurate derivatives */
vstride = BRW_VERTICAL_STRIDE_2;
width = BRW_WIDTH_2;
}
else {
/* replicate the derivative at the top-left pixel to other pixels */
vstride = BRW_VERTICAL_STRIDE_4;
width = BRW_WIDTH_4;
}
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
BRW_REGISTER_TYPE_F,
i965: compute DDX in a subspan based only on top row Consider only the top-left and top-right pixels to approximate DDX in a 2x2 subspan, unless the application requests a more accurate approximation via GL_FRAGMENT_SHADER_DERIVATIVE_HINT or this optimization is disabled from the new driconf option disable_derivative_optimization. This results in a less accurate approximation. However, it improves the performance of Xonotic with Ultra settings by 24.3879% +/- 0.832202% (at 95.0% confidence) on Haswell. No noticeable image quality difference observed. The improvement comes from faster sample_d. It seems, on Haswell, some optimizations are introduced to allow faster sample_d when all pixels in a subspan have the same derivative. I considered SAMPLE_STATE too, which allows one to control the quality of sample_d on Haswell. But it gave much worse image quality without giving better performance comparing to this change. No piglit quick.tests regression on Haswell (tested with v1). v2: better guess for precompile program key Signed-off-by: Chia-I Wu <olv@lunarg.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2013-09-12 06:00:52 +01:00
vstride,
width,
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
BRW_HORIZONTAL_STRIDE_0,
BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
BRW_REGISTER_TYPE_F,
i965: compute DDX in a subspan based only on top row Consider only the top-left and top-right pixels to approximate DDX in a 2x2 subspan, unless the application requests a more accurate approximation via GL_FRAGMENT_SHADER_DERIVATIVE_HINT or this optimization is disabled from the new driconf option disable_derivative_optimization. This results in a less accurate approximation. However, it improves the performance of Xonotic with Ultra settings by 24.3879% +/- 0.832202% (at 95.0% confidence) on Haswell. No noticeable image quality difference observed. The improvement comes from faster sample_d. It seems, on Haswell, some optimizations are introduced to allow faster sample_d when all pixels in a subspan have the same derivative. I considered SAMPLE_STATE too, which allows one to control the quality of sample_d on Haswell. But it gave much worse image quality without giving better performance comparing to this change. No piglit quick.tests regression on Haswell (tested with v1). v2: better guess for precompile program key Signed-off-by: Chia-I Wu <olv@lunarg.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2013-09-12 06:00:52 +01:00
vstride,
width,
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
BRW_HORIZONTAL_STRIDE_0,
BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
brw_ADD(p, dst, src0, negate(src1));
}
i965: Compute dFdy() correctly for FBOs. On i965, dFdx() and dFdy() are computed by taking advantage of the fact that each consecutive set of 4 pixels dispatched to the fragment shader always constitutes a contiguous 2x2 block of pixels in a fixed arrangement known as a "sub-span". So we calculate dFdx() by taking the difference between the values computed for the left and right halves of the sub-span, and we calculate dFdy() by taking the difference between the values computed for the top and bottom halves of the sub-span. However, there's a subtlety when FBOs are in use: since FBOs use a coordinate system where the origin is at the upper left, and window system framebuffers use a coordinate system where the origin is at the lower left, the computation of dFdy() needs to be negated for FBOs. This patch modifies the fragment shader back-ends to negate the value of dFdy() when an FBO is in use. It also modifies the code that populates the program key (brw_wm_populate_key() and brw_fs_precompile()) so that they always record in the program key whether we are rendering to an FBO or to a window system framebuffer; this ensures that the fragment shader will get recompiled when switching between FBO and non-FBO use. This will result in unnecessary recompiles of fragment shaders that don't use dFdy(). To fix that, we will need to adapt the GLSL and NV_fragment_program front-ends to record whether or not a given shader uses dFdy(). I plan to implement this in a future patch series; I've left FIXME comments in the code as a reminder. Fixes Piglit test "fbo-deriv". NOTE: This is a candidate for stable release branches. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-06-20 21:40:45 +01:00
/* The negate_value boolean is used to negate the derivative computation for
* FBOs, since they place the origin at the upper left instead of the lower
* left.
*/
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
void
i965/fs: Split final assembly code generation out of fs_visitor. Compiling shaders requires several main steps: 1. Generating FS IR from either GLSL IR or Mesa IR 2. Optimizing the IR 3. Register allocation 4. Generating assembly code This patch splits out step 4 into a separate class named "fs_generator." There are several reasons for doing so: 1. Future hardware has a different instruction encoding. Splitting this out will allow us to replace fs_generator (which relies heavily on the brw_eu_emit.c code and struct brw_instruction) with a new code generator that writes the new format. 2. It reduces the size of the fs_visitor monolith. (Arguably, a lot more should be split out, but that's left for "future work.") 3. Separate namespaces allow us to make helper functions for generating instructions in both classes: ADD() can exist in fs_visitor and create IR, while ADD() in fs_generator() can create brw_instructions. (Patches for this upcoming.) Furthermore, this patch changes the order of operations slightly. Rather than doing steps 1-4 for SIMD8, then 1-4 for SIMD16, we now: - Do steps 1-3 for SIMD8, then repeat 1-3 for SIMD16 - Generate final assembly code for both modes together This is because the frontend work can be done independently, but final assembly generation needs to pack both into a single program store to feed the GPU. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-11-09 09:05:47 +00:00
fs_generator::generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
i965: Compute dFdy() correctly for FBOs. On i965, dFdx() and dFdy() are computed by taking advantage of the fact that each consecutive set of 4 pixels dispatched to the fragment shader always constitutes a contiguous 2x2 block of pixels in a fixed arrangement known as a "sub-span". So we calculate dFdx() by taking the difference between the values computed for the left and right halves of the sub-span, and we calculate dFdy() by taking the difference between the values computed for the top and bottom halves of the sub-span. However, there's a subtlety when FBOs are in use: since FBOs use a coordinate system where the origin is at the upper left, and window system framebuffers use a coordinate system where the origin is at the lower left, the computation of dFdy() needs to be negated for FBOs. This patch modifies the fragment shader back-ends to negate the value of dFdy() when an FBO is in use. It also modifies the code that populates the program key (brw_wm_populate_key() and brw_fs_precompile()) so that they always record in the program key whether we are rendering to an FBO or to a window system framebuffer; this ensures that the fragment shader will get recompiled when switching between FBO and non-FBO use. This will result in unnecessary recompiles of fragment shaders that don't use dFdy(). To fix that, we will need to adapt the GLSL and NV_fragment_program front-ends to record whether or not a given shader uses dFdy(). I plan to implement this in a future patch series; I've left FIXME comments in the code as a reminder. Fixes Piglit test "fbo-deriv". NOTE: This is a candidate for stable release branches. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-06-20 21:40:45 +01:00
bool negate_value)
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
{
i965/fs: Replace c->key with a direct reference in the generators. 'c' is going away. This is also a bit shorter. Marking the key pointer as const will also deter people from changing it in these classes, as that's absolutely not OK. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-05-14 08:24:50 +01:00
if (key->high_quality_derivatives) {
i965/fs: Only unroll high-accuracy dFdy() from SIMD16 to SIMD8 on gen4 and IVB. In commit 800610f (i965/fs: Improve accuracy of dFdy() to match dFdx()) I unrolled the high-accuracy dFdy() computation from a single SIMD16 instruction to two SIMD8 instructions because of text I found in the i965 (gen4) PRM saying that instruction compression could not be used in align16 mode. I couldn't find similar text in later hardware docs, and I observed problems trying to use instruction compression on align16 mode on Ivy Bridge, so I assumed that the restriction still applied and the associated documentation had simply been lost. After consultation with the hardware engineers, it turns out this is not the case. In point of fact, the restriction was dropped in gen5, re-introduced in Ivy Bridge, and dropped again in Haswell. The reason I didn't notice this is that in the Ivy Bridge documentation, the restriction was in a different section, and described using different language. Now that we know that the restriction only applies to Gen4 and Ivy Bridge, we can limit the unrolling to those platforms. Tested on gen5, gen6, and gen7 (both Ivy Bridge and Haswell). Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-10-22 13:56:37 +01:00
/* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
* Region Restrictions):
*
* In Align16 access mode, SIMD16 is not allowed for DW operations
* and SIMD8 is not allowed for DF operations.
*
* In this context, "DW operations" means "operations acting on 32-bit
* values", so it includes operations on floats.
*
* Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
* (Instruction Compression -> Rules and Restrictions):
*
* A compressed instruction must be in Align1 access mode. Align16
* mode instructions cannot be compressed.
*
* Similar text exists in the g45 PRM.
*
* On these platforms, if we're building a SIMD16 shader, we need to
* manually unroll to a pair of SIMD8 instructions.
*/
bool unroll_to_simd8 =
(dispatch_width == 16 &&
(brw->gen == 4 || (brw->gen == 7 && !brw->is_haswell)));
i965/fs: Improve accuracy of dFdy() to match dFdx(). Previously, we computed dFdy() using the following instruction: add(8) dst<1>F src<4,4,0)F -src.2<4,4,0>F { align1 1Q } That had the disadvantage that it computed the same value for all 4 pixels of a 2x2 subspan, which meant that it was less accurate than dFdx(). This patch changes it to the following instruction when c->key.high_quality_derivatives is set: add(8) dst<1>F src<4,4,1>.xyxyF -src<4,4,1>.zwzwF { align16 1Q } This gives it comparable accuracy to dFdx(). Unfortunately, align16 instructions can't be compressed, so in SIMD16 shaders, instead of emitting this instruction: add(16) dst<1>F src<4,4,1>.xyxyF -src<4,4,1>.zwzwF { align16 1H } We need to unroll to two instructions: add(8) dst<1>F src<4,4,1>.xyxyF -src<4,4,1>.zwzwF { align16 1Q } add(8) (dst+1)<1>F (src+1)<4,4,1>.xyxyF -(src+1)<4,4,1>.zwzwF { align16 2Q } Fixes piglit test spec/glsl-1.10/execution/fs-dfdy-accuracy. Acked-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-09-20 17:04:31 +01:00
/* produce accurate derivatives */
struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
BRW_REGISTER_TYPE_F,
BRW_VERTICAL_STRIDE_4,
BRW_WIDTH_4,
BRW_HORIZONTAL_STRIDE_1,
BRW_SWIZZLE_XYXY, WRITEMASK_XYZW);
struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
BRW_REGISTER_TYPE_F,
BRW_VERTICAL_STRIDE_4,
BRW_WIDTH_4,
BRW_HORIZONTAL_STRIDE_1,
BRW_SWIZZLE_ZWZW, WRITEMASK_XYZW);
brw_push_insn_state(p);
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_access_mode(p, BRW_ALIGN_16);
i965/fs: Only unroll high-accuracy dFdy() from SIMD16 to SIMD8 on gen4 and IVB. In commit 800610f (i965/fs: Improve accuracy of dFdy() to match dFdx()) I unrolled the high-accuracy dFdy() computation from a single SIMD16 instruction to two SIMD8 instructions because of text I found in the i965 (gen4) PRM saying that instruction compression could not be used in align16 mode. I couldn't find similar text in later hardware docs, and I observed problems trying to use instruction compression on align16 mode on Ivy Bridge, so I assumed that the restriction still applied and the associated documentation had simply been lost. After consultation with the hardware engineers, it turns out this is not the case. In point of fact, the restriction was dropped in gen5, re-introduced in Ivy Bridge, and dropped again in Haswell. The reason I didn't notice this is that in the Ivy Bridge documentation, the restriction was in a different section, and described using different language. Now that we know that the restriction only applies to Gen4 and Ivy Bridge, we can limit the unrolling to those platforms. Tested on gen5, gen6, and gen7 (both Ivy Bridge and Haswell). Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-10-22 13:56:37 +01:00
if (unroll_to_simd8)
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
i965/fs: Improve accuracy of dFdy() to match dFdx(). Previously, we computed dFdy() using the following instruction: add(8) dst<1>F src<4,4,0)F -src.2<4,4,0>F { align1 1Q } That had the disadvantage that it computed the same value for all 4 pixels of a 2x2 subspan, which meant that it was less accurate than dFdx(). This patch changes it to the following instruction when c->key.high_quality_derivatives is set: add(8) dst<1>F src<4,4,1>.xyxyF -src<4,4,1>.zwzwF { align16 1Q } This gives it comparable accuracy to dFdx(). Unfortunately, align16 instructions can't be compressed, so in SIMD16 shaders, instead of emitting this instruction: add(16) dst<1>F src<4,4,1>.xyxyF -src<4,4,1>.zwzwF { align16 1H } We need to unroll to two instructions: add(8) dst<1>F src<4,4,1>.xyxyF -src<4,4,1>.zwzwF { align16 1Q } add(8) (dst+1)<1>F (src+1)<4,4,1>.xyxyF -(src+1)<4,4,1>.zwzwF { align16 2Q } Fixes piglit test spec/glsl-1.10/execution/fs-dfdy-accuracy. Acked-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-09-20 17:04:31 +01:00
if (negate_value)
brw_ADD(p, dst, src1, negate(src0));
else
brw_ADD(p, dst, src0, negate(src1));
i965/fs: Only unroll high-accuracy dFdy() from SIMD16 to SIMD8 on gen4 and IVB. In commit 800610f (i965/fs: Improve accuracy of dFdy() to match dFdx()) I unrolled the high-accuracy dFdy() computation from a single SIMD16 instruction to two SIMD8 instructions because of text I found in the i965 (gen4) PRM saying that instruction compression could not be used in align16 mode. I couldn't find similar text in later hardware docs, and I observed problems trying to use instruction compression on align16 mode on Ivy Bridge, so I assumed that the restriction still applied and the associated documentation had simply been lost. After consultation with the hardware engineers, it turns out this is not the case. In point of fact, the restriction was dropped in gen5, re-introduced in Ivy Bridge, and dropped again in Haswell. The reason I didn't notice this is that in the Ivy Bridge documentation, the restriction was in a different section, and described using different language. Now that we know that the restriction only applies to Gen4 and Ivy Bridge, we can limit the unrolling to those platforms. Tested on gen5, gen6, and gen7 (both Ivy Bridge and Haswell). Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-10-22 13:56:37 +01:00
if (unroll_to_simd8) {
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
i965/fs: Improve accuracy of dFdy() to match dFdx(). Previously, we computed dFdy() using the following instruction: add(8) dst<1>F src<4,4,0)F -src.2<4,4,0>F { align1 1Q } That had the disadvantage that it computed the same value for all 4 pixels of a 2x2 subspan, which meant that it was less accurate than dFdx(). This patch changes it to the following instruction when c->key.high_quality_derivatives is set: add(8) dst<1>F src<4,4,1>.xyxyF -src<4,4,1>.zwzwF { align16 1Q } This gives it comparable accuracy to dFdx(). Unfortunately, align16 instructions can't be compressed, so in SIMD16 shaders, instead of emitting this instruction: add(16) dst<1>F src<4,4,1>.xyxyF -src<4,4,1>.zwzwF { align16 1H } We need to unroll to two instructions: add(8) dst<1>F src<4,4,1>.xyxyF -src<4,4,1>.zwzwF { align16 1Q } add(8) (dst+1)<1>F (src+1)<4,4,1>.xyxyF -(src+1)<4,4,1>.zwzwF { align16 2Q } Fixes piglit test spec/glsl-1.10/execution/fs-dfdy-accuracy. Acked-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-09-20 17:04:31 +01:00
src0 = sechalf(src0);
src1 = sechalf(src1);
dst = sechalf(dst);
if (negate_value)
brw_ADD(p, dst, src1, negate(src0));
else
brw_ADD(p, dst, src0, negate(src1));
}
brw_pop_insn_state(p);
} else {
/* replicate the derivative at the top-left pixel to other pixels */
struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
BRW_REGISTER_TYPE_F,
BRW_VERTICAL_STRIDE_4,
BRW_WIDTH_4,
BRW_HORIZONTAL_STRIDE_0,
BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
BRW_REGISTER_TYPE_F,
BRW_VERTICAL_STRIDE_4,
BRW_WIDTH_4,
BRW_HORIZONTAL_STRIDE_0,
BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
if (negate_value)
brw_ADD(p, dst, src1, negate(src0));
else
brw_ADD(p, dst, src0, negate(src1));
}
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
}
i965/fs: Improve performance of shaders that start out with a discard. I had tried this in the past, but ran into trouble with applications that sample from undiscarded pixels in the same subspan. To fix that issue, only jump to the end for an entire subspan at a time. Improves GLbenchmark 2.7 (1024x768) performance by 7.9 +/- 1.5% (n=8). v2: Drop the br variable in the jump instruction -- if I ever do jumps pre-gen6, it'll be a different code block anyway since we don't have HALT until gen6. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-06 18:15:08 +00:00
void
fs_generator::generate_discard_jump(fs_inst *inst)
{
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 08:36:46 +01:00
assert(brw->gen >= 6);
i965/fs: Improve performance of shaders that start out with a discard. I had tried this in the past, but ran into trouble with applications that sample from undiscarded pixels in the same subspan. To fix that issue, only jump to the end for an entire subspan at a time. Improves GLbenchmark 2.7 (1024x768) performance by 7.9 +/- 1.5% (n=8). v2: Drop the br variable in the jump instruction -- if I ever do jumps pre-gen6, it'll be a different code block anyway since we don't have HALT until gen6. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-06 18:15:08 +00:00
/* This HALT will be patched up at FB write time to point UIP at the end of
* the program, and at brw_uip_jip() JIP will be set to the end of the
* current block (or the program).
*/
this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
brw_push_insn_state(p);
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
i965/fs: Improve performance of shaders that start out with a discard. I had tried this in the past, but ran into trouble with applications that sample from undiscarded pixels in the same subspan. To fix that issue, only jump to the end for an entire subspan at a time. Improves GLbenchmark 2.7 (1024x768) performance by 7.9 +/- 1.5% (n=8). v2: Drop the br variable in the jump instruction -- if I ever do jumps pre-gen6, it'll be a different code block anyway since we don't have HALT until gen6. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-06 18:15:08 +00:00
gen6_HALT(p);
brw_pop_insn_state(p);
}
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
void
i965: Merge together opcodes for SHADER_OPCODE_GEN4_SCRATCH_READ/WRITE I'm going to be introducing gen7 variants, and the previous naming was going to get confusing. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-10-16 19:45:06 +01:00
fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
{
assert(inst->mlen != 0);
brw_MOV(p,
retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_UD),
retype(src, BRW_REGISTER_TYPE_UD));
i965/fs: Fix register spilling for 16-wide. Things blew up when I enabled the debug register spill code without disabling 16-wide, so I decided to just fix 16-wide spilling. We still don't generate 16-wide when register spilling happens as part of allocation (since we expect it to be slower), but now we can experiment with allowing it in some cases in the future. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-10-16 20:16:51 +01:00
brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
i965/fs: Fix message setup for SIMD8 spills. In the SIMD16 spilling changes, I replaced a "1" in the spill path with "mlen", but obviously it wasn't mlen before because spills have the g0 header along with the payload. The interface I was trying to use was asking for how many physical regs we're writing, so we're looking for "1" or "2". I'm guessing this actually passed piglit because the high 8 bits of the execution mask in SIMD8 mode are all 0s. Cc: "10.0" <mesa-stable@lists.freedesktop.org> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-11-05 06:56:33 +00:00
dispatch_width / 8, inst->offset);
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
}
void
i965: Merge together opcodes for SHADER_OPCODE_GEN4_SCRATCH_READ/WRITE I'm going to be introducing gen7 variants, and the previous naming was going to get confusing. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-10-16 19:45:06 +01:00
fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst)
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
{
assert(inst->mlen != 0);
i965/fs: Fix register spilling for 16-wide. Things blew up when I enabled the debug register spill code without disabling 16-wide, so I decided to just fix 16-wide spilling. We still don't generate 16-wide when register spilling happens as part of allocation (since we expect it to be slower), but now we can experiment with allowing it in some cases in the future. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-10-16 20:16:51 +01:00
brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf),
dispatch_width / 8, inst->offset);
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
}
i965/fs: Use the gen7 scratch read opcode when possible. This avoids a lot of message setup we had to do otherwise. Improves GLB2.7 performance with register spilling force enabled by 1.6442% +/- 0.553218% (n=4). v2: Use BRW_PREDICATE_NONE, improve a comment (by Paul). Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-10-16 19:51:22 +01:00
void
fs_generator::generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst)
{
gen7_block_read_scratch(p, dst, dispatch_width / 8, inst->offset);
}
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
void
i965/fs: Rename the existing pull constant load opcode. We're going to use another send message for handling loads with a varying per-fragment array index.
2012-11-07 18:42:34 +00:00
fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
struct brw_reg dst,
struct brw_reg index,
struct brw_reg offset)
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
{
assert(inst->mlen != 0);
i965/fs: Communicate the pull constant block read parameters through fs_regs. I wanted to add the surface index as a variable value for UBO support, and a reg seemed like the obvious way to go. This exposes more of the information to CSE, which we'll probably want to apply to pull constant loads for UBOs eventually (you might access 4 floats in a row, each of which would produce an oword block read of the same block). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-06-20 23:41:14 +01:00
assert(index.file == BRW_IMMEDIATE_VALUE &&
index.type == BRW_REGISTER_TYPE_UD);
uint32_t surf_index = index.dw1.ud;
assert(offset.file == BRW_IMMEDIATE_VALUE &&
offset.type == BRW_REGISTER_TYPE_UD);
uint32_t read_offset = offset.dw1.ud;
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
i965/fs: Communicate the pull constant block read parameters through fs_regs. I wanted to add the surface index as a variable value for UBO support, and a reg seemed like the obvious way to go. This exposes more of the information to CSE, which we'll probably want to apply to pull constant loads for UBOs eventually (you might access 4 floats in a row, each of which would produce an oword block read of the same block). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-06-20 23:41:14 +01:00
read_offset, surf_index);
i965/fs: Track the binding table size in brw_wm_prog_data. By tracking the maximum surface index used by the shader, we know just how small we can make the binding table. Since it depends entirely on the shader program, we can just compute it once at compile time, rather than at binding table emit time (which happens during drawing). v2: Store binding_table_size, rather than max_surface_index, for consistency with the VS (which needs to be able to represent 0 surfaces). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-08-15 03:49:33 +01:00
i965/fs: Replace c->prog_data with a direct reference in the generators. 'c' is going away. This is also a bit shorter. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-05-14 08:20:24 +01:00
brw_mark_surface_used(&prog_data->base, surf_index);
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
}
i965/fs: Set up gen7 UBO loads as sends from GRFs. This gives the instruction scheduler a chance to schedule between the loads, whereas before it was restricted due to the dependencies between the MRFs for setting them up. For one shader in gles3conform, it goes from getting stuck in register allocation for as long as anybody's bothered to leave it running down to 23 seconds, thanks to the LIFO scheduling. Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-05 08:06:30 +00:00
void
fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
struct brw_reg dst,
struct brw_reg index,
struct brw_reg offset)
{
assert(inst->mlen == 0);
assert(index.file == BRW_IMMEDIATE_VALUE &&
index.type == BRW_REGISTER_TYPE_UD);
uint32_t surf_index = index.dw1.ud;
assert(offset.file == BRW_GENERAL_REGISTER_FILE);
i965/fs: Switch to using sampler LD messages for uniform pull constants. When forcing the compiler to always generate pull constants instead of push constants (in order to have an easy to use testcase), improves performance of my old GLSL demo 23.3553% +/- 1.42968% (n=7). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60866 Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-06 22:47:22 +00:00
/* Reference just the dword we need, to avoid angering validate_reg(). */
offset = brw_vec1_grf(offset.nr, 0);
i965/fs: Set up gen7 UBO loads as sends from GRFs. This gives the instruction scheduler a chance to schedule between the loads, whereas before it was restricted due to the dependencies between the MRFs for setting them up. For one shader in gles3conform, it goes from getting stuck in register allocation for as long as anybody's bothered to leave it running down to 23 seconds, thanks to the LIFO scheduling. Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-05 08:06:30 +00:00
brw_push_insn_state(p);
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 22:29:25 +01:00
brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
i965/fs: Set up gen7 UBO loads as sends from GRFs. This gives the instruction scheduler a chance to schedule between the loads, whereas before it was restricted due to the dependencies between the MRFs for setting them up. For one shader in gles3conform, it goes from getting stuck in register allocation for as long as anybody's bothered to leave it running down to 23 seconds, thanks to the LIFO scheduling. Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-05 08:06:30 +00:00
brw_pop_insn_state(p);
i965/fs: Switch to using sampler LD messages for uniform pull constants. When forcing the compiler to always generate pull constants instead of push constants (in order to have an easy to use testcase), improves performance of my old GLSL demo 23.3553% +/- 1.42968% (n=7). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60866 Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-06 22:47:22 +00:00
/* We use the SIMD4x2 mode because we want to end up with 4 components in
* the destination loaded consecutively from the same offset (which appears
* in the first component, and the rest are ignored).
*/
dst.width = BRW_WIDTH_4;
i965/fs: Set up gen7 UBO loads as sends from GRFs. This gives the instruction scheduler a chance to schedule between the loads, whereas before it was restricted due to the dependencies between the MRFs for setting them up. For one shader in gles3conform, it goes from getting stuck in register allocation for as long as anybody's bothered to leave it running down to 23 seconds, thanks to the LIFO scheduling. Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-05 08:06:30 +00:00
brw_set_dest(p, send, dst);
brw_set_src0(p, send, offset);
i965/fs: Switch to using sampler LD messages for uniform pull constants. When forcing the compiler to always generate pull constants instead of push constants (in order to have an easy to use testcase), improves performance of my old GLSL demo 23.3553% +/- 1.42968% (n=7). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60866 Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-06 22:47:22 +00:00
brw_set_sampler_message(p, send,
i965/fs: Set up gen7 UBO loads as sends from GRFs. This gives the instruction scheduler a chance to schedule between the loads, whereas before it was restricted due to the dependencies between the MRFs for setting them up. For one shader in gles3conform, it goes from getting stuck in register allocation for as long as anybody's bothered to leave it running down to 23 seconds, thanks to the LIFO scheduling. Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-05 08:06:30 +00:00
surf_index,
i965/fs: Switch to using sampler LD messages for uniform pull constants. When forcing the compiler to always generate pull constants instead of push constants (in order to have an easy to use testcase), improves performance of my old GLSL demo 23.3553% +/- 1.42968% (n=7). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60866 Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-06 22:47:22 +00:00
0, /* LD message ignores sampler unit */
GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1, /* rlen */
1, /* mlen */
false, /* no header */
BRW_SAMPLER_SIMD_MODE_SIMD4X2,
0);
i965/fs: Track the binding table size in brw_wm_prog_data. By tracking the maximum surface index used by the shader, we know just how small we can make the binding table. Since it depends entirely on the shader program, we can just compute it once at compile time, rather than at binding table emit time (which happens during drawing). v2: Store binding_table_size, rather than max_surface_index, for consistency with the VS (which needs to be able to represent 0 surfaces). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-08-15 03:49:33 +01:00
i965/fs: Replace c->prog_data with a direct reference in the generators. 'c' is going away. This is also a bit shorter. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-05-14 08:20:24 +01:00
brw_mark_surface_used(&prog_data->base, surf_index);
i965/fs: Set up gen7 UBO loads as sends from GRFs. This gives the instruction scheduler a chance to schedule between the loads, whereas before it was restricted due to the dependencies between the MRFs for setting them up. For one shader in gles3conform, it goes from getting stuck in register allocation for as long as anybody's bothered to leave it running down to 23 seconds, thanks to the LIFO scheduling. Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-05 08:06:30 +00:00
}
i965/fs: Add instruction emit for varying-index reads of uniforms. The gen7 send-from-GRF path is sufficiently different from the perspective of IR generation and optimization that I just made it a separate opcode. v2: fix whitespace, rebase on Ken's recent refactor.
2012-11-07 19:18:34 +00:00
void
fs_generator::generate_varying_pull_constant_load(fs_inst *inst,
struct brw_reg dst,
i965/fs: Use LD messages for pre-gen7 varying-index uniform loads This comes at a minor performance cost at the moment (-3.2% +/- 0.2%, n=14 on my GM45 forced to load all uniforms through the varying-index path), but we get a whole vec4 at a time to reuse in the next commit. v2: Fix comment about channels in the other message. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> NOTE: This is a candidate for the 9.1 branch.
2013-03-18 17:16:42 +00:00
struct brw_reg index,
struct brw_reg offset)
i965/fs: Add instruction emit for varying-index reads of uniforms. The gen7 send-from-GRF path is sufficiently different from the perspective of IR generation and optimization that I just made it a separate opcode. v2: fix whitespace, rebase on Ken's recent refactor.
2012-11-07 19:18:34 +00:00
{
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 08:36:46 +01:00
assert(brw->gen < 7); /* Should use the gen7 variant. */
i965/fs: Add instruction emit for varying-index reads of uniforms. The gen7 send-from-GRF path is sufficiently different from the perspective of IR generation and optimization that I just made it a separate opcode. v2: fix whitespace, rebase on Ken's recent refactor.
2012-11-07 19:18:34 +00:00
assert(inst->header_present);
i965/fs: Use LD messages for pre-gen7 varying-index uniform loads This comes at a minor performance cost at the moment (-3.2% +/- 0.2%, n=14 on my GM45 forced to load all uniforms through the varying-index path), but we get a whole vec4 at a time to reuse in the next commit. v2: Fix comment about channels in the other message. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> NOTE: This is a candidate for the 9.1 branch.
2013-03-18 17:16:42 +00:00
assert(inst->mlen);
i965/fs: Add instruction emit for varying-index reads of uniforms. The gen7 send-from-GRF path is sufficiently different from the perspective of IR generation and optimization that I just made it a separate opcode. v2: fix whitespace, rebase on Ken's recent refactor.
2012-11-07 19:18:34 +00:00
assert(index.file == BRW_IMMEDIATE_VALUE &&
index.type == BRW_REGISTER_TYPE_UD);
uint32_t surf_index = index.dw1.ud;
i965/fs: Use LD messages for pre-gen7 varying-index uniform loads This comes at a minor performance cost at the moment (-3.2% +/- 0.2%, n=14 on my GM45 forced to load all uniforms through the varying-index path), but we get a whole vec4 at a time to reuse in the next commit. v2: Fix comment about channels in the other message. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> NOTE: This is a candidate for the 9.1 branch.
2013-03-18 17:16:42 +00:00
uint32_t simd_mode, rlen, msg_type;
i965/fs: Add instruction emit for varying-index reads of uniforms. The gen7 send-from-GRF path is sufficiently different from the perspective of IR generation and optimization that I just made it a separate opcode. v2: fix whitespace, rebase on Ken's recent refactor.
2012-11-07 19:18:34 +00:00
if (dispatch_width == 16) {
i965/fs: Use LD messages for pre-gen7 varying-index uniform loads This comes at a minor performance cost at the moment (-3.2% +/- 0.2%, n=14 on my GM45 forced to load all uniforms through the varying-index path), but we get a whole vec4 at a time to reuse in the next commit. v2: Fix comment about channels in the other message. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> NOTE: This is a candidate for the 9.1 branch.
2013-03-18 17:16:42 +00:00
simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
rlen = 8;
i965/fs: Add instruction emit for varying-index reads of uniforms. The gen7 send-from-GRF path is sufficiently different from the perspective of IR generation and optimization that I just made it a separate opcode. v2: fix whitespace, rebase on Ken's recent refactor.
2012-11-07 19:18:34 +00:00
} else {
i965/fs: Use LD messages for pre-gen7 varying-index uniform loads This comes at a minor performance cost at the moment (-3.2% +/- 0.2%, n=14 on my GM45 forced to load all uniforms through the varying-index path), but we get a whole vec4 at a time to reuse in the next commit. v2: Fix comment about channels in the other message. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> NOTE: This is a candidate for the 9.1 branch.
2013-03-18 17:16:42 +00:00
simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
rlen = 4;
i965/fs: Add instruction emit for varying-index reads of uniforms. The gen7 send-from-GRF path is sufficiently different from the perspective of IR generation and optimization that I just made it a separate opcode. v2: fix whitespace, rebase on Ken's recent refactor.
2012-11-07 19:18:34 +00:00
}
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 08:36:46 +01:00
if (brw->gen >= 5)
i965/fs: Use LD messages for pre-gen7 varying-index uniform loads This comes at a minor performance cost at the moment (-3.2% +/- 0.2%, n=14 on my GM45 forced to load all uniforms through the varying-index path), but we get a whole vec4 at a time to reuse in the next commit. v2: Fix comment about channels in the other message. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> NOTE: This is a candidate for the 9.1 branch.
2013-03-18 17:16:42 +00:00
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
else {
/* We always use the SIMD16 message so that we only have to load U, and
* not V or R.
*/
msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
assert(inst->mlen == 3);
assert(inst->regs_written == 8);
rlen = 8;
simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
}
struct brw_reg offset_mrf = retype(brw_message_reg(inst->base_mrf + 1),
BRW_REGISTER_TYPE_D);
brw_MOV(p, offset_mrf, offset);
i965/fs: Add instruction emit for varying-index reads of uniforms. The gen7 send-from-GRF path is sufficiently different from the perspective of IR generation and optimization that I just made it a separate opcode. v2: fix whitespace, rebase on Ken's recent refactor.
2012-11-07 19:18:34 +00:00
struct brw_reg header = brw_vec8_grf(0, 0);
gen6_resolve_implied_move(p, &header, inst->base_mrf);
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 22:29:25 +01:00
brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
i965: Convert fs_generator to the new brw_inst API. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-08 06:44:24 +01:00
brw_inst_set_qtr_control(brw, send, BRW_COMPRESSION_NONE);
i965: Retype pre-Gen6 varying pull load destination to UW. This sets up the proper execution mask for sends in SIMD16 mode. Fixes Piglit's glsl-fs-normalmatrix, glsl-fs-uniform-array-2, glsl-fs-uniform-array-6, and glsl-fs-uniform-array-7 on Ironlake, which regressed when I enabled SIMD16 pull parameter support in commit b207e88b25e526d0f1ada7b19605b880a27866dc. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2014-04-17 04:15:23 +01:00
brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
i965/fs: Add instruction emit for varying-index reads of uniforms. The gen7 send-from-GRF path is sufficiently different from the perspective of IR generation and optimization that I just made it a separate opcode. v2: fix whitespace, rebase on Ken's recent refactor.
2012-11-07 19:18:34 +00:00
brw_set_src0(p, send, header);
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 08:36:46 +01:00
if (brw->gen < 6)
i965: Convert fs_generator to the new brw_inst API. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-08 06:44:24 +01:00
brw_inst_set_base_mrf(brw, send, inst->base_mrf);
i965/fs: Use LD messages for pre-gen7 varying-index uniform loads This comes at a minor performance cost at the moment (-3.2% +/- 0.2%, n=14 on my GM45 forced to load all uniforms through the varying-index path), but we get a whole vec4 at a time to reuse in the next commit. v2: Fix comment about channels in the other message. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> NOTE: This is a candidate for the 9.1 branch.
2013-03-18 17:16:42 +00:00
/* Our surface is set up as floats, regardless of what actual data is
* stored in it.
*/
uint32_t return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
brw_set_sampler_message(p, send,
i965/fs: Add instruction emit for varying-index reads of uniforms. The gen7 send-from-GRF path is sufficiently different from the perspective of IR generation and optimization that I just made it a separate opcode. v2: fix whitespace, rebase on Ken's recent refactor.
2012-11-07 19:18:34 +00:00
surf_index,
i965/fs: Use LD messages for pre-gen7 varying-index uniform loads This comes at a minor performance cost at the moment (-3.2% +/- 0.2%, n=14 on my GM45 forced to load all uniforms through the varying-index path), but we get a whole vec4 at a time to reuse in the next commit. v2: Fix comment about channels in the other message. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> NOTE: This is a candidate for the 9.1 branch.
2013-03-18 17:16:42 +00:00
0, /* sampler (unused) */
i965/fs: Add instruction emit for varying-index reads of uniforms. The gen7 send-from-GRF path is sufficiently different from the perspective of IR generation and optimization that I just made it a separate opcode. v2: fix whitespace, rebase on Ken's recent refactor.
2012-11-07 19:18:34 +00:00
msg_type,
i965/fs: Use LD messages for pre-gen7 varying-index uniform loads This comes at a minor performance cost at the moment (-3.2% +/- 0.2%, n=14 on my GM45 forced to load all uniforms through the varying-index path), but we get a whole vec4 at a time to reuse in the next commit. v2: Fix comment about channels in the other message. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> NOTE: This is a candidate for the 9.1 branch.
2013-03-18 17:16:42 +00:00
rlen,
i965/fs: Add instruction emit for varying-index reads of uniforms. The gen7 send-from-GRF path is sufficiently different from the perspective of IR generation and optimization that I just made it a separate opcode. v2: fix whitespace, rebase on Ken's recent refactor.
2012-11-07 19:18:34 +00:00
inst->mlen,
inst->header_present,
i965/fs: Use LD messages for pre-gen7 varying-index uniform loads This comes at a minor performance cost at the moment (-3.2% +/- 0.2%, n=14 on my GM45 forced to load all uniforms through the varying-index path), but we get a whole vec4 at a time to reuse in the next commit. v2: Fix comment about channels in the other message. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> NOTE: This is a candidate for the 9.1 branch.
2013-03-18 17:16:42 +00:00
simd_mode,
return_format);
i965/fs: Track the binding table size in brw_wm_prog_data. By tracking the maximum surface index used by the shader, we know just how small we can make the binding table. Since it depends entirely on the shader program, we can just compute it once at compile time, rather than at binding table emit time (which happens during drawing). v2: Store binding_table_size, rather than max_surface_index, for consistency with the VS (which needs to be able to represent 0 surfaces). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-08-15 03:49:33 +01:00
i965/fs: Replace c->prog_data with a direct reference in the generators. 'c' is going away. This is also a bit shorter. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-05-14 08:20:24 +01:00
brw_mark_surface_used(&prog_data->base, surf_index);
i965/fs: Add instruction emit for varying-index reads of uniforms. The gen7 send-from-GRF path is sufficiently different from the perspective of IR generation and optimization that I just made it a separate opcode. v2: fix whitespace, rebase on Ken's recent refactor.
2012-11-07 19:18:34 +00:00
}
void
fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
struct brw_reg dst,
struct brw_reg index,
struct brw_reg offset)
{
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 08:36:46 +01:00
assert(brw->gen >= 7);
i965/fs: Add instruction emit for varying-index reads of uniforms. The gen7 send-from-GRF path is sufficiently different from the perspective of IR generation and optimization that I just made it a separate opcode. v2: fix whitespace, rebase on Ken's recent refactor.
2012-11-07 19:18:34 +00:00
/* Varying-offset pull constant loads are treated as a normal expression on
* gen7, so the fact that it's a send message is hidden at the IR level.
*/
assert(!inst->header_present);
assert(!inst->mlen);
assert(index.file == BRW_IMMEDIATE_VALUE &&
index.type == BRW_REGISTER_TYPE_UD);
uint32_t surf_index = index.dw1.ud;
i965/fs: Improve performance of varying-index uniform loads on IVB. Like we have done for the VS and for constant-index uniform loads, we use the sampler engine to get caching in front of the L3 to avoid tickling the IVB L3 bug. This is also a bit of a functional change, as we're now loading a vec4 instead of a single dword, though we're not taking advantage of the other 3 components of the vec4 (yet). With the driver hacked to always take the varying-index path for all uniforms, improves performance of my old GLSL demo by 315% +/- 2% (n=4). This a major fix for some blur shaders in compositors from the varying-index uniforms support I introduced in 9.1. v2: Move old offset computation into the pre-gen7 path. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=61554 NOTE: This is a candidate for the 9.1 branch.
2013-03-13 21:48:55 +00:00
uint32_t simd_mode, rlen, mlen;
i965/fs: Add instruction emit for varying-index reads of uniforms. The gen7 send-from-GRF path is sufficiently different from the perspective of IR generation and optimization that I just made it a separate opcode. v2: fix whitespace, rebase on Ken's recent refactor.
2012-11-07 19:18:34 +00:00
if (dispatch_width == 16) {
i965/fs: Improve performance of varying-index uniform loads on IVB. Like we have done for the VS and for constant-index uniform loads, we use the sampler engine to get caching in front of the L3 to avoid tickling the IVB L3 bug. This is also a bit of a functional change, as we're now loading a vec4 instead of a single dword, though we're not taking advantage of the other 3 components of the vec4 (yet). With the driver hacked to always take the varying-index path for all uniforms, improves performance of my old GLSL demo by 315% +/- 2% (n=4). This a major fix for some blur shaders in compositors from the varying-index uniforms support I introduced in 9.1. v2: Move old offset computation into the pre-gen7 path. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=61554 NOTE: This is a candidate for the 9.1 branch.
2013-03-13 21:48:55 +00:00
mlen = 2;
rlen = 8;
simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
i965/fs: Add instruction emit for varying-index reads of uniforms. The gen7 send-from-GRF path is sufficiently different from the perspective of IR generation and optimization that I just made it a separate opcode. v2: fix whitespace, rebase on Ken's recent refactor.
2012-11-07 19:18:34 +00:00
} else {
i965/fs: Improve performance of varying-index uniform loads on IVB. Like we have done for the VS and for constant-index uniform loads, we use the sampler engine to get caching in front of the L3 to avoid tickling the IVB L3 bug. This is also a bit of a functional change, as we're now loading a vec4 instead of a single dword, though we're not taking advantage of the other 3 components of the vec4 (yet). With the driver hacked to always take the varying-index path for all uniforms, improves performance of my old GLSL demo by 315% +/- 2% (n=4). This a major fix for some blur shaders in compositors from the varying-index uniforms support I introduced in 9.1. v2: Move old offset computation into the pre-gen7 path. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=61554 NOTE: This is a candidate for the 9.1 branch.
2013-03-13 21:48:55 +00:00
mlen = 1;
rlen = 4;
simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
i965/fs: Add instruction emit for varying-index reads of uniforms. The gen7 send-from-GRF path is sufficiently different from the perspective of IR generation and optimization that I just made it a separate opcode. v2: fix whitespace, rebase on Ken's recent refactor.
2012-11-07 19:18:34 +00:00
}
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 22:29:25 +01:00
brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
i965/fs: Add instruction emit for varying-index reads of uniforms. The gen7 send-from-GRF path is sufficiently different from the perspective of IR generation and optimization that I just made it a separate opcode. v2: fix whitespace, rebase on Ken's recent refactor.
2012-11-07 19:18:34 +00:00
brw_set_dest(p, send, dst);
brw_set_src0(p, send, offset);
i965/fs: Improve performance of varying-index uniform loads on IVB. Like we have done for the VS and for constant-index uniform loads, we use the sampler engine to get caching in front of the L3 to avoid tickling the IVB L3 bug. This is also a bit of a functional change, as we're now loading a vec4 instead of a single dword, though we're not taking advantage of the other 3 components of the vec4 (yet). With the driver hacked to always take the varying-index path for all uniforms, improves performance of my old GLSL demo by 315% +/- 2% (n=4). This a major fix for some blur shaders in compositors from the varying-index uniforms support I introduced in 9.1. v2: Move old offset computation into the pre-gen7 path. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=61554 NOTE: This is a candidate for the 9.1 branch.
2013-03-13 21:48:55 +00:00
brw_set_sampler_message(p, send,
i965/fs: Add instruction emit for varying-index reads of uniforms. The gen7 send-from-GRF path is sufficiently different from the perspective of IR generation and optimization that I just made it a separate opcode. v2: fix whitespace, rebase on Ken's recent refactor.
2012-11-07 19:18:34 +00:00
surf_index,
i965/fs: Improve performance of varying-index uniform loads on IVB. Like we have done for the VS and for constant-index uniform loads, we use the sampler engine to get caching in front of the L3 to avoid tickling the IVB L3 bug. This is also a bit of a functional change, as we're now loading a vec4 instead of a single dword, though we're not taking advantage of the other 3 components of the vec4 (yet). With the driver hacked to always take the varying-index path for all uniforms, improves performance of my old GLSL demo by 315% +/- 2% (n=4). This a major fix for some blur shaders in compositors from the varying-index uniforms support I introduced in 9.1. v2: Move old offset computation into the pre-gen7 path. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=61554 NOTE: This is a candidate for the 9.1 branch.
2013-03-13 21:48:55 +00:00
0, /* LD message ignores sampler unit */
GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
rlen,
i965/fs: Add instruction emit for varying-index reads of uniforms. The gen7 send-from-GRF path is sufficiently different from the perspective of IR generation and optimization that I just made it a separate opcode. v2: fix whitespace, rebase on Ken's recent refactor.
2012-11-07 19:18:34 +00:00
mlen,
i965/fs: Improve performance of varying-index uniform loads on IVB. Like we have done for the VS and for constant-index uniform loads, we use the sampler engine to get caching in front of the L3 to avoid tickling the IVB L3 bug. This is also a bit of a functional change, as we're now loading a vec4 instead of a single dword, though we're not taking advantage of the other 3 components of the vec4 (yet). With the driver hacked to always take the varying-index path for all uniforms, improves performance of my old GLSL demo by 315% +/- 2% (n=4). This a major fix for some blur shaders in compositors from the varying-index uniforms support I introduced in 9.1. v2: Move old offset computation into the pre-gen7 path. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=61554 NOTE: This is a candidate for the 9.1 branch.
2013-03-13 21:48:55 +00:00
false, /* no header */
simd_mode,
0);
i965/fs: Track the binding table size in brw_wm_prog_data. By tracking the maximum surface index used by the shader, we know just how small we can make the binding table. Since it depends entirely on the shader program, we can just compute it once at compile time, rather than at binding table emit time (which happens during drawing). v2: Store binding_table_size, rather than max_surface_index, for consistency with the VS (which needs to be able to represent 0 surfaces). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-08-15 03:49:33 +01:00
i965/fs: Replace c->prog_data with a direct reference in the generators. 'c' is going away. This is also a bit shorter. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-05-14 08:20:24 +01:00
brw_mark_surface_used(&prog_data->base, surf_index);
i965/fs: Add instruction emit for varying-index reads of uniforms. The gen7 send-from-GRF path is sufficiently different from the perspective of IR generation and optimization that I just made it a separate opcode. v2: fix whitespace, rebase on Ken's recent refactor.
2012-11-07 19:18:34 +00:00
}
i965/fs: Add FS_OPCODE_MOV_DISPATCH_TO_FLAGS to fragment shader backend. In order to compute centroid varyings correctly, the fragment shader needs to be able to load the current pixel/sample mask into a flag register. This patch adds an opcode to the fragment shader back-end to do this; the opcode gets translated into the instruction mov(1) f0<1>UW g1.14<0,1,0>UW { align1 WE_all } Since this instruction clobbers f0, instruction scheduling has to treat it the same as instructions that have a conditional modifier. Reviewed-by: Eric Anholt <eric@anholt.net>
2012-06-18 22:50:04 +01:00
/**
* Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
* into the flags register (f0.0).
*
* Used only on Gen6 and above.
*/
void
i965/fs: Add an instruction flag for choosing the flag subregister. We're going to redo discard handling to track discards in the other flag subregister, saving instructions in the discard and allowing predicated jumps out to the end of the shader. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-06 18:36:11 +00:00
fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
i965/fs: Add FS_OPCODE_MOV_DISPATCH_TO_FLAGS to fragment shader backend. In order to compute centroid varyings correctly, the fragment shader needs to be able to load the current pixel/sample mask into a flag register. This patch adds an opcode to the fragment shader back-end to do this; the opcode gets translated into the instruction mov(1) f0<1>UW g1.14<0,1,0>UW { align1 WE_all } Since this instruction clobbers f0, instruction scheduling has to treat it the same as instructions that have a conditional modifier. Reviewed-by: Eric Anholt <eric@anholt.net>
2012-06-18 22:50:04 +01:00
{
i965/fs: Add an instruction flag for choosing the flag subregister. We're going to redo discard handling to track discards in the other flag subregister, saving instructions in the discard and allowing predicated jumps out to the end of the shader. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-06 18:36:11 +00:00
struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg);
i965/fs: Rewrite discards to use a flag subreg to track discarded pixels. This makes much more sense on gen6+, and will also prove useful for early exit of shaders on discard. v2: fix up a stale comment from before converting gen4-5. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-06 20:15:13 +00:00
struct brw_reg dispatch_mask;
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 08:36:46 +01:00
if (brw->gen >= 6)
i965/fs: Rewrite discards to use a flag subreg to track discarded pixels. This makes much more sense on gen6+, and will also prove useful for early exit of shaders on discard. v2: fix up a stale comment from before converting gen4-5. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-06 20:15:13 +00:00
dispatch_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
else
dispatch_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
i965/fs: Add FS_OPCODE_MOV_DISPATCH_TO_FLAGS to fragment shader backend. In order to compute centroid varyings correctly, the fragment shader needs to be able to load the current pixel/sample mask into a flag register. This patch adds an opcode to the fragment shader back-end to do this; the opcode gets translated into the instruction mov(1) f0<1>UW g1.14<0,1,0>UW { align1 WE_all } Since this instruction clobbers f0, instruction scheduling has to treat it the same as instructions that have a conditional modifier. Reviewed-by: Eric Anholt <eric@anholt.net>
2012-06-18 22:50:04 +01:00
brw_push_insn_state(p);
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
i965/fs: Rewrite discards to use a flag subreg to track discarded pixels. This makes much more sense on gen6+, and will also prove useful for early exit of shaders on discard. v2: fix up a stale comment from before converting gen4-5. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-06 20:15:13 +00:00
brw_MOV(p, flags, dispatch_mask);
i965/fs: Add FS_OPCODE_MOV_DISPATCH_TO_FLAGS to fragment shader backend. In order to compute centroid varyings correctly, the fragment shader needs to be able to load the current pixel/sample mask into a flag register. This patch adds an opcode to the fragment shader back-end to do this; the opcode gets translated into the instruction mov(1) f0<1>UW g1.14<0,1,0>UW { align1 WE_all } Since this instruction clobbers f0, instruction scheduling has to treat it the same as instructions that have a conditional modifier. Reviewed-by: Eric Anholt <eric@anholt.net>
2012-06-18 22:50:04 +01:00
brw_pop_insn_state(p);
}
i965/fs: Make register file enum 0 be the undefined register file. In 6d874d0ee18b3694c49e0206fa519bd8b746ec24, I checked whether a register that had been stored was BAD_FILE (as opposed to a legitimate GRF), but actually the unset register was ARF NULL because it had been memset to 0. Finding BAD_FILE for unset values in debugging was my intention with that file, so make it the case more often by rearranging the enum. There was only one place we relied on the magic enum register_file to hardware register file correspondance anyway.
2011-11-23 18:13:39 +00:00
static uint32_t brw_file_from_reg(fs_reg *reg)
{
switch (reg->file) {
case GRF:
return BRW_GENERAL_REGISTER_FILE;
case MRF:
return BRW_MESSAGE_REGISTER_FILE;
case IMM:
return BRW_IMMEDIATE_VALUE;
default:
assert(!"not reached");
return BRW_GENERAL_REGISTER_FILE;
}
}
i965: Expose brw_reg_from_fs_reg() to other files. This will be useful for Broadwell code as well. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-01 20:29:37 +00:00
struct brw_reg
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
brw_reg_from_fs_reg(fs_reg *reg)
{
struct brw_reg brw_reg;
switch (reg->file) {
case GRF:
case MRF:
i965/fs: Remove fs_reg::smear. The same effect can be achieved using a combination of ::stride and ::subreg_offset. Remove the less flexible ::smear to keep the data members of fs_reg orthogonal. Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2014-01-15 21:21:30 +00:00
if (reg->stride == 0) {
brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->reg, 0);
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
} else {
i965/fs: Add support for specifying register horizontal strides. v2: Some improvements for copy propagation with non-contiguous register strides and mismatching types. v3: Add example of the situation that the copy propagation changes are intended to avoid. Clarify that 'fs_reg::apply_stride()' is expected to work with zero strides too. Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-12-08 03:57:35 +00:00
brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0);
brw_reg = stride(brw_reg, 8 * reg->stride, 8, reg->stride);
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
}
i965/fs: Add support for specifying register horizontal strides. v2: Some improvements for copy propagation with non-contiguous register strides and mismatching types. v3: Add example of the situation that the copy propagation changes are intended to avoid. Clarify that 'fs_reg::apply_stride()' is expected to work with zero strides too. Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-12-08 03:57:35 +00:00
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
brw_reg = retype(brw_reg, reg->type);
i965/fs: Add support for sub-register byte offsets to the FS back-end IR. It would be nice if we could have a single 'reg_offset' field expressed in bytes that would serve the purpose of both, but the semantics of 'reg_offset' are quite complex currently (it's measured in units of one, eight or sixteen dwords depending on the register file and the dispatch width) and changing it to bytes would be a very intrusive change at this stage. Add a separate 'subreg_offset' field for now. Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-12-08 03:57:08 +00:00
brw_reg = byte_offset(brw_reg, reg->subreg_offset);
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
break;
case IMM:
switch (reg->type) {
case BRW_REGISTER_TYPE_F:
brw_reg = brw_imm_f(reg->imm.f);
break;
case BRW_REGISTER_TYPE_D:
brw_reg = brw_imm_d(reg->imm.i);
break;
case BRW_REGISTER_TYPE_UD:
brw_reg = brw_imm_ud(reg->imm.u);
break;
default:
assert(!"not reached");
brw_reg = brw_null_reg();
break;
}
break;
i965: Share the register file enum between the two backends. I need this so I can look at vec4 and fs registers' files from the same .cpp file without namespaces. As far as I can tell we never rely on the particular numerical values of the files, though I thought it sounded like a good idea when doing the VS (it turns out having 0 be BAD_FILE is nicer). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2013-04-30 00:05:05 +01:00
case HW_REG:
i965: Make sure that backend_reg::type and brw_reg::type are consistent for fixed regs. And define non-mutating helper functions to retype fixed and normal regs with a common interface. At some point we may want to get rid of ::fixed_hw_reg completely and have fixed regs use the normal register data members (e.g. backend_reg::reg to select a fixed GRF number, src_reg::swizzle to store the swizzle, etc.), I have the feeling that this is not the last headache we're going to get because of the multiple ways to represent the same thing and the different register interface depending on the file a register is stored in... Reviewed-by: Paul Berry <stereotype441@gmail.com>
2014-02-19 14:21:07 +00:00
assert(reg->type == reg->fixed_hw_reg.type);
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
brw_reg = reg->fixed_hw_reg;
break;
case BAD_FILE:
/* Probably unused. */
brw_reg = brw_null_reg();
break;
case UNIFORM:
assert(!"not reached");
brw_reg = brw_null_reg();
break;
default:
assert(!"not reached");
brw_reg = brw_null_reg();
break;
}
if (reg->abs)
brw_reg = brw_abs(brw_reg);
if (reg->negate)
brw_reg = negate(brw_reg);
return brw_reg;
}
i965/fs: Set up gen7 UBO loads as sends from GRFs. This gives the instruction scheduler a chance to schedule between the loads, whereas before it was restricted due to the dependencies between the MRFs for setting them up. For one shader in gles3conform, it goes from getting stuck in register allocation for as long as anybody's bothered to leave it running down to 23 seconds, thanks to the LIFO scheduling. Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-05 08:06:30 +00:00
/**
i965/fs: Switch to using sampler LD messages for uniform pull constants. When forcing the compiler to always generate pull constants instead of push constants (in order to have an easy to use testcase), improves performance of my old GLSL demo 23.3553% +/- 1.42968% (n=7). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60866 Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-06 22:47:22 +00:00
* Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
* sampler LD messages.
i965/fs: Set up gen7 UBO loads as sends from GRFs. This gives the instruction scheduler a chance to schedule between the loads, whereas before it was restricted due to the dependencies between the MRFs for setting them up. For one shader in gles3conform, it goes from getting stuck in register allocation for as long as anybody's bothered to leave it running down to 23 seconds, thanks to the LIFO scheduling. Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-05 08:06:30 +00:00
*
i965/fs: Switch to using sampler LD messages for uniform pull constants. When forcing the compiler to always generate pull constants instead of push constants (in order to have an easy to use testcase), improves performance of my old GLSL demo 23.3553% +/- 1.42968% (n=7). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60866 Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-06 22:47:22 +00:00
* We don't want to bake it into the send message's code generation because
* that means we don't get a chance to schedule the instructions.
i965/fs: Set up gen7 UBO loads as sends from GRFs. This gives the instruction scheduler a chance to schedule between the loads, whereas before it was restricted due to the dependencies between the MRFs for setting them up. For one shader in gles3conform, it goes from getting stuck in register allocation for as long as anybody's bothered to leave it running down to 23 seconds, thanks to the LIFO scheduling. Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-05 08:06:30 +00:00
*/
void
i965/fs: Switch to using sampler LD messages for uniform pull constants. When forcing the compiler to always generate pull constants instead of push constants (in order to have an easy to use testcase), improves performance of my old GLSL demo 23.3553% +/- 1.42968% (n=7). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60866 Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-06 22:47:22 +00:00
fs_generator::generate_set_simd4x2_offset(fs_inst *inst,
struct brw_reg dst,
struct brw_reg value)
i965/fs: Set up gen7 UBO loads as sends from GRFs. This gives the instruction scheduler a chance to schedule between the loads, whereas before it was restricted due to the dependencies between the MRFs for setting them up. For one shader in gles3conform, it goes from getting stuck in register allocation for as long as anybody's bothered to leave it running down to 23 seconds, thanks to the LIFO scheduling. Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-05 08:06:30 +00:00
{
assert(value.file == BRW_IMMEDIATE_VALUE);
brw_push_insn_state(p);
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
i965/fs: Switch to using sampler LD messages for uniform pull constants. When forcing the compiler to always generate pull constants instead of push constants (in order to have an easy to use testcase), improves performance of my old GLSL demo 23.3553% +/- 1.42968% (n=7). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60866 Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-06 22:47:22 +00:00
brw_MOV(p, retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value);
i965/fs: Set up gen7 UBO loads as sends from GRFs. This gives the instruction scheduler a chance to schedule between the loads, whereas before it was restricted due to the dependencies between the MRFs for setting them up. For one shader in gles3conform, it goes from getting stuck in register allocation for as long as anybody's bothered to leave it running down to 23 seconds, thanks to the LIFO scheduling. Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-05 08:06:30 +00:00
brw_pop_insn_state(p);
}
i965: Add FS backend for builtin gl_SampleMask[] V2: - Update comments - Add a special backend instructions to compute sample_mask. - Add a new variable uses_omask in brw_wm_prog_data. V3: - Make changes to support simd16 mode. - Delete redundant AND instruction and handle the register stride in FS backend instruction. Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-10-25 00:21:13 +01:00
/* Sets vstride=16, width=8, hstride=2 or vstride=0, width=1, hstride=0
* (when mask is passed as a uniform) of register mask before moving it
* to register dst.
*/
void
fs_generator::generate_set_omask(fs_inst *inst,
struct brw_reg dst,
struct brw_reg mask)
{
bool stride_8_8_1 =
(mask.vstride == BRW_VERTICAL_STRIDE_8 &&
mask.width == BRW_WIDTH_8 &&
mask.hstride == BRW_HORIZONTAL_STRIDE_1);
bool stride_0_1_0 =
(mask.vstride == BRW_VERTICAL_STRIDE_0 &&
mask.width == BRW_WIDTH_1 &&
mask.hstride == BRW_HORIZONTAL_STRIDE_0);
assert(stride_8_8_1 || stride_0_1_0);
assert(dst.type == BRW_REGISTER_TYPE_UW);
if (dispatch_width == 16)
dst = vec16(dst);
brw_push_insn_state(p);
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
i965: Add FS backend for builtin gl_SampleMask[] V2: - Update comments - Add a special backend instructions to compute sample_mask. - Add a new variable uses_omask in brw_wm_prog_data. V3: - Make changes to support simd16 mode. - Delete redundant AND instruction and handle the register stride in FS backend instruction. Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-10-25 00:21:13 +01:00
if (stride_8_8_1) {
i965/fs: Simplify FS_OPCODE_SET_OMASK stride mashing a bit. In the first case, we can simply call stride(mask, 16, 8, 2) rather than creating a new register with a different stride, then immediately changing it a second time. In the second case, the stride was already what we wanted, so we can just use mask without any changes at all. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-02-10 23:37:09 +00:00
brw_MOV(p, dst, retype(stride(mask, 16, 8, 2), dst.type));
i965: Add FS backend for builtin gl_SampleMask[] V2: - Update comments - Add a special backend instructions to compute sample_mask. - Add a new variable uses_omask in brw_wm_prog_data. V3: - Make changes to support simd16 mode. - Delete redundant AND instruction and handle the register stride in FS backend instruction. Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-10-25 00:21:13 +01:00
} else if (stride_0_1_0) {
i965/fs: Simplify FS_OPCODE_SET_OMASK stride mashing a bit. In the first case, we can simply call stride(mask, 16, 8, 2) rather than creating a new register with a different stride, then immediately changing it a second time. In the second case, the stride was already what we wanted, so we can just use mask without any changes at all. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-02-10 23:37:09 +00:00
brw_MOV(p, dst, retype(mask, dst.type));
i965: Add FS backend for builtin gl_SampleMask[] V2: - Update comments - Add a special backend instructions to compute sample_mask. - Add a new variable uses_omask in brw_wm_prog_data. V3: - Make changes to support simd16 mode. - Delete redundant AND instruction and handle the register stride in FS backend instruction. Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-10-25 00:21:13 +01:00
}
brw_pop_insn_state(p);
}
i965: Add FS backend for builtin gl_SampleID V2: - Update comments - Add compute_sample_id variables in brw_wm_prog_key - Add a special backend instruction to compute sample_id. V3: - Make changes to support simd16 mode. Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-10-25 00:17:08 +01:00
/* Sets vstride=1, width=4, hstride=0 of register src1 during
* the ADD instruction.
*/
void
fs_generator::generate_set_sample_id(fs_inst *inst,
struct brw_reg dst,
struct brw_reg src0,
struct brw_reg src1)
{
assert(dst.type == BRW_REGISTER_TYPE_D ||
dst.type == BRW_REGISTER_TYPE_UD);
assert(src0.type == BRW_REGISTER_TYPE_D ||
src0.type == BRW_REGISTER_TYPE_UD);
brw_push_insn_state(p);
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
i965/fs: Simplify FS_OPCODE_SET_SAMPLE_ID stride mashing a bit. stride(brw_vec1_reg(...) ...) takes some register, changes the strides, then changes the strides again. Let's do it once. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-02-10 22:46:49 +00:00
struct brw_reg reg = retype(stride(src1, 1, 4, 0), BRW_REGISTER_TYPE_UW);
i965: Add FS backend for builtin gl_SampleID V2: - Update comments - Add compute_sample_id variables in brw_wm_prog_key - Add a special backend instruction to compute sample_id. V3: - Make changes to support simd16 mode. Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-10-25 00:17:08 +01:00
brw_ADD(p, dst, src0, reg);
if (dispatch_width == 16)
brw_ADD(p, offset(dst, 1), offset(src0, 1), suboffset(reg, 2));
brw_pop_insn_state(p);
}
i965/fs/gen7: Emit code for GLSL 3.00 pack/unpack operations (v4) v2: Remove lewd comment. [for idr] v3: - Optimize away tmp register for packHalf2x16. [for anholt, paul] - Improve comments. [for anholt, paul] - Reduce near-duplicate code by removing vec4_visitor emit_pack/unpack methods. [for chadv] v4: Factor our UD/W register conversion into helper function. [for anholt] Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v2) Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
2013-01-09 19:46:42 +00:00
/**
* Change the register's data type from UD to W, doubling the strides in order
* to compensate for halving the data type width.
*/
static struct brw_reg
ud_reg_to_w(struct brw_reg r)
{
assert(r.type == BRW_REGISTER_TYPE_UD);
r.type = BRW_REGISTER_TYPE_W;
/* The BRW_*_STRIDE enums are defined so that incrementing the field
* doubles the real stride.
*/
if (r.hstride != 0)
++r.hstride;
if (r.vstride != 0)
++r.vstride;
return r;
}
void
fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
struct brw_reg dst,
struct brw_reg x,
struct brw_reg y)
{
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 08:36:46 +01:00
assert(brw->gen >= 7);
i965/fs/gen7: Emit code for GLSL 3.00 pack/unpack operations (v4) v2: Remove lewd comment. [for idr] v3: - Optimize away tmp register for packHalf2x16. [for anholt, paul] - Improve comments. [for anholt, paul] - Reduce near-duplicate code by removing vec4_visitor emit_pack/unpack methods. [for chadv] v4: Factor our UD/W register conversion into helper function. [for anholt] Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v2) Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
2013-01-09 19:46:42 +00:00
assert(dst.type == BRW_REGISTER_TYPE_UD);
i965: Fix assignment instead of comparison in asserts. Fixes side effect in assertion defects reported by Coverity. Note: This is a candidate for the 9.1 branch. Signed-off-by: Vinson Lee <vlee@freedesktop.org> Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
2013-01-26 07:27:50 +00:00
assert(x.type == BRW_REGISTER_TYPE_F);
assert(y.type == BRW_REGISTER_TYPE_F);
i965/fs/gen7: Emit code for GLSL 3.00 pack/unpack operations (v4) v2: Remove lewd comment. [for idr] v3: - Optimize away tmp register for packHalf2x16. [for anholt, paul] - Improve comments. [for anholt, paul] - Reduce near-duplicate code by removing vec4_visitor emit_pack/unpack methods. [for chadv] v4: Factor our UD/W register conversion into helper function. [for anholt] Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v2) Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
2013-01-09 19:46:42 +00:00
/* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
*
* Because this instruction does not have a 16-bit floating-point type,
* the destination data type must be Word (W).
*
* The destination must be DWord-aligned and specify a horizontal stride
* (HorzStride) of 2. The 16-bit result is stored in the lower word of
* each destination channel and the upper word is not modified.
*/
struct brw_reg dst_w = ud_reg_to_w(dst);
/* Give each 32-bit channel of dst the form below , where "." means
* unchanged.
* 0x....hhhh
*/
brw_F32TO16(p, dst_w, y);
/* Now the form:
* 0xhhhh0000
*/
brw_SHL(p, dst, dst, brw_imm_ud(16u));
/* And, finally the form of packHalf2x16's output:
* 0xhhhhllll
*/
brw_F32TO16(p, dst_w, x);
}
void
fs_generator::generate_unpack_half_2x16_split(fs_inst *inst,
struct brw_reg dst,
struct brw_reg src)
{
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 08:36:46 +01:00
assert(brw->gen >= 7);
i965/fs/gen7: Emit code for GLSL 3.00 pack/unpack operations (v4) v2: Remove lewd comment. [for idr] v3: - Optimize away tmp register for packHalf2x16. [for anholt, paul] - Improve comments. [for anholt, paul] - Reduce near-duplicate code by removing vec4_visitor emit_pack/unpack methods. [for chadv] v4: Factor our UD/W register conversion into helper function. [for anholt] Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v2) Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
2013-01-09 19:46:42 +00:00
assert(dst.type == BRW_REGISTER_TYPE_F);
assert(src.type == BRW_REGISTER_TYPE_UD);
/* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
*
* Because this instruction does not have a 16-bit floating-point type,
* the source data type must be Word (W). The destination type must be
* F (Float).
*/
struct brw_reg src_w = ud_reg_to_w(src);
/* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
* For the Y case, we wish to access only the upper word; therefore
* a 16-bit subregister offset is needed.
*/
assert(inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X ||
inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y);
if (inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y)
i965/fs/gen7: Fix fatal typo in unpackHalf2x16 s/src/src_w/ That little typo, which sneaked into v4 of the previous patch, generates incorrect fs code. Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
2013-01-25 05:48:40 +00:00
src_w.subnr += 2;
i965/fs/gen7: Emit code for GLSL 3.00 pack/unpack operations (v4) v2: Remove lewd comment. [for idr] v3: - Optimize away tmp register for packHalf2x16. [for anholt, paul] - Improve comments. [for anholt, paul] - Reduce near-duplicate code by removing vec4_visitor emit_pack/unpack methods. [for chadv] v4: Factor our UD/W register conversion into helper function. [for anholt] Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v2) Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
2013-01-09 19:46:42 +00:00
brw_F16TO32(p, dst, src_w);
}
i965/fs: Switch shader_time writes to using GRFs. This avoids conflicts between shader_time and FB writes, so we can include more of the program under our profiling. This does mean hiding more of the message setup from the optimizer, which doesn't have a way to handle multi-reg sends from GRFs. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-19 22:28:11 +00:00
void
fs_generator::generate_shader_time_add(fs_inst *inst,
struct brw_reg payload,
struct brw_reg offset,
struct brw_reg value)
{
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 08:36:46 +01:00
assert(brw->gen >= 7);
i965/fs: Switch shader_time writes to using GRFs. This avoids conflicts between shader_time and FB writes, so we can include more of the program under our profiling. This does mean hiding more of the message setup from the optimizer, which doesn't have a way to handle multi-reg sends from GRFs. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-19 22:28:11 +00:00
brw_push_insn_state(p);
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_mask_control(p, true);
i965/fs: Switch shader_time writes to using GRFs. This avoids conflicts between shader_time and FB writes, so we can include more of the program under our profiling. This does mean hiding more of the message setup from the optimizer, which doesn't have a way to handle multi-reg sends from GRFs. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-19 22:28:11 +00:00
assert(payload.file == BRW_GENERAL_REGISTER_FILE);
struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0),
offset.type);
struct brw_reg payload_value = retype(brw_vec1_grf(payload.nr + 1, 0),
value.type);
assert(offset.file == BRW_IMMEDIATE_VALUE);
if (value.file == BRW_GENERAL_REGISTER_FILE) {
value.width = BRW_WIDTH_1;
value.hstride = BRW_HORIZONTAL_STRIDE_0;
value.vstride = BRW_VERTICAL_STRIDE_0;
} else {
assert(value.file == BRW_IMMEDIATE_VALUE);
}
/* Trying to deal with setup of the params from the IR is crazy in the FS8
* case, and we don't really care about squeezing every bit of performance
* out of this path, so we just emit the MOVs from here.
*/
brw_MOV(p, payload_offset, offset);
brw_MOV(p, payload_value, value);
i965: Make a brw_stage_prog_data for storing the SURF_INDEX information. It would be nice to be able to pack our binding table so that programs that use 1 render target don't upload an extra BRW_MAX_DRAW_BUFFERS - 1 binding table entries. To do that, we need the compiled program to have information on where its surfaces go. v2: Rename size to size_bytes to be more explicit. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-10-02 22:07:40 +01:00
brw_shader_time_add(p, payload,
i965/fs: Replace c->prog_data with a direct reference in the generators. 'c' is going away. This is also a bit shorter. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-05-14 08:20:24 +01:00
prog_data->base.binding_table.shader_time_start);
i965/fs: Switch shader_time writes to using GRFs. This avoids conflicts between shader_time and FB writes, so we can include more of the program under our profiling. This does mean hiding more of the message setup from the optimizer, which doesn't have a way to handle multi-reg sends from GRFs. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-19 22:28:11 +00:00
brw_pop_insn_state(p);
i965/fs: Track the binding table size in brw_wm_prog_data. By tracking the maximum surface index used by the shader, we know just how small we can make the binding table. Since it depends entirely on the shader program, we can just compute it once at compile time, rather than at binding table emit time (which happens during drawing). v2: Store binding_table_size, rather than max_surface_index, for consistency with the VS (which needs to be able to represent 0 surfaces). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-08-15 03:49:33 +01:00
i965/fs: Replace c->prog_data with a direct reference in the generators. 'c' is going away. This is also a bit shorter. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-05-14 08:20:24 +01:00
brw_mark_surface_used(&prog_data->base,
prog_data->base.binding_table.shader_time_start);
i965/fs: Switch shader_time writes to using GRFs. This avoids conflicts between shader_time and FB writes, so we can include more of the program under our profiling. This does mean hiding more of the message setup from the optimizer, which doesn't have a way to handle multi-reg sends from GRFs. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-19 22:28:11 +00:00
}
i965/gen7: Implement code generation for untyped atomic instructions. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-09-11 22:01:50 +01:00
void
fs_generator::generate_untyped_atomic(fs_inst *inst, struct brw_reg dst,
struct brw_reg atomic_op,
struct brw_reg surf_index)
{
assert(atomic_op.file == BRW_IMMEDIATE_VALUE &&
atomic_op.type == BRW_REGISTER_TYPE_UD &&
surf_index.file == BRW_IMMEDIATE_VALUE &&
surf_index.type == BRW_REGISTER_TYPE_UD);
brw_untyped_atomic(p, dst, brw_message_reg(inst->base_mrf),
atomic_op.dw1.ud, surf_index.dw1.ud,
inst->mlen, dispatch_width / 8);
i965/fs: Replace c->prog_data with a direct reference in the generators. 'c' is going away. This is also a bit shorter. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-05-14 08:20:24 +01:00
brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
i965/gen7: Implement code generation for untyped atomic instructions. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-09-11 22:01:50 +01:00
}
i965/gen7: Implement code generation for untyped surface read instructions.
2013-09-11 22:03:13 +01:00
void
fs_generator::generate_untyped_surface_read(fs_inst *inst, struct brw_reg dst,
struct brw_reg surf_index)
{
assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
surf_index.type == BRW_REGISTER_TYPE_UD);
brw_untyped_surface_read(p, dst, brw_message_reg(inst->base_mrf),
surf_index.dw1.ud,
inst->mlen, dispatch_width / 8);
i965/fs: Replace c->prog_data with a direct reference in the generators. 'c' is going away. This is also a bit shorter. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-05-14 08:20:24 +01:00
brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
i965/gen7: Implement code generation for untyped surface read instructions.
2013-09-11 22:03:13 +01:00
}
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
void
i965: Move annotation info into generate code. Suggested by Ken as a way to cut down lines of code. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-25 18:42:32 +01:00
fs_generator::generate_code(exec_list *instructions)
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
{
i965: Move annotation info into generate code. Suggested by Ken as a way to cut down lines of code. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-25 18:42:32 +01:00
int start_offset = p->next_insn_offset;
struct annotation_info annotation;
memset(&annotation, 0, sizeof(annotation));
i965: Rename fs_cfg types to not mention fs. fs_bblock_link -> bblock_link fs_bblock -> bblock_t (to avoid conflicting with all the fs_bblock *bblock) fs_cfg -> cfg_t (to avoid conflicting with all the fs_cfg *cfg) Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-10-03 21:16:09 +01:00
cfg_t *cfg = NULL;
i965/fs: Don't hardcode DEBUG_WM in generic fs code. Similar to Paul's commit e9fa3a944 except brw_fs_generator's debug_flag is for DEBUG_WM and DEBUG_BLORP. Reviewed-by: Eric Anholt <eric@anholt.net>
2014-05-14 23:05:09 +01:00
if (unlikely(debug_flag))
i965/cfg: Clean up cfg_t constructors. parent_mem_ctx was unused since db47074a, so remove the two wrappers around create() and make create() the constructor. Reviewed-by: Eric Anholt <eric@anholt.net>
2013-11-29 07:24:44 +00:00
cfg = new(mem_ctx) cfg_t(instructions);
i965: Add basic block generator. This takes the fs_inst list generated by the visitor, and generates a list of basic blocks with edges between them. This is a building block for data-flow analysis.
2012-04-10 20:01:50 +01:00
i965/fs: Split final assembly code generation out of fs_visitor. Compiling shaders requires several main steps: 1. Generating FS IR from either GLSL IR or Mesa IR 2. Optimizing the IR 3. Register allocation 4. Generating assembly code This patch splits out step 4 into a separate class named "fs_generator." There are several reasons for doing so: 1. Future hardware has a different instruction encoding. Splitting this out will allow us to replace fs_generator (which relies heavily on the brw_eu_emit.c code and struct brw_instruction) with a new code generator that writes the new format. 2. It reduces the size of the fs_visitor monolith. (Arguably, a lot more should be split out, but that's left for "future work.") 3. Separate namespaces allow us to make helper functions for generating instructions in both classes: ADD() can exist in fs_visitor and create IR, while ADD() in fs_generator() can create brw_instructions. (Patches for this upcoming.) Furthermore, this patch changes the order of operations slightly. Rather than doing steps 1-4 for SIMD8, then 1-4 for SIMD16, we now: - Do steps 1-3 for SIMD8, then repeat 1-3 for SIMD16 - Generate final assembly code for both modes together This is because the frontend work can be done independently, but final assembly generation needs to pack both into a single program store to feed the GPU. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-11-09 09:05:47 +00:00
foreach_list(node, instructions) {
i965/fs: Stop using the exec_list iterator. The old style has gone out of favor in the project, but I kept copy and pasting from existing iterator code.
2011-07-29 19:52:39 +01:00
fs_inst *inst = (fs_inst *)node;
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
struct brw_reg src[3], dst;
i965: Don't use brw_set_conditionalmod in the FS and vec4 compilers. brw_set_conditionalmod and brw_next_insn work together to set the conditional modifier for the next instruction, then turn it off. The Gen8+ generators don't implement this: we just set it for all future instructions, and whack it for each fs_inst/vec4_instruction. Both approaches work out because we only set conditional_mod on IR instructions like CMP, AND, and so on, which correspond to exactly one assembly instruction. The Gen8 generators would break if we had an IR instruction that generated multiple instructions, and the Gen4-7 EU emit layer would do...something. To safeguard against this, assert that we only generated one instruction if conditional_mod is set, and just set the flag directly on that instruction rather than altering default state. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-05-31 00:41:32 +01:00
unsigned int last_insn_offset = p->next_insn_offset;
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
i965: Print disassembly after compaction. Reviewed-by: Eric Anholt <eric@anholt.net>
2014-05-19 18:20:37 +01:00
if (unlikely(debug_flag))
i965: Move annotation info into generate code. Suggested by Ken as a way to cut down lines of code. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-25 18:42:32 +01:00
annotate(brw, &annotation, cfg, inst, p->next_insn_offset);
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
i965/fs: Loop from 0 to inst->sources, not 0 to 3. Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-03-17 17:39:43 +00:00
for (unsigned int i = 0; i < inst->sources; i++) {
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
src[i] = brw_reg_from_fs_reg(&inst->src[i]);
i965/fs: Fix comparisions with uint negation. The condmod instruction ends up generating garbage condition codes, because apparently the comparison happens on the accumulator value (33 bits for UD), not the truncated value that would be written. Fixes fs-op-neg-* Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2011-10-03 23:12:10 +01:00
/* The accumulator result appears to get used for the
* conditional modifier generation. When negating a UD
* value, there is a 33rd bit generated for the sign in the
* accumulator value, so now you can't check, for example,
* equality with a 32-bit value. See piglit fs-op-neg-uvec4.
*/
assert(!inst->conditional_mod ||
inst->src[i].type != BRW_REGISTER_TYPE_UD ||
!inst->src[i].negate);
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
}
dst = brw_reg_from_fs_reg(&inst->dst);
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_predicate_control(p, inst->predicate);
brw_set_default_predicate_inverse(p, inst->predicate_inverse);
brw_set_default_flag_reg(p, 0, inst->flag_subreg);
brw_set_default_saturate(p, inst->saturate);
brw_set_default_mask_control(p, inst->force_writemask_all);
brw_set_default_acc_write_control(p, inst->writes_accumulator);
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
i965/fs: Move brw_wm_compile::dispatch_width into fs_visitor. Also, rather than having brw_wm_fs_emit poke at it directly, make it a parameter to the fs_visitor constructor. All other changes generated by search and replace (with occasional whitespace fixup). v2: Make dispatch_width const (as suggested by Paul); fix doxygen mistake (pointed out by Eric); update for rebase. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-11-20 21:50:52 +00:00
if (inst->force_uncompressed || dispatch_width == 8) {
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
} else if (inst->force_sechalf) {
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
} else {
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
}
switch (inst->opcode) {
case BRW_OPCODE_MOV:
brw_MOV(p, dst, src[0]);
break;
case BRW_OPCODE_ADD:
brw_ADD(p, dst, src[0], src[1]);
break;
case BRW_OPCODE_MUL:
brw_MUL(p, dst, src[0], src[1]);
break;
i965/fs: add support for BRW_OPCODE_AVG in fs_generator Needed for compiling blorp blit programs. Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-12-17 14:39:16 +00:00
case BRW_OPCODE_AVG:
brw_AVG(p, dst, src[0], src[1]);
break;
i965/fs: Fix 32-bit integer multiplication. The MUL opcode does a 16bit * 32bit multiply, and we need to do the MACH to get the top 16bit * 32bit added in. Fixes fs-op-mult-int-*, fs-op-mult-ivec* Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-08-16 06:36:18 +01:00
case BRW_OPCODE_MACH:
brw_MACH(p, dst, src[0], src[1]);
break;
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
i965/fs: Add support for generating MADs. Improves nexuiz performance 0.65% +/- .10% (n=5) on my gen6, and .39% +/- .11% (n=10) on gen7. No statistically significant performance difference on warsow (n=5, but only one shader has MADs). v2: Add support for MADs in 16-wide by using compression control. v3: Don't generate MADs when it will force an immediate to be moved to a temp. (it's not clear whether this is a win or not, but it should result in less questionable change to codegen compared to v2). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v2)
2012-02-06 23:59:11 +00:00
case BRW_OPCODE_MAD:
i965: Add Gen assertion checks for newer instructions. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-09-20 06:55:24 +01:00
assert(brw->gen >= 6);
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_access_mode(p, BRW_ALIGN_16);
i965: Extend is_haswell checks to gen >= 8 in Gen4-7 generators. We're going to use fs_generator/vec4_generator for Gen8+ code soon, thanks to the new brw_instruction API. When we do, we'll generally want to take the Haswell paths on Gen8+ as well. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-08 07:52:37 +01:00
if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
i965/fs: Add support for generating MADs. Improves nexuiz performance 0.65% +/- .10% (n=5) on my gen6, and .39% +/- .11% (n=10) on gen7. No statistically significant performance difference on warsow (n=5, but only one shader has MADs). v2: Add support for MADs in 16-wide by using compression control. v3: Don't generate MADs when it will force an immediate to be moved to a temp. (it's not clear whether this is a win or not, but it should result in less questionable change to codegen compared to v2). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v2)
2012-02-06 23:59:11 +00:00
brw_MAD(p, dst, src[0], src[1], src[2]);
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
i965/fs: Add support for generating MADs. Improves nexuiz performance 0.65% +/- .10% (n=5) on my gen6, and .39% +/- .11% (n=10) on gen7. No statistically significant performance difference on warsow (n=5, but only one shader has MADs). v2: Add support for MADs in 16-wide by using compression control. v3: Don't generate MADs when it will force an immediate to be moved to a temp. (it's not clear whether this is a win or not, but it should result in less questionable change to codegen compared to v2). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v2)
2012-02-06 23:59:11 +00:00
brw_MAD(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
i965/fs: Add support for generating MADs. Improves nexuiz performance 0.65% +/- .10% (n=5) on my gen6, and .39% +/- .11% (n=10) on gen7. No statistically significant performance difference on warsow (n=5, but only one shader has MADs). v2: Add support for MADs in 16-wide by using compression control. v3: Don't generate MADs when it will force an immediate to be moved to a temp. (it's not clear whether this is a win or not, but it should result in less questionable change to codegen compared to v2). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v2)
2012-02-06 23:59:11 +00:00
} else {
brw_MAD(p, dst, src[0], src[1], src[2]);
}
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_access_mode(p, BRW_ALIGN_1);
i965/fs: Add support for generating MADs. Improves nexuiz performance 0.65% +/- .10% (n=5) on my gen6, and .39% +/- .11% (n=10) on gen7. No statistically significant performance difference on warsow (n=5, but only one shader has MADs). v2: Add support for MADs in 16-wide by using compression control. v3: Don't generate MADs when it will force an immediate to be moved to a temp. (it's not clear whether this is a win or not, but it should result in less questionable change to codegen compared to v2). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v2)
2012-02-06 23:59:11 +00:00
break;
i965/fs: Use the LRP instruction for ir_triop_lrp when possible. v2 [mattst88]: - Add BRW_OPCODE_LRP to list of CSE-able expressions. - Fix op_var[] array size. - Rename arguments to emit_lrp to (x, y, a) to clear confusion. - Add LRP function to brw_fs.cpp/.h. - Corrected comment about LRP instruction arguments in emit_lrp. v3 [mattst88]: - Duplicate MAD code for LRP instead of using a function pointer. - Check for != GRF instead of == IMM in emit_lrp. - Lower LRP on gen < 6. Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> 1
2012-12-02 08:08:15 +00:00
case BRW_OPCODE_LRP:
i965: Add Gen assertion checks for newer instructions. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-09-20 06:55:24 +01:00
assert(brw->gen >= 6);
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_access_mode(p, BRW_ALIGN_16);
i965: Extend is_haswell checks to gen >= 8 in Gen4-7 generators. We're going to use fs_generator/vec4_generator for Gen8+ code soon, thanks to the new brw_instruction API. When we do, we'll generally want to take the Haswell paths on Gen8+ as well. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-08 07:52:37 +01:00
if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
i965/fs: Use the LRP instruction for ir_triop_lrp when possible. v2 [mattst88]: - Add BRW_OPCODE_LRP to list of CSE-able expressions. - Fix op_var[] array size. - Rename arguments to emit_lrp to (x, y, a) to clear confusion. - Add LRP function to brw_fs.cpp/.h. - Corrected comment about LRP instruction arguments in emit_lrp. v3 [mattst88]: - Duplicate MAD code for LRP instead of using a function pointer. - Check for != GRF instead of == IMM in emit_lrp. - Lower LRP on gen < 6. Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> 1
2012-12-02 08:08:15 +00:00
brw_LRP(p, dst, src[0], src[1], src[2]);
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
i965/fs: Use the LRP instruction for ir_triop_lrp when possible. v2 [mattst88]: - Add BRW_OPCODE_LRP to list of CSE-able expressions. - Fix op_var[] array size. - Rename arguments to emit_lrp to (x, y, a) to clear confusion. - Add LRP function to brw_fs.cpp/.h. - Corrected comment about LRP instruction arguments in emit_lrp. v3 [mattst88]: - Duplicate MAD code for LRP instead of using a function pointer. - Check for != GRF instead of == IMM in emit_lrp. - Lower LRP on gen < 6. Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> 1
2012-12-02 08:08:15 +00:00
brw_LRP(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
i965/fs: Use the LRP instruction for ir_triop_lrp when possible. v2 [mattst88]: - Add BRW_OPCODE_LRP to list of CSE-able expressions. - Fix op_var[] array size. - Rename arguments to emit_lrp to (x, y, a) to clear confusion. - Add LRP function to brw_fs.cpp/.h. - Corrected comment about LRP instruction arguments in emit_lrp. v3 [mattst88]: - Duplicate MAD code for LRP instead of using a function pointer. - Check for != GRF instead of == IMM in emit_lrp. - Lower LRP on gen < 6. Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> 1
2012-12-02 08:08:15 +00:00
} else {
brw_LRP(p, dst, src[0], src[1], src[2]);
}
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_access_mode(p, BRW_ALIGN_1);
i965/fs: Use the LRP instruction for ir_triop_lrp when possible. v2 [mattst88]: - Add BRW_OPCODE_LRP to list of CSE-able expressions. - Fix op_var[] array size. - Rename arguments to emit_lrp to (x, y, a) to clear confusion. - Add LRP function to brw_fs.cpp/.h. - Corrected comment about LRP instruction arguments in emit_lrp. v3 [mattst88]: - Duplicate MAD code for LRP instead of using a function pointer. - Check for != GRF instead of == IMM in emit_lrp. - Lower LRP on gen < 6. Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> 1
2012-12-02 08:08:15 +00:00
break;
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
case BRW_OPCODE_FRC:
brw_FRC(p, dst, src[0]);
break;
case BRW_OPCODE_RNDD:
brw_RNDD(p, dst, src[0]);
break;
case BRW_OPCODE_RNDE:
brw_RNDE(p, dst, src[0]);
break;
case BRW_OPCODE_RNDZ:
brw_RNDZ(p, dst, src[0]);
break;
case BRW_OPCODE_AND:
brw_AND(p, dst, src[0], src[1]);
break;
case BRW_OPCODE_OR:
brw_OR(p, dst, src[0], src[1]);
break;
case BRW_OPCODE_XOR:
brw_XOR(p, dst, src[0], src[1]);
break;
case BRW_OPCODE_NOT:
brw_NOT(p, dst, src[0]);
break;
case BRW_OPCODE_ASR:
brw_ASR(p, dst, src[0], src[1]);
break;
case BRW_OPCODE_SHR:
brw_SHR(p, dst, src[0], src[1]);
break;
case BRW_OPCODE_SHL:
brw_SHL(p, dst, src[0], src[1]);
break;
i965/fs/gen7: Emit code for GLSL 3.00 pack/unpack operations (v4) v2: Remove lewd comment. [for idr] v3: - Optimize away tmp register for packHalf2x16. [for anholt, paul] - Improve comments. [for anholt, paul] - Reduce near-duplicate code by removing vec4_visitor emit_pack/unpack methods. [for chadv] v4: Factor our UD/W register conversion into helper function. [for anholt] Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v2) Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
2013-01-09 19:46:42 +00:00
case BRW_OPCODE_F32TO16:
i965: Add Gen assertion checks for newer instructions. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-09-20 06:55:24 +01:00
assert(brw->gen >= 7);
i965/fs/gen7: Emit code for GLSL 3.00 pack/unpack operations (v4) v2: Remove lewd comment. [for idr] v3: - Optimize away tmp register for packHalf2x16. [for anholt, paul] - Improve comments. [for anholt, paul] - Reduce near-duplicate code by removing vec4_visitor emit_pack/unpack methods. [for chadv] v4: Factor our UD/W register conversion into helper function. [for anholt] Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v2) Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
2013-01-09 19:46:42 +00:00
brw_F32TO16(p, dst, src[0]);
break;
case BRW_OPCODE_F16TO32:
i965: Add Gen assertion checks for newer instructions. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-09-20 06:55:24 +01:00
assert(brw->gen >= 7);
i965/fs/gen7: Emit code for GLSL 3.00 pack/unpack operations (v4) v2: Remove lewd comment. [for idr] v3: - Optimize away tmp register for packHalf2x16. [for anholt, paul] - Improve comments. [for anholt, paul] - Reduce near-duplicate code by removing vec4_visitor emit_pack/unpack methods. [for chadv] v4: Factor our UD/W register conversion into helper function. [for anholt] Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v2) Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
2013-01-09 19:46:42 +00:00
brw_F16TO32(p, dst, src[0]);
break;
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
case BRW_OPCODE_CMP:
brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
break;
case BRW_OPCODE_SEL:
brw_SEL(p, dst, src[0], src[1]);
break;
i965/fs: Add support for bit instructions. Don't bother scalarizing ir_binop_bfm, since its results are identical for all channels. v2: Subtract result of FBH from 31 (unless an error) to convert MSB counts to LSB counts. v3: Use op0->clone() in ir_triop_bfi to prevent (var_ref channel_expressions) from appearing multiple times in the IR. Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v2]
2013-04-10 03:22:34 +01:00
case BRW_OPCODE_BFREV:
i965: Add Gen assertion checks for newer instructions. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-09-20 06:55:24 +01:00
assert(brw->gen >= 7);
i965/fs: Add support for bit instructions. Don't bother scalarizing ir_binop_bfm, since its results are identical for all channels. v2: Subtract result of FBH from 31 (unless an error) to convert MSB counts to LSB counts. v3: Use op0->clone() in ir_triop_bfi to prevent (var_ref channel_expressions) from appearing multiple times in the IR. Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v2]
2013-04-10 03:22:34 +01:00
/* BFREV only supports UD type for src and dst. */
brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
retype(src[0], BRW_REGISTER_TYPE_UD));
break;
case BRW_OPCODE_FBH:
i965: Add Gen assertion checks for newer instructions. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-09-20 06:55:24 +01:00
assert(brw->gen >= 7);
i965/fs: Add support for bit instructions. Don't bother scalarizing ir_binop_bfm, since its results are identical for all channels. v2: Subtract result of FBH from 31 (unless an error) to convert MSB counts to LSB counts. v3: Use op0->clone() in ir_triop_bfi to prevent (var_ref channel_expressions) from appearing multiple times in the IR. Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v2]
2013-04-10 03:22:34 +01:00
/* FBH only supports UD type for dst. */
brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
break;
case BRW_OPCODE_FBL:
i965: Add Gen assertion checks for newer instructions. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-09-20 06:55:24 +01:00
assert(brw->gen >= 7);
i965/fs: Add support for bit instructions. Don't bother scalarizing ir_binop_bfm, since its results are identical for all channels. v2: Subtract result of FBH from 31 (unless an error) to convert MSB counts to LSB counts. v3: Use op0->clone() in ir_triop_bfi to prevent (var_ref channel_expressions) from appearing multiple times in the IR. Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v2]
2013-04-10 03:22:34 +01:00
/* FBL only supports UD type for dst. */
brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
break;
case BRW_OPCODE_CBIT:
i965: Add Gen assertion checks for newer instructions. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-09-20 06:55:24 +01:00
assert(brw->gen >= 7);
i965/fs: Add support for bit instructions. Don't bother scalarizing ir_binop_bfm, since its results are identical for all channels. v2: Subtract result of FBH from 31 (unless an error) to convert MSB counts to LSB counts. v3: Use op0->clone() in ir_triop_bfi to prevent (var_ref channel_expressions) from appearing multiple times in the IR. Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v2]
2013-04-10 03:22:34 +01:00
/* CBIT only supports UD type for dst. */
brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
break;
i965: Generate code for ir_binop_carry and ir_binop_borrow. Using the ADDC and SUBB instructions on Gen7. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-09-19 21:01:08 +01:00
case BRW_OPCODE_ADDC:
assert(brw->gen >= 7);
brw_ADDC(p, dst, src[0], src[1]);
break;
case BRW_OPCODE_SUBB:
assert(brw->gen >= 7);
brw_SUBB(p, dst, src[0], src[1]);
break;
i965/fs: Add support for the MAC instruction. This allows us to generate the MAC (multiply-accumulate) instruction, which can be used to implement some expressions in fewer instructions than doing a series of MUL and ADDs. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
2014-03-28 13:28:32 +00:00
case BRW_OPCODE_MAC:
brw_MAC(p, dst, src[0], src[1]);
break;
i965/fs: Add support for bit instructions. Don't bother scalarizing ir_binop_bfm, since its results are identical for all channels. v2: Subtract result of FBH from 31 (unless an error) to convert MSB counts to LSB counts. v3: Use op0->clone() in ir_triop_bfi to prevent (var_ref channel_expressions) from appearing multiple times in the IR. Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v2]
2013-04-10 03:22:34 +01:00
case BRW_OPCODE_BFE:
i965: Add Gen assertion checks for newer instructions. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-09-20 06:55:24 +01:00
assert(brw->gen >= 7);
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_access_mode(p, BRW_ALIGN_16);
i965: Extend is_haswell checks to gen >= 8 in Gen4-7 generators. We're going to use fs_generator/vec4_generator for Gen8+ code soon, thanks to the new brw_instruction API. When we do, we'll generally want to take the Haswell paths on Gen8+ as well. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-08 07:52:37 +01:00
if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
i965/fs: Add support for bit instructions. Don't bother scalarizing ir_binop_bfm, since its results are identical for all channels. v2: Subtract result of FBH from 31 (unless an error) to convert MSB counts to LSB counts. v3: Use op0->clone() in ir_triop_bfi to prevent (var_ref channel_expressions) from appearing multiple times in the IR. Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v2]
2013-04-10 03:22:34 +01:00
brw_BFE(p, dst, src[0], src[1], src[2]);
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
i965/fs: Add support for bit instructions. Don't bother scalarizing ir_binop_bfm, since its results are identical for all channels. v2: Subtract result of FBH from 31 (unless an error) to convert MSB counts to LSB counts. v3: Use op0->clone() in ir_triop_bfi to prevent (var_ref channel_expressions) from appearing multiple times in the IR. Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v2]
2013-04-10 03:22:34 +01:00
brw_BFE(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
i965/fs: Add support for bit instructions. Don't bother scalarizing ir_binop_bfm, since its results are identical for all channels. v2: Subtract result of FBH from 31 (unless an error) to convert MSB counts to LSB counts. v3: Use op0->clone() in ir_triop_bfi to prevent (var_ref channel_expressions) from appearing multiple times in the IR. Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v2]
2013-04-10 03:22:34 +01:00
} else {
brw_BFE(p, dst, src[0], src[1], src[2]);
}
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_access_mode(p, BRW_ALIGN_1);
i965/fs: Add support for bit instructions. Don't bother scalarizing ir_binop_bfm, since its results are identical for all channels. v2: Subtract result of FBH from 31 (unless an error) to convert MSB counts to LSB counts. v3: Use op0->clone() in ir_triop_bfi to prevent (var_ref channel_expressions) from appearing multiple times in the IR. Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v2]
2013-04-10 03:22:34 +01:00
break;
case BRW_OPCODE_BFI1:
i965: Add Gen assertion checks for newer instructions. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-09-20 06:55:24 +01:00
assert(brw->gen >= 7);
i965/fs: Don't emit SIMD16 BFI instructions. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-16 21:16:50 +00:00
/* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
* should
*
* "Force BFI instructions to be executed always in SIMD8."
*/
if (dispatch_width == 16 && brw->is_haswell) {
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
i965/fs: Don't emit SIMD16 BFI instructions. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-16 21:16:50 +00:00
brw_BFI1(p, dst, src[0], src[1]);
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
i965/fs: Don't emit SIMD16 BFI instructions. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-16 21:16:50 +00:00
brw_BFI1(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]));
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
i965/fs: Don't emit SIMD16 BFI instructions. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-16 21:16:50 +00:00
} else {
brw_BFI1(p, dst, src[0], src[1]);
}
i965/fs: Add support for bit instructions. Don't bother scalarizing ir_binop_bfm, since its results are identical for all channels. v2: Subtract result of FBH from 31 (unless an error) to convert MSB counts to LSB counts. v3: Use op0->clone() in ir_triop_bfi to prevent (var_ref channel_expressions) from appearing multiple times in the IR. Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v2]
2013-04-10 03:22:34 +01:00
break;
case BRW_OPCODE_BFI2:
i965: Add Gen assertion checks for newer instructions. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-09-20 06:55:24 +01:00
assert(brw->gen >= 7);
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_access_mode(p, BRW_ALIGN_16);
i965/fs: Don't emit SIMD16 BFI instructions. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-16 21:16:50 +00:00
/* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
* should
*
* "Force BFI instructions to be executed always in SIMD8."
*
* Otherwise we would be able to emit compressed instructions like we
* do for the other three-source instructions.
*/
i965/fs: Add support for bit instructions. Don't bother scalarizing ir_binop_bfm, since its results are identical for all channels. v2: Subtract result of FBH from 31 (unless an error) to convert MSB counts to LSB counts. v3: Use op0->clone() in ir_triop_bfi to prevent (var_ref channel_expressions) from appearing multiple times in the IR. Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v2]
2013-04-10 03:22:34 +01:00
if (dispatch_width == 16) {
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
i965/fs: Add support for bit instructions. Don't bother scalarizing ir_binop_bfm, since its results are identical for all channels. v2: Subtract result of FBH from 31 (unless an error) to convert MSB counts to LSB counts. v3: Use op0->clone() in ir_triop_bfi to prevent (var_ref channel_expressions) from appearing multiple times in the IR. Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v2]
2013-04-10 03:22:34 +01:00
brw_BFI2(p, dst, src[0], src[1], src[2]);
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
i965/fs: Add support for bit instructions. Don't bother scalarizing ir_binop_bfm, since its results are identical for all channels. v2: Subtract result of FBH from 31 (unless an error) to convert MSB counts to LSB counts. v3: Use op0->clone() in ir_triop_bfi to prevent (var_ref channel_expressions) from appearing multiple times in the IR. Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v2]
2013-04-10 03:22:34 +01:00
brw_BFI2(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
i965/fs: Add support for bit instructions. Don't bother scalarizing ir_binop_bfm, since its results are identical for all channels. v2: Subtract result of FBH from 31 (unless an error) to convert MSB counts to LSB counts. v3: Use op0->clone() in ir_triop_bfi to prevent (var_ref channel_expressions) from appearing multiple times in the IR. Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v2]
2013-04-10 03:22:34 +01:00
} else {
brw_BFI2(p, dst, src[0], src[1], src[2]);
}
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_access_mode(p, BRW_ALIGN_1);
i965/fs: Add support for bit instructions. Don't bother scalarizing ir_binop_bfm, since its results are identical for all channels. v2: Subtract result of FBH from 31 (unless an error) to convert MSB counts to LSB counts. v3: Use op0->clone() in ir_triop_bfi to prevent (var_ref channel_expressions) from appearing multiple times in the IR. Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v2]
2013-04-10 03:22:34 +01:00
break;
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
case BRW_OPCODE_IF:
if (inst->src[0].file != BAD_FILE) {
/* The instruction has an embedded compare (only allowed on gen6) */
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 08:36:46 +01:00
assert(brw->gen == 6);
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
gen6_IF(p, inst->conditional_mod, src[0], src[1]);
} else {
i965/fs: Move brw_wm_compile::dispatch_width into fs_visitor. Also, rather than having brw_wm_fs_emit poke at it directly, make it a parameter to the fs_visitor constructor. All other changes generated by search and replace (with occasional whitespace fixup). v2: Make dispatch_width const (as suggested by Paul); fix doxygen mistake (pointed out by Eric); update for rebase. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-11-20 21:50:52 +00:00
brw_IF(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
}
break;
case BRW_OPCODE_ELSE:
brw_ELSE(p);
break;
case BRW_OPCODE_ENDIF:
brw_ENDIF(p);
break;
case BRW_OPCODE_DO:
i965: Don't make consumers of brw_WHILE do pre-gen6 BREAK/CONT patching. The EU code itself can just do this work, since all the consumers were duplicating it. Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
2011-12-06 20:30:03 +00:00
brw_DO(p, BRW_EXECUTE_8);
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
break;
case BRW_OPCODE_BREAK:
i965: Don't make consumers of brw_CONT/brw_WHILE track if depth in loop. The codegen backends all had this same tracking, so just do it at the EU level. Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
2011-12-06 20:44:41 +00:00
brw_BREAK(p);
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
break;
case BRW_OPCODE_CONTINUE:
/* FINISHME: We need to write the loop instruction support still. */
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 08:36:46 +01:00
if (brw->gen >= 6)
i965: Drop unused do_insn argument from gen6_CONT(). The branch distances get patched up later at the WHILE instruction. Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
2011-12-06 20:09:58 +00:00
gen6_CONT(p);
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
else
i965: Don't make consumers of brw_CONT/brw_WHILE track if depth in loop. The codegen backends all had this same tracking, so just do it at the EU level. Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
2011-12-06 20:44:41 +00:00
brw_CONT(p);
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
break;
i965: Don't make consumers of brw_WHILE do pre-gen6 BREAK/CONT patching. The EU code itself can just do this work, since all the consumers were duplicating it. Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
2011-12-06 20:30:03 +00:00
case BRW_OPCODE_WHILE:
brw_WHILE(p);
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
break;
i965: Rename math FS_OPCODE_* to SHADER_OPCODE_*. I want to just use the same enums in the VS.
2011-08-05 20:38:58 +01:00
case SHADER_OPCODE_RCP:
case SHADER_OPCODE_RSQ:
case SHADER_OPCODE_SQRT:
case SHADER_OPCODE_EXP2:
case SHADER_OPCODE_LOG2:
case SHADER_OPCODE_SIN:
case SHADER_OPCODE_COS:
i965/fs: Drop the generate_math[12]_gen7 methods. These functions are basically identical, so we should combine them. However, they're so trivial, we may as well just fold them into their only call sites. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-06-07 10:27:43 +01:00
assert(brw->gen < 6 || inst->mlen == 0);
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 08:36:46 +01:00
if (brw->gen >= 7) {
i965/fs: Drop the generate_math[12]_gen7 methods. These functions are basically identical, so we should combine them. However, they're so trivial, we may as well just fold them into their only call sites. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-06-07 10:27:43 +01:00
gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
brw_null_reg());
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 08:36:46 +01:00
} else if (brw->gen == 6) {
i965/fs: Combine generate_math[12]_gen6 methods. These used to call different math emitters (brw_math vs. brw_math2). Now that they both call gen6_math, they're virtually identical. When unrolling SIMD16 to multiple SIMD8 operations, we should take care not to apply sechalf to brw_null_reg for src1. Otherwise, we'd end up with BRW_ARF_NULL + 1 as the register number, and I'm not sure if that's valid. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-06-07 10:21:47 +01:00
generate_math_gen6(inst, dst, src[0], brw_null_reg());
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 08:36:46 +01:00
} else if (brw->gen == 5 || brw->is_g4x) {
i965: Implement 16-wide math on G45 and Ironlake. [chrisf:] Improves performance in CS:S video stress test by about 2%. No piglit regressions on Ironlake. Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2013-03-30 07:15:54 +00:00
generate_math_g45(inst, dst, src[0]);
i965/fs: Split generate_math into gen4/gen6 and 1/2 operand variants. This mirrors the structure Eric used in the new VS backend, and seems simpler. In particular, the math1/math2 split will avoid having to figure out how many operands there are, as this is already known by the caller. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-08-18 19:55:42 +01:00
} else {
generate_math_gen4(inst, dst, src[0]);
}
break;
i965/fs: Implement integer quotient and remainder math operations. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Tested-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-09-29 01:37:54 +01:00
case SHADER_OPCODE_INT_QUOTIENT:
case SHADER_OPCODE_INT_REMAINDER:
i965/fs: Split generate_math into gen4/gen6 and 1/2 operand variants. This mirrors the structure Eric used in the new VS backend, and seems simpler. In particular, the math1/math2 split will avoid having to figure out how many operands there are, as this is already known by the caller. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-08-18 19:55:42 +01:00
case SHADER_OPCODE_POW:
i965/fs: Drop the generate_math[12]_gen7 methods. These functions are basically identical, so we should combine them. However, they're so trivial, we may as well just fold them into their only call sites. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-06-07 10:27:43 +01:00
assert(brw->gen < 6 || inst->mlen == 0);
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 08:36:46 +01:00
if (brw->gen >= 7) {
i965/fs: Drop the generate_math[12]_gen7 methods. These functions are basically identical, so we should combine them. However, they're so trivial, we may as well just fold them into their only call sites. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-06-07 10:27:43 +01:00
gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
i965: Move intel_context::gen and gt fields to brw_context. Most functions no longer use intel_context, so this patch additionally removes the local "intel" variables to avoid compiler warnings. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Chris Forbes <chrisf@ijw.co.nz> Acked-by: Paul Berry <stereotype441@gmail.com> Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
2013-07-06 08:36:46 +01:00
} else if (brw->gen == 6) {
i965/fs: Combine generate_math[12]_gen6 methods. These used to call different math emitters (brw_math vs. brw_math2). Now that they both call gen6_math, they're virtually identical. When unrolling SIMD16 to multiple SIMD8 operations, we should take care not to apply sechalf to brw_null_reg for src1. Otherwise, we'd end up with BRW_ARF_NULL + 1 as the register number, and I'm not sure if that's valid. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2014-06-07 10:21:47 +01:00
generate_math_gen6(inst, dst, src[0], src[1]);
i965/fs: Split generate_math into gen4/gen6 and 1/2 operand variants. This mirrors the structure Eric used in the new VS backend, and seems simpler. In particular, the math1/math2 split will avoid having to figure out how many operands there are, as this is already known by the caller. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-08-18 19:55:42 +01:00
} else {
generate_math_gen4(inst, dst, src[0]);
}
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
break;
case FS_OPCODE_PIXEL_X:
generate_pixel_xy(dst, true);
break;
case FS_OPCODE_PIXEL_Y:
generate_pixel_xy(dst, false);
break;
case FS_OPCODE_CINTERP:
brw_MOV(p, dst, src[0]);
break;
case FS_OPCODE_LINTERP:
generate_linterp(inst, dst, src);
break;
i965: Rename texturing ops from FS_OPCODE to SHADER_OPCODE, except TXB. We'll be reusing most of these for the VS shortly. The one exception is TXB (texturing with LOD bias), which is explicitly forbidden in the VS. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-10-26 20:58:37 +01:00
case SHADER_OPCODE_TEX:
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
case FS_OPCODE_TXB:
i965: Rename texturing ops from FS_OPCODE to SHADER_OPCODE, except TXB. We'll be reusing most of these for the VS shortly. The one exception is TXB (texturing with LOD bias), which is explicitly forbidden in the VS. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-10-26 20:58:37 +01:00
case SHADER_OPCODE_TXD:
case SHADER_OPCODE_TXF:
i965: rename tex_ms to tex_cms Prepares for the introduction of non-compressed multi-sampled lookup used in the blorp programs. v2: now also taking into account gen8 Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-12-10 14:36:31 +00:00
case SHADER_OPCODE_TXF_CMS:
i965/fs: introduce non-compressed equivalent of tex_cms v2: introduces 'SHADER_OPCODE_TXF_UMS' also for gen8 Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-12-10 14:38:15 +00:00
case SHADER_OPCODE_TXF_UMS:
i965: Add shader opcode for sampling MCS surface Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Paul Berry <stereotype441@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-11-29 21:32:16 +00:00
case SHADER_OPCODE_TXF_MCS:
i965: Rename texturing ops from FS_OPCODE to SHADER_OPCODE, except TXB. We'll be reusing most of these for the VS shortly. The one exception is TXB (texturing with LOD bias), which is explicitly forbidden in the VS. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-10-26 20:58:37 +01:00
case SHADER_OPCODE_TXL:
case SHADER_OPCODE_TXS:
i965/fs: Generate LOD sampler message from ir_lod. v2: Support Ironlake as well. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-06 22:47:01 +00:00
case SHADER_OPCODE_LOD:
i965: add SHADER_OPCODE_TG4 Adds the Gen7 message IDs, a new SHADER_OPCODE_TG4 pseudo-op, and low-level support for emitting it via generate_tex(). V3: Updated for changes in master. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-31 09:31:12 +01:00
case SHADER_OPCODE_TG4:
i965: Add SHADER_OPCODE_TG4_OFFSET for gather with nonconstant offsets. The generator code ends up clearer this way than if we had to sniff via the message length. Implemented via the gather4_po message in hardware, which is present in Gen7 and later. Signed-off-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-10-08 09:42:10 +01:00
case SHADER_OPCODE_TG4_OFFSET:
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
generate_tex(inst, dst, src[0]);
break;
case FS_OPCODE_DDX:
generate_ddx(inst, dst, src[0]);
break;
case FS_OPCODE_DDY:
i965: Avoid unnecessary recompiles for shaders that don't use dFdy(). The i965 back-end needs to compile dFdy() differently for FBOs and window system framebuffers, because Y coordinates are flipped between the two (see commit 82d2596: i965: Compute dFdy() correctly for FBOs). This patch avoids unnecessarily recompiling shaders that don't use dFdy(), by only setting render_to_fbo in the wm program key if the shader actually uses dFdy(). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2012-06-20 21:40:45 +01:00
/* Make sure fp->UsesDFdy flag got set (otherwise there's no
i965/fs: Replace c->key with a direct reference in the generators. 'c' is going away. This is also a bit shorter. Marking the key pointer as const will also deter people from changing it in these classes, as that's absolutely not OK. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-05-14 08:24:50 +01:00
* guarantee that key->render_to_fbo is set).
i965: Avoid unnecessary recompiles for shaders that don't use dFdy(). The i965 back-end needs to compile dFdy() differently for FBOs and window system framebuffers, because Y coordinates are flipped between the two (see commit 82d2596: i965: Compute dFdy() correctly for FBOs). This patch avoids unnecessarily recompiling shaders that don't use dFdy(), by only setting render_to_fbo in the wm program key if the shader actually uses dFdy(). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2012-06-20 21:40:45 +01:00
*/
assert(fp->UsesDFdy);
i965/fs: Replace c->key with a direct reference in the generators. 'c' is going away. This is also a bit shorter. Marking the key pointer as const will also deter people from changing it in these classes, as that's absolutely not OK. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-05-14 08:24:50 +01:00
generate_ddy(inst, dst, src[0], key->render_to_fbo);
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
break;
i965: Merge together opcodes for SHADER_OPCODE_GEN4_SCRATCH_READ/WRITE I'm going to be introducing gen7 variants, and the previous naming was going to get confusing. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-10-16 19:45:06 +01:00
case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
generate_scratch_write(inst, src[0]);
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
break;
i965: Merge together opcodes for SHADER_OPCODE_GEN4_SCRATCH_READ/WRITE I'm going to be introducing gen7 variants, and the previous naming was going to get confusing. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-10-16 19:45:06 +01:00
case SHADER_OPCODE_GEN4_SCRATCH_READ:
generate_scratch_read(inst, dst);
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
break;
i965/fs: Use the gen7 scratch read opcode when possible. This avoids a lot of message setup we had to do otherwise. Improves GLB2.7 performance with register spilling force enabled by 1.6442% +/- 0.553218% (n=4). v2: Use BRW_PREDICATE_NONE, improve a comment (by Paul). Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-10-16 19:51:22 +01:00
case SHADER_OPCODE_GEN7_SCRATCH_READ:
generate_scratch_read_gen7(inst, dst);
break;
i965/fs: Rename the existing pull constant load opcode. We're going to use another send message for handling loads with a varying per-fragment array index.
2012-11-07 18:42:34 +00:00
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
generate_uniform_pull_constant_load(inst, dst, src[0], src[1]);
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
break;
i965/fs: Set up gen7 UBO loads as sends from GRFs. This gives the instruction scheduler a chance to schedule between the loads, whereas before it was restricted due to the dependencies between the MRFs for setting them up. For one shader in gles3conform, it goes from getting stuck in register allocation for as long as anybody's bothered to leave it running down to 23 seconds, thanks to the LIFO scheduling. Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-05 08:06:30 +00:00
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]);
break;
i965/fs: Add instruction emit for varying-index reads of uniforms. The gen7 send-from-GRF path is sufficiently different from the perspective of IR generation and optimization that I just made it a separate opcode. v2: fix whitespace, rebase on Ken's recent refactor.
2012-11-07 19:18:34 +00:00
case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
i965/fs: Use LD messages for pre-gen7 varying-index uniform loads This comes at a minor performance cost at the moment (-3.2% +/- 0.2%, n=14 on my GM45 forced to load all uniforms through the varying-index path), but we get a whole vec4 at a time to reuse in the next commit. v2: Fix comment about channels in the other message. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> NOTE: This is a candidate for the 9.1 branch.
2013-03-18 17:16:42 +00:00
generate_varying_pull_constant_load(inst, dst, src[0], src[1]);
i965/fs: Add instruction emit for varying-index reads of uniforms. The gen7 send-from-GRF path is sufficiently different from the perspective of IR generation and optimization that I just made it a separate opcode. v2: fix whitespace, rebase on Ken's recent refactor.
2012-11-07 19:18:34 +00:00
break;
case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
generate_varying_pull_constant_load_gen7(inst, dst, src[0], src[1]);
break;
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
case FS_OPCODE_FB_WRITE:
generate_fb_write(inst);
break;
i965/fs: Add FS_OPCODE_MOV_DISPATCH_TO_FLAGS to fragment shader backend. In order to compute centroid varyings correctly, the fragment shader needs to be able to load the current pixel/sample mask into a flag register. This patch adds an opcode to the fragment shader back-end to do this; the opcode gets translated into the instruction mov(1) f0<1>UW g1.14<0,1,0>UW { align1 WE_all } Since this instruction clobbers f0, instruction scheduling has to treat it the same as instructions that have a conditional modifier. Reviewed-by: Eric Anholt <eric@anholt.net>
2012-06-18 22:50:04 +01:00
i965/fs: introduce blorp specific rt-write for fs_generator The compiler for blorp programs likes to emit instructions for the message construction itself meaning that the generator needs to skip any such when blorp programs are translated for the hw. In addition, the binding table control is special for blorp programs and the generator does not need to update the binding tables associated with the compiler bookkeeping (this in fact gets thrown away as the blorp compiler sets the program data in its own way). v2 (Paul): do not hardcode the binding table index but use fs_inst::target instead. Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-12-17 12:00:50 +00:00
case FS_OPCODE_BLORP_FB_WRITE:
generate_blorp_fb_write(inst);
break;
i965/fs: Add FS_OPCODE_MOV_DISPATCH_TO_FLAGS to fragment shader backend. In order to compute centroid varyings correctly, the fragment shader needs to be able to load the current pixel/sample mask into a flag register. This patch adds an opcode to the fragment shader back-end to do this; the opcode gets translated into the instruction mov(1) f0<1>UW g1.14<0,1,0>UW { align1 WE_all } Since this instruction clobbers f0, instruction scheduling has to treat it the same as instructions that have a conditional modifier. Reviewed-by: Eric Anholt <eric@anholt.net>
2012-06-18 22:50:04 +01:00
case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
i965/fs: Add an instruction flag for choosing the flag subregister. We're going to redo discard handling to track discards in the other flag subregister, saving instructions in the discard and allowing predicated jumps out to the end of the shader. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-06 18:36:11 +00:00
generate_mov_dispatch_to_flags(inst);
i965/fs: Add FS_OPCODE_MOV_DISPATCH_TO_FLAGS to fragment shader backend. In order to compute centroid varyings correctly, the fragment shader needs to be able to load the current pixel/sample mask into a flag register. This patch adds an opcode to the fragment shader back-end to do this; the opcode gets translated into the instruction mov(1) f0<1>UW g1.14<0,1,0>UW { align1 WE_all } Since this instruction clobbers f0, instruction scheduling has to treat it the same as instructions that have a conditional modifier. Reviewed-by: Eric Anholt <eric@anholt.net>
2012-06-18 22:50:04 +01:00
break;
i965/fs: Improve performance of shaders that start out with a discard. I had tried this in the past, but ran into trouble with applications that sample from undiscarded pixels in the same subspan. To fix that issue, only jump to the end for an entire subspan at a time. Improves GLbenchmark 2.7 (1024x768) performance by 7.9 +/- 1.5% (n=8). v2: Drop the br variable in the jump instruction -- if I ever do jumps pre-gen6, it'll be a different code block anyway since we don't have HALT until gen6. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-06 18:15:08 +00:00
case FS_OPCODE_DISCARD_JUMP:
generate_discard_jump(inst);
break;
i965: Add a debug flag for counting cycles spent in each compiled shader. This can be used for two purposes: Using hand-coded shaders to determine per-instruction timings, or figuring out which shader to optimize in a whole application. Note that this doesn't cover the instructions that set up the message to the URB/FB write -- we'd need to convert the MRF usage in these instructions to GRFs so that our offsets/times don't overwrite our shader outputs. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1) v2: Check the timestamp reset flag in the VS, which is apparently getting set fairly regularly in the range we watch, resulting in negative numbers getting added to our 32-bit counter, and thus large values added to our uint64_t. v3: Rebase on reladdr changes, removing a new safety check that proved impossible to satisfy. Add a comment to the AOP defs from Ken's review, and put them in a slightly more sensible spot. v4: Check timestamp reset in the FS as well.
2012-11-27 22:10:52 +00:00
case SHADER_OPCODE_SHADER_TIME_ADD:
i965/fs: Switch shader_time writes to using GRFs. This avoids conflicts between shader_time and FB writes, so we can include more of the program under our profiling. This does mean hiding more of the message setup from the optimizer, which doesn't have a way to handle multi-reg sends from GRFs. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-19 22:28:11 +00:00
generate_shader_time_add(inst, src[0], src[1], src[2]);
i965: Add a debug flag for counting cycles spent in each compiled shader. This can be used for two purposes: Using hand-coded shaders to determine per-instruction timings, or figuring out which shader to optimize in a whole application. Note that this doesn't cover the instructions that set up the message to the URB/FB write -- we'd need to convert the MRF usage in these instructions to GRFs so that our offsets/times don't overwrite our shader outputs. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1) v2: Check the timestamp reset flag in the VS, which is apparently getting set fairly regularly in the range we watch, resulting in negative numbers getting added to our 32-bit counter, and thus large values added to our uint64_t. v3: Rebase on reladdr changes, removing a new safety check that proved impossible to satisfy. Add a comment to the AOP defs from Ken's review, and put them in a slightly more sensible spot. v4: Check timestamp reset in the FS as well.
2012-11-27 22:10:52 +00:00
break;
i965/gen7: Implement code generation for untyped atomic instructions. Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-09-11 22:01:50 +01:00
case SHADER_OPCODE_UNTYPED_ATOMIC:
generate_untyped_atomic(inst, dst, src[0], src[1]);
break;
i965/gen7: Implement code generation for untyped surface read instructions.
2013-09-11 22:03:13 +01:00
case SHADER_OPCODE_UNTYPED_SURFACE_READ:
generate_untyped_surface_read(inst, dst, src[0]);
break;
i965/fs: Switch to using sampler LD messages for uniform pull constants. When forcing the compiler to always generate pull constants instead of push constants (in order to have an easy to use testcase), improves performance of my old GLSL demo 23.3553% +/- 1.42968% (n=7). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60866 Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-06 22:47:22 +00:00
case FS_OPCODE_SET_SIMD4X2_OFFSET:
generate_set_simd4x2_offset(inst, dst, src[0]);
i965/fs: Set up gen7 UBO loads as sends from GRFs. This gives the instruction scheduler a chance to schedule between the loads, whereas before it was restricted due to the dependencies between the MRFs for setting them up. For one shader in gles3conform, it goes from getting stuck in register allocation for as long as anybody's bothered to leave it running down to 23 seconds, thanks to the LIFO scheduling. Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2012-12-05 08:06:30 +00:00
break;
i965: Add FS backend for builtin gl_SampleMask[] V2: - Update comments - Add a special backend instructions to compute sample_mask. - Add a new variable uses_omask in brw_wm_prog_data. V3: - Make changes to support simd16 mode. - Delete redundant AND instruction and handle the register stride in FS backend instruction. Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-10-25 00:21:13 +01:00
case FS_OPCODE_SET_OMASK:
generate_set_omask(inst, dst, src[0]);
break;
i965: Add FS backend for builtin gl_SampleID V2: - Update comments - Add compute_sample_id variables in brw_wm_prog_key - Add a special backend instruction to compute sample_id. V3: - Make changes to support simd16 mode. Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-10-25 00:17:08 +01:00
case FS_OPCODE_SET_SAMPLE_ID:
generate_set_sample_id(inst, dst, src[0], src[1]);
break;
i965/fs/gen7: Emit code for GLSL 3.00 pack/unpack operations (v4) v2: Remove lewd comment. [for idr] v3: - Optimize away tmp register for packHalf2x16. [for anholt, paul] - Improve comments. [for anholt, paul] - Reduce near-duplicate code by removing vec4_visitor emit_pack/unpack methods. [for chadv] v4: Factor our UD/W register conversion into helper function. [for anholt] Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v2) Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
2013-01-09 19:46:42 +00:00
case FS_OPCODE_PACK_HALF_2x16_SPLIT:
generate_pack_half_2x16_split(inst, dst, src[0], src[1]);
break;
case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
generate_unpack_half_2x16_split(inst, dst, src[0]);
break;
i965: Fix INTEL_DEBUG=shader_time for fragment shaders with discards. "discard" instructions generate HALT instructions which jump to a final HALT near the end of the shader. Previously, fs_generator created this final jump target when it saw the first FS_OPCODE_FB_WRITE, causing it to jump right before the FB write epilogue. This is normally good. However, INTEL_DEBUG=shader_time also has an epilogue section which records the final timestamp. The frontend emits IR for this just before FS_OPCODE_FB_WRITE. Unfortunately, this led to the following ordering: 1. Shader Time Epilogue 2. Final HALT (where discards jump) 3. Framebuffer Write Epilogue This meant that discarded pixels completely skipped the shader time epilogue, causing no ending timestamp to be written. This obviously led to inaccurate results. This patch adds a new FS_OPCODE_PLACEHOLDER_HALT in the IR stream just before any epilogue sections. This is where the final HALT should be generated, and makes it easy to ensure the correct ordering: 1. Final HALT 2. Shader Time Epilogue 3. Framebuffer Write Epilogue For shaders that don't discard, this opcode compiles away to nothing. The scheduler adds barrier dependencies to make sure that it doesn't get moved above any FS_OPCODE_DISCARD_JUMP instructions. One 8-wide shader in GLBenchmark 2.7 dropped from 2291.67 Gcycles to a mere 5.13 Gcycles. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-03-28 06:19:39 +00:00
case FS_OPCODE_PLACEHOLDER_HALT:
/* This is the place where the final HALT needs to be inserted if
* we've emitted any discards. If not, this will emit no code.
*/
i965: Print disassembly after compaction. Reviewed-by: Eric Anholt <eric@anholt.net>
2014-05-19 18:20:37 +01:00
if (!patch_discard_jumps_to_fb_writes()) {
i965/fs: Don't modify ann_count if not debugging. If we make ann_count non-zero, annotation_finalize() won't bail. Not modifying it seems to make the code more clear than would modifying annotation_finalize().
2014-05-25 18:30:13 +01:00
if (unlikely(debug_flag)) {
i965: Move annotation info into generate code. Suggested by Ken as a way to cut down lines of code. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-25 18:42:32 +01:00
annotation.ann_count--;
i965/fs: Don't modify ann_count if not debugging. If we make ann_count non-zero, annotation_finalize() won't bail. Not modifying it seems to make the code more clear than would modifying annotation_finalize().
2014-05-25 18:30:13 +01:00
}
i965: Print disassembly after compaction. Reviewed-by: Eric Anholt <eric@anholt.net>
2014-05-19 18:20:37 +01:00
}
i965: Fix INTEL_DEBUG=shader_time for fragment shaders with discards. "discard" instructions generate HALT instructions which jump to a final HALT near the end of the shader. Previously, fs_generator created this final jump target when it saw the first FS_OPCODE_FB_WRITE, causing it to jump right before the FB write epilogue. This is normally good. However, INTEL_DEBUG=shader_time also has an epilogue section which records the final timestamp. The frontend emits IR for this just before FS_OPCODE_FB_WRITE. Unfortunately, this led to the following ordering: 1. Shader Time Epilogue 2. Final HALT (where discards jump) 3. Framebuffer Write Epilogue This meant that discarded pixels completely skipped the shader time epilogue, causing no ending timestamp to be written. This obviously led to inaccurate results. This patch adds a new FS_OPCODE_PLACEHOLDER_HALT in the IR stream just before any epilogue sections. This is where the final HALT should be generated, and makes it easy to ensure the correct ordering: 1. Final HALT 2. Shader Time Epilogue 3. Framebuffer Write Epilogue For shaders that don't discard, this opcode compiles away to nothing. The scheduler adds barrier dependencies to make sure that it doesn't get moved above any FS_OPCODE_DISCARD_JUMP instructions. One 8-wide shader in GLBenchmark 2.7 dropped from 2291.67 Gcycles to a mere 5.13 Gcycles. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-03-28 06:19:39 +00:00
break;
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
default:
i965: Remove duplicate brw_opcodes table in favor of opcode_descs. brw_optimize.c's brw_opcodes table was a copy of brw_disasm.c's opcode_descs table, but with an additional field: is_arith. Now that I've deleted that, the two are identical. Keep the one in brw_disasm.c. Reviewed-by: Eric Anholt <eric@anholt.net>
2012-11-14 22:24:31 +00:00
if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
_mesa_problem(ctx, "Unsupported opcode `%s' in FS",
i965: Remove duplicate brw_opcodes table in favor of opcode_descs. brw_optimize.c's brw_opcodes table was a copy of brw_disasm.c's opcode_descs table, but with an additional field: is_arith. Now that I've deleted that, the two are identical. Keep the one in brw_disasm.c. Reviewed-by: Eric Anholt <eric@anholt.net>
2012-11-14 22:24:31 +00:00
opcode_descs[inst->opcode].name);
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
} else {
_mesa_problem(ctx, "Unsupported opcode %d in FS", inst->opcode);
}
i965/fs: Abort on unsupported opcodes rather than failing. Final code generation should never fail. This is a bug, and there should be no user-triggerable cases where this could occur. Also, we're not going to have a fail() method in a moment. v2: Just abort() rather than assert, to cover the NDEBUG case (suggested by Eric). Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-11-21 01:02:23 +00:00
abort();
i965/fs: Add SHADER_OPCODE_LOAD_PAYLOAD. Will be used to simplify the handling of large virtual GRFs in SSA form. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-05-28 02:47:40 +01:00
case SHADER_OPCODE_LOAD_PAYLOAD:
assert(!"Should be lowered by lower_load_payload()");
break;
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
}
i965: Don't use brw_set_conditionalmod in the FS and vec4 compilers. brw_set_conditionalmod and brw_next_insn work together to set the conditional modifier for the next instruction, then turn it off. The Gen8+ generators don't implement this: we just set it for all future instructions, and whack it for each fs_inst/vec4_instruction. Both approaches work out because we only set conditional_mod on IR instructions like CMP, AND, and so on, which correspond to exactly one assembly instruction. The Gen8 generators would break if we had an IR instruction that generated multiple instructions, and the Gen4-7 EU emit layer would do...something. To safeguard against this, assert that we only generated one instruction if conditional_mod is set, and just set the flag directly on that instruction rather than altering default state. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-05-31 00:41:32 +01:00
i965/fs: Add no_dd_{clear,check} fields to fs_inst. And plumb them through. Also make the assert in the generator look like the vec4 one. Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2014-06-29 07:31:04 +01:00
if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
assert(p->next_insn_offset == last_insn_offset + 16 ||
!"conditional_mod, no_dd_check, or no_dd_clear set for IR "
"emitting more than 1 instruction");
i965: Replace 'struct brw_instruction' with 'brw_inst'. Use this an an opportunity to clean up the formatting of some old code (brw_ADD, for instance). Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-06-13 22:29:25 +01:00
brw_inst *last = &p->store[last_insn_offset / 16];
i965/fs: Add no_dd_{clear,check} fields to fs_inst. And plumb them through. Also make the assert in the generator look like the vec4 one. Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2014-06-29 07:31:04 +01:00
i965: Convert fs_generator to the new brw_inst API. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-08 06:44:24 +01:00
brw_inst_set_cond_modifier(brw, last, inst->conditional_mod);
i965/fs: Add no_dd_{clear,check} fields to fs_inst. And plumb them through. Also make the assert in the generator look like the vec4 one. Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2014-06-29 07:31:04 +01:00
brw_inst_set_no_dd_clear(brw, last, inst->no_dd_clear);
brw_inst_set_no_dd_check(brw, last, inst->no_dd_check);
i965: Don't use brw_set_conditionalmod in the FS and vec4 compilers. brw_set_conditionalmod and brw_next_insn work together to set the conditional modifier for the next instruction, then turn it off. The Gen8+ generators don't implement this: we just set it for all future instructions, and whack it for each fs_inst/vec4_instruction. Both approaches work out because we only set conditional_mod on IR instructions like CMP, AND, and so on, which correspond to exactly one assembly instruction. The Gen8 generators would break if we had an IR instruction that generated multiple instructions, and the Gen4-7 EU emit layer would do...something. To safeguard against this, assert that we only generated one instruction if conditional_mod is set, and just set the flag directly on that instruction rather than altering default state. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-05-31 00:41:32 +01:00
}
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
}
brw_set_uip_jip(p);
i965: Move annotation info into generate code. Suggested by Ken as a way to cut down lines of code. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-25 18:42:32 +01:00
annotation_finalize(&annotation, p->next_insn_offset);
i965: Emit compaction stats without walking the assembly. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-25 22:56:41 +01:00
int before_size = p->next_insn_offset - start_offset;
i965: Move annotation info into generate code. Suggested by Ken as a way to cut down lines of code. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-25 18:42:32 +01:00
brw_compact_instructions(p, start_offset, annotation.ann_count,
annotation.ann);
i965: Emit compaction stats without walking the assembly. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-25 22:56:41 +01:00
int after_size = p->next_insn_offset - start_offset;
i965: Move annotation info into generate code. Suggested by Ken as a way to cut down lines of code. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-25 18:42:32 +01:00
if (unlikely(debug_flag)) {
i965: Move program header printing to end of generate_code(). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-25 18:46:55 +01:00
if (prog) {
fprintf(stderr,
"Native code for %s fragment shader %d (SIMD%d dispatch):\n",
prog->Label ? prog->Label : "unnamed",
prog->Name, dispatch_width);
} else if (fp) {
fprintf(stderr,
"Native code for fragment program %d (SIMD%d dispatch):\n",
fp->Base.Id, dispatch_width);
} else {
fprintf(stderr, "Native code for blorp program (SIMD%d dispatch):\n",
dispatch_width);
}
i965: Emit compaction stats without walking the assembly. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-25 22:56:41 +01:00
fprintf(stderr, "SIMD%d shader: %d instructions. Compacted %d to %d"
" bytes (%.0f%%)\n",
dispatch_width, before_size / 16, before_size, after_size,
100.0f * (before_size - after_size) / before_size);
i965: Move program header printing to end of generate_code(). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-25 18:46:55 +01:00
i965: Move annotation info into generate code. Suggested by Ken as a way to cut down lines of code. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-25 18:42:32 +01:00
const struct gl_program *prog = fp ? &fp->Base : NULL;
i965/disasm: Stop using gen8_disassemble in favor of brw_disassemble. At this point, brw_disassemble can do everything gen8_disassemble can do - and, thanks to the new brw_inst API, it supports all generations. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2014-06-29 04:37:56 +01:00
dump_assembly(p->store, annotation.ann_count, annotation.ann, brw, prog);
i965: Move annotation info into generate code. Suggested by Ken as a way to cut down lines of code. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-25 18:42:32 +01:00
ralloc_free(annotation.ann);
}
i965/fs: Split the BRW native code emit to brw_fs_emit.cpp This is all separate from the visitor and the optimization passes which feed into it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-05-25 00:34:27 +01:00
}
i965/fs: Split final assembly code generation out of fs_visitor. Compiling shaders requires several main steps: 1. Generating FS IR from either GLSL IR or Mesa IR 2. Optimizing the IR 3. Register allocation 4. Generating assembly code This patch splits out step 4 into a separate class named "fs_generator." There are several reasons for doing so: 1. Future hardware has a different instruction encoding. Splitting this out will allow us to replace fs_generator (which relies heavily on the brw_eu_emit.c code and struct brw_instruction) with a new code generator that writes the new format. 2. It reduces the size of the fs_visitor monolith. (Arguably, a lot more should be split out, but that's left for "future work.") 3. Separate namespaces allow us to make helper functions for generating instructions in both classes: ADD() can exist in fs_visitor and create IR, while ADD() in fs_generator() can create brw_instructions. (Patches for this upcoming.) Furthermore, this patch changes the order of operations slightly. Rather than doing steps 1-4 for SIMD8, then 1-4 for SIMD16, we now: - Do steps 1-3 for SIMD8, then repeat 1-3 for SIMD16 - Generate final assembly code for both modes together This is because the frontend work can be done independently, but final assembly generation needs to pack both into a single program store to feed the GPU. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-11-09 09:05:47 +00:00
const unsigned *
fs_generator::generate_assembly(exec_list *simd8_instructions,
exec_list *simd16_instructions,
i965/fs+blorp: Remove left over dump_file arguments. Were used by the blorp unit test programs. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
2014-05-17 21:25:15 +01:00
unsigned *assembly_size)
i965/fs: Split final assembly code generation out of fs_visitor. Compiling shaders requires several main steps: 1. Generating FS IR from either GLSL IR or Mesa IR 2. Optimizing the IR 3. Register allocation 4. Generating assembly code This patch splits out step 4 into a separate class named "fs_generator." There are several reasons for doing so: 1. Future hardware has a different instruction encoding. Splitting this out will allow us to replace fs_generator (which relies heavily on the brw_eu_emit.c code and struct brw_instruction) with a new code generator that writes the new format. 2. It reduces the size of the fs_visitor monolith. (Arguably, a lot more should be split out, but that's left for "future work.") 3. Separate namespaces allow us to make helper functions for generating instructions in both classes: ADD() can exist in fs_visitor and create IR, while ADD() in fs_generator() can create brw_instructions. (Patches for this upcoming.) Furthermore, this patch changes the order of operations slightly. Rather than doing steps 1-4 for SIMD8, then 1-4 for SIMD16, we now: - Do steps 1-3 for SIMD8, then repeat 1-3 for SIMD16 - Generate final assembly code for both modes together This is because the frontend work can be done independently, but final assembly generation needs to pack both into a single program store to feed the GPU. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-11-09 09:05:47 +00:00
{
i965/fs: generate fs programs also without any 8-width instructions Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2013-11-27 12:32:41 +00:00
assert(simd8_instructions || simd16_instructions);
if (simd8_instructions) {
dispatch_width = 8;
i965: Move annotation info into generate code. Suggested by Ken as a way to cut down lines of code. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-25 18:42:32 +01:00
generate_code(simd8_instructions);
i965/fs: generate fs programs also without any 8-width instructions Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2013-11-27 12:32:41 +00:00
}
i965/fs: Split final assembly code generation out of fs_visitor. Compiling shaders requires several main steps: 1. Generating FS IR from either GLSL IR or Mesa IR 2. Optimizing the IR 3. Register allocation 4. Generating assembly code This patch splits out step 4 into a separate class named "fs_generator." There are several reasons for doing so: 1. Future hardware has a different instruction encoding. Splitting this out will allow us to replace fs_generator (which relies heavily on the brw_eu_emit.c code and struct brw_instruction) with a new code generator that writes the new format. 2. It reduces the size of the fs_visitor monolith. (Arguably, a lot more should be split out, but that's left for "future work.") 3. Separate namespaces allow us to make helper functions for generating instructions in both classes: ADD() can exist in fs_visitor and create IR, while ADD() in fs_generator() can create brw_instructions. (Patches for this upcoming.) Furthermore, this patch changes the order of operations slightly. Rather than doing steps 1-4 for SIMD8, then 1-4 for SIMD16, we now: - Do steps 1-3 for SIMD8, then repeat 1-3 for SIMD16 - Generate final assembly code for both modes together This is because the frontend work can be done independently, but final assembly generation needs to pack both into a single program store to feed the GPU. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-11-09 09:05:47 +00:00
if (simd16_instructions) {
/* align to 64 byte boundary. */
i965/fs: Use next_insn_offset rather than nr_insn. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-18 19:16:26 +01:00
while (p->next_insn_offset % 64) {
i965/fs: Split final assembly code generation out of fs_visitor. Compiling shaders requires several main steps: 1. Generating FS IR from either GLSL IR or Mesa IR 2. Optimizing the IR 3. Register allocation 4. Generating assembly code This patch splits out step 4 into a separate class named "fs_generator." There are several reasons for doing so: 1. Future hardware has a different instruction encoding. Splitting this out will allow us to replace fs_generator (which relies heavily on the brw_eu_emit.c code and struct brw_instruction) with a new code generator that writes the new format. 2. It reduces the size of the fs_visitor monolith. (Arguably, a lot more should be split out, but that's left for "future work.") 3. Separate namespaces allow us to make helper functions for generating instructions in both classes: ADD() can exist in fs_visitor and create IR, while ADD() in fs_generator() can create brw_instructions. (Patches for this upcoming.) Furthermore, this patch changes the order of operations slightly. Rather than doing steps 1-4 for SIMD8, then 1-4 for SIMD16, we now: - Do steps 1-3 for SIMD8, then repeat 1-3 for SIMD16 - Generate final assembly code for both modes together This is because the frontend work can be done independently, but final assembly generation needs to pack both into a single program store to feed the GPU. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-11-09 09:05:47 +00:00
brw_NOP(p);
}
i965: Replace 8-wide and 16-wide with SIMD8 and SIMD16. Those are the terms used in the docs, and think "n-wide" was something I just happened to say. Note that shader-db needs updating for the INTEL_DEBUG=fs parsing. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-11-12 23:33:27 +00:00
/* Save off the start of this SIMD16 program */
i965/fs: Use next_insn_offset rather than nr_insn. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-18 19:16:26 +01:00
prog_data->prog_offset_16 = p->next_insn_offset;
i965/fs: Split final assembly code generation out of fs_visitor. Compiling shaders requires several main steps: 1. Generating FS IR from either GLSL IR or Mesa IR 2. Optimizing the IR 3. Register allocation 4. Generating assembly code This patch splits out step 4 into a separate class named "fs_generator." There are several reasons for doing so: 1. Future hardware has a different instruction encoding. Splitting this out will allow us to replace fs_generator (which relies heavily on the brw_eu_emit.c code and struct brw_instruction) with a new code generator that writes the new format. 2. It reduces the size of the fs_visitor monolith. (Arguably, a lot more should be split out, but that's left for "future work.") 3. Separate namespaces allow us to make helper functions for generating instructions in both classes: ADD() can exist in fs_visitor and create IR, while ADD() in fs_generator() can create brw_instructions. (Patches for this upcoming.) Furthermore, this patch changes the order of operations slightly. Rather than doing steps 1-4 for SIMD8, then 1-4 for SIMD16, we now: - Do steps 1-3 for SIMD8, then repeat 1-3 for SIMD16 - Generate final assembly code for both modes together This is because the frontend work can be done independently, but final assembly generation needs to pack both into a single program store to feed the GPU. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-11-09 09:05:47 +00:00
i965: Put '_default_' in the name of functions that set default state. Eventually we're going to use functions to set bits on an instruction. Putting 'default' in the name of functions that alter default state will help distinguins them. This patch was generated entirely mechanically, by the following: for file in brw*.{cpp,c,h}; do sed -i \ -e 's/brw_set_mask_control/brw_set_default_mask_control/g' \ -e 's/brw_set_saturate/brw_set_default_saturate/g' \ -e 's/brw_set_access_mode/brw_set_default_access_mode/g' \ -e 's/brw_set_compression_control/brw_set_default_compression_control/g' \ -e 's/brw_set_predicate_control/brw_set_default_predicate_control/g' \ -e 's/brw_set_predicate_inverse/brw_set_default_predicate_inverse/g' \ -e 's/brw_set_flag_reg/brw_set_default_flag_reg/g' \ -e 's/brw_set_acc_write_control/brw_set_default_acc_write_control/g' \ $file; done No manual changes were done after running that command. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-06-01 00:57:02 +01:00
brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
i965/fs: Split final assembly code generation out of fs_visitor. Compiling shaders requires several main steps: 1. Generating FS IR from either GLSL IR or Mesa IR 2. Optimizing the IR 3. Register allocation 4. Generating assembly code This patch splits out step 4 into a separate class named "fs_generator." There are several reasons for doing so: 1. Future hardware has a different instruction encoding. Splitting this out will allow us to replace fs_generator (which relies heavily on the brw_eu_emit.c code and struct brw_instruction) with a new code generator that writes the new format. 2. It reduces the size of the fs_visitor monolith. (Arguably, a lot more should be split out, but that's left for "future work.") 3. Separate namespaces allow us to make helper functions for generating instructions in both classes: ADD() can exist in fs_visitor and create IR, while ADD() in fs_generator() can create brw_instructions. (Patches for this upcoming.) Furthermore, this patch changes the order of operations slightly. Rather than doing steps 1-4 for SIMD8, then 1-4 for SIMD16, we now: - Do steps 1-3 for SIMD8, then repeat 1-3 for SIMD16 - Generate final assembly code for both modes together This is because the frontend work can be done independently, but final assembly generation needs to pack both into a single program store to feed the GPU. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-11-09 09:05:47 +00:00
dispatch_width = 16;
i965: Move annotation info into generate code. Suggested by Ken as a way to cut down lines of code. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-25 18:42:32 +01:00
generate_code(simd16_instructions);
i965/fs: Split final assembly code generation out of fs_visitor. Compiling shaders requires several main steps: 1. Generating FS IR from either GLSL IR or Mesa IR 2. Optimizing the IR 3. Register allocation 4. Generating assembly code This patch splits out step 4 into a separate class named "fs_generator." There are several reasons for doing so: 1. Future hardware has a different instruction encoding. Splitting this out will allow us to replace fs_generator (which relies heavily on the brw_eu_emit.c code and struct brw_instruction) with a new code generator that writes the new format. 2. It reduces the size of the fs_visitor monolith. (Arguably, a lot more should be split out, but that's left for "future work.") 3. Separate namespaces allow us to make helper functions for generating instructions in both classes: ADD() can exist in fs_visitor and create IR, while ADD() in fs_generator() can create brw_instructions. (Patches for this upcoming.) Furthermore, this patch changes the order of operations slightly. Rather than doing steps 1-4 for SIMD8, then 1-4 for SIMD16, we now: - Do steps 1-3 for SIMD8, then repeat 1-3 for SIMD16 - Generate final assembly code for both modes together This is because the frontend work can be done independently, but final assembly generation needs to pack both into a single program store to feed the GPU. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-11-09 09:05:47 +00:00
}
return brw_get_program(p, assembly_size);
}