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i965/fs: Use the instruction execution size directly for texture generation 

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
This commit is contained in:
Jason Ekstrand 2014-08-29 17:22:57 -07:00
parent 48ddd2889e
commit 30d718c2fb
1 changed files with 10 additions and 3 deletions
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13
src/mesa/drivers/dri/i965/brw_fs_generator.cpp
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@ -388,7 +388,7 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src
{
int msg_type = -1;
int rlen = 4;
uint32_t simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
uint32_t simd_mode;
uint32_t return_format;
switch (dst.type) {
@ -403,9 +403,16 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src
break;
}
if (dispatch_width == 16 &&
!inst->force_uncompressed && !inst->force_sechalf)
switch (inst->exec_size) {
case 8:
simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
break;
case 16:
simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
break;
default:
unreachable("Invalid width for texture instruction");
}
if (brw->gen >= 5) {
switch (inst->opcode) {