Commit Graph

97180 Commits

Author SHA1 Message Date
Dave Airlie 16cfbef44c ac/llvm: drop pointless wrappers around umsb/imsb
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-10-26 15:59:34 +10:00
Dave Airlie 82d47b9d38 ac/llvm: consolidate find lsb function.
This was the same between si and ac.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-10-26 15:59:31 +10:00
Dave Airlie de2b241111 ac/llvm: drop v4f32empty. (v2)
This was unused.

v2: drop args.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-10-26 15:59:22 +10:00
Dave Airlie a76b6c2192 ac/llvm: add i1false/i1true to common code.
These get used in fair few places.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-10-26 15:59:18 +10:00
Dave Airlie 88b7ddbe65 ac/llvm: use the ac i32 0/1 and f32 0/1 llvm types.
This just avoids having two copies of these.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-10-26 15:59:13 +10:00
Dave Airlie f925f5b074 ac/nir: move lds declaration/load/store into shared code.
This was duplicated between both drivers, share here.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-10-26 15:59:11 +10:00
Dave Airlie 74fc9e9186 st/mesa: enable nir path for all shaders.
There is no reason to block this here, if a driver enables
it, let it handle it.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-10-26 00:55:59 +01:00
Dave Airlie 3ee2e98aff st/program: add support for gs/tes/tcs nir shaders.
This probably needs more work but this just add the initial
code to convert gs/tcs/tes nir based shaders in the state tracker.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-10-26 00:55:56 +01:00
Dave Airlie 3c34d11589 st/program: rework basic variant interface
This just passes st_common_program and uses it.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-10-26 00:55:52 +01:00
Jason Ekstrand 3720d913dd anv/entrypoints: Dump useful data if mako throws an exception
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-10-25 16:14:09 -07:00
Jason Ekstrand e0519294c7 nir/opt_intrinsics: Rework progress
This commit fixes two issues:  First, we were returning false regardless
of whether or not the function made progress.  Second, we were calling
nir_metadata_preserve far more often than needed; we only need to call
it once per impl.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-10-25 16:14:09 -07:00
Jason Ekstrand d24311b7b5 intel/compiler: Call nir_lower_system_values in brw_preprocess_nir
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-10-25 16:14:09 -07:00
Jason Ekstrand ece206b848 i965/program: Move nir_lower_system_values higher up
We want this to get called before nir_lower_subgroups which is going in
brw_preprocess_nir.  Now that nir_lower_wpos_ytransform can handle
system values, this should be safe to do.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-10-25 16:14:09 -07:00
Jason Ekstrand 2cfa3ef438 nir/lower_wpos_ytransform: Support system value intrinsics
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-10-25 16:14:09 -07:00
Jason Ekstrand 279f8fb69c anv/pipeline: Call nir_lower_system_valaues after brw_preprocess_nir
We currently have a bug where nir_lower_system_values gets called before
nir_lower_var_copies so it will miss any system value uses which come
from a copy_var intrinsic.  Moving it to after brw_preprocess_nir fixes
this problem.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable@lists.freedesktop.org
2017-10-25 16:14:09 -07:00
Jason Ekstrand afa0ddb81e anv/pipeline: Drop nir_lower_clip_cull_distance_arrays
We already handle it in brw_preprocess_nir

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-10-25 16:14:09 -07:00
Jason Ekstrand e758b6519d anv/pipeline: Dump shader immedately after spirv_to_nir
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-10-25 16:14:09 -07:00
Jason Ekstrand 562b8d458c intel/eu: Use EXECUTE_1 for JMPI
The PRM says "The execution size must be 1."  In 73137997e2, the
execution size was set to 1 when it should have been BRW_EXECUTE_1
(which maps to 0).  Later, in dc2d3a7f5c, JMPI was used for
line AA on gen6 and earlier and we started manually stomping the
exeution size to BRW_EXECUTE_1 in the generator.  This commit fixes the
original bug and makes brw_JMPI just do the right thing.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Fixes: 73137997e2
2017-10-25 16:14:09 -07:00
Alejandro Piñeiro 4723933b8e i965/fs: Add brw_reg_type_from_bit_size utility method
Returns the brw_type for a given ssa.bit_size, and a reference type.
So if bit_size is 64, and the reference type is BRW_REGISTER_TYPE_F,
it returns BRW_REGISTER_TYPE_DF. The same applies if bit_size is 32
and reference type is BRW_REGISTER_TYPE_HF it returns BRW_REGISTER_TYPE_F

v2 (Jason Ekstrand):
 - Use better unreachable() messages
 - Add Q types

Signed-off-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Signed-off-by: Alejandro Piñeiro <apinheiro@igalia.com
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-10-25 16:14:09 -07:00
Jason Ekstrand 99778e7f9f i965/fs/nir: Use the nir_src_bit_size helper
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-10-25 16:14:09 -07:00
Jason Ekstrand fa6e74e33e intel/fs: Handle flag read/write aliasing in needs_src_copy
In order to implement the ballot intrinsic, we do a MOV from flag
register to some GRF.  If that GRF is used in a SEL, cmod propagation
helpfully changes it into a MOV from the flag register with a cmod.
This is perfectly valid but when lower_simd_width comes along, it simply
splits into two instructions which both have conditional modifiers.
This is a problem since we're reading the flag register.  This commit
makes us check whether or not flags_written() overlaps with the flag
values that we are reading via the instruction source and, if we have
any interference, will force us to emit a copy of the source.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
2017-10-25 16:14:09 -07:00
Jan Vesely a6d38f476b clover: Fix compilation after clang r315871
v2: use a more generic compat function
v3: rename and formatting cleanup

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103388
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
CC: <mesa-stable@lists.freedesktop.org>
2017-10-25 18:57:42 -04:00
Marek Olšák b85cd69415 glsl_to_tgsi: remove unused glsl_version variable
trivial
2017-10-26 00:43:31 +02:00
Bas Nieuwenhuizen 61a9ef4ab1 radv: Compute ac keys from pipeline key.
The beginning of the end for the shader keys. Not entirely sure
what I'm going to replace them with for the compiler though, so this
is the first step.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-10-26 00:28:40 +02:00
Bas Nieuwenhuizen 49d035122e radv: Add single pipeline cache key.
To decouple the key used for info gathering and the cache from
whatever we pass to the compiler.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-10-26 00:28:40 +02:00
Bas Nieuwenhuizen de38491a57 radv: Don't compute as_ls/as_es before hashing.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-10-26 00:28:40 +02:00
Jordan Justen 87e71726e0 glsl_to_nir: Zero nir_constant in constant_copy for valgrind & nir_serialize
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-10-25 12:36:21 -07:00
Jordan Justen 16867154d8 glsl_to_nir: Zero nir_variable struct for valgrind & nir_serialize
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-10-25 12:36:21 -07:00
Jordan Justen 78550869a1 nir: Zero nir_load_const_instr::value for valgrind & nir_serialize
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-10-25 12:36:21 -07:00
Jordan Justen b35e8c3b86 intel/nir: Zero local index const struct for valgrind & nir_serialize
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-10-25 12:36:21 -07:00
Jordan Justen d917f57c2f nir: Zero local_size const struct for valgrind & nir_serialize
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-10-25 12:36:21 -07:00
Jordan Justen abbcdc9b69 glsl: Add field initializers for glsl_struct_field default constructor
This helps valgrind when encode_type_to_blob is used.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-10-25 12:36:21 -07:00
Jason Ekstrand 23327af91c compiler/types: Support [de]serializing void types
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2017-10-25 12:36:21 -07:00
Jason Ekstrand c1b84256cc nir/intrinsics: Set the correct num_indices for load_output
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2017-10-25 12:36:20 -07:00
Connor Abbott 7686f0b316 glsl: move shader_cache type handling to glsl_types
Not sure if this is the best place to put it, but we're going to need
this for NIR too.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-10-25 12:36:20 -07:00
Alex Smith 9626128f32 vulkan: Update headers and registry to 1.0.64
Acked-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Alex Smith <asmith@feralinteractive.com>
2017-10-26 05:17:57 +10:00
Matthew Nicholls 27a0b24bf2 ac/nir: generate correct instruction for atomic min/max on unsigned images
v2: fix silly typo

Cc: "17.2 17.3" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-25 20:52:58 +02:00
Roland Scheidegger 20c77ae639 gallium/util: remove some block alignment assertions
These assertions were revisited a couple of times in the past, and they
still weren't quite right.
The problem I was seeing (with some other state tracker) was a copy between
two 512x512 s3tc textures, but from mip level 0 to mip level 8. Therefore,
the destination has only size 2x2 (not a full block), so the box width/height
was only 2, causing the assertion to trigger for src alignment.
As far as I can tell, such a copy is completely legal, and because a correct
assertion would get ridiculously complicated just get rid of it for good.

Reviewed-by: Brian Paul <brianp@vmware.com>
2017-10-25 19:52:24 +02:00
Eric Engestrom 7983adc60f meson: be explicit about the version required
This way, we know what we're allowed to use (no nested include lists
for instance) and users get immediate feedback when trying to use
unsupported versions, rather than a cryptic crash or things being
silently not built correctly.

Cc: Dylan Baker <dylan@pnwbakers.com>
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2017-10-25 14:05:56 +01:00
Erik Faye-Lund 9e5a5a11ed meson: add opt-out of libunwind
Libunwind has some issues on some platforms, so let's allow people
who have issues to opt-out. This is similar to what we do in automake,
and the implementation is modelled after our opt-out for valgrind.

Signed-off-by: Erik Faye-Lund <kusmabite@gmail.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2017-10-25 14:05:24 +02:00
Harish Krupo d37bcf3cc2 gles2: support for GL_EXT_occlusion_query_boolean
Following test checking entrypoints passes:
   dEQP-EGL.functional.get_proc_address.extension.gl_ext_occlusion_query_boolean

Piglit test 'ext_occlusion_query_boolean-any-samples' passes with these changes.

No changes/regression observed in WebGL occlusion tests or Intel CI.

v2: add es2="2.0" for glapi entrypoints, clean up xml
    dispatch_sanity changes (fix 'make check')

Signed-off-by: Harish Krupo <harish.krupo.kps@intel.com>
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2017-10-25 14:10:38 +03:00
Tapani Pälli f5bec8583a mesa: enum checks for GL_EXT_occlusion_query_boolean
Some of the checks are valid for generic ES 3.2 as well.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2017-10-25 14:10:38 +03:00
Samuel Pitoiset 9711979df0 radv: print NIR before LLVM IR and disassembly
It's still printed after linking, but it makes more sense to
have SPIRV->NIR->LLVM IR->ASM.

Fixes: f0a2bbd1a4 (radv: move nir print after linking is done)
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-25 11:46:53 +02:00
Bas Nieuwenhuizen 5bfbab2fdc radv: Fix truncation issue hexifying the cache uuid for the disk cache.
Going from binary to hex has a 2x blowup.

Fixes: 1421625292 'radv: create on-disk shader cache'
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-10-25 09:50:05 +02:00
Timothy Arceri 767ca5bdf1 radv: enable lower to scalar nir pass
This will allow dead components of varyings to be removed.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-25 17:02:40 +11:00
Timothy Arceri 8ebaf8192a ac: add support for explicit component packing
This is needed for RADV to support explicit component packing.

This is also required to use the new NIR component splitting /
packing passes.

V2:
 - add commponent packing support for interpolate_at* intrinsics
 - improve store packing support when not all varyings are scalar
   as spotted by Bas the store source was incorrectly offset.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-25 17:02:40 +11:00
Timothy Arceri e0e0666584 i965: fix unused var warnings in release build
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2017-10-25 14:26:39 +11:00
Dave Airlie d8cefaa197 radv: use device name in cache creation like radeonsi.
Not sure how useful this is, but it makes it more consistent.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.3" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-10-25 02:26:01 +01:00
Dave Airlie 3cd3035ace radv: use a define for the transition point between cp and compute shader
For certain buffer meta ops we can use the CP or a compute shader,
we should use a define to rather than hardcoding 4096, allows
for easier testing and more consistency.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-10-25 10:01:13 +10:00
Kenneth Graunke b704538b00 docs: Mark GL_KHR_no_error as done.
Drivers have supported KHR_no_error for a while.  We'd been leaving it
marked as "in progress" because there's a zillion places that could get
slightly more optimized.  But, Timothy and Samuel have already done
piles of work, and I think we have a solid implementation at this point.

Let's check it off the list.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2017-10-24 16:56:58 -07:00