This is done in autotools, and is an oversight in the meson build.
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Tested-by: Eric Engestrom <eric.engestrom@imgtec.com>
It's supposed to be linked with pthread-stubs (if the platform needs
pthread-stubs). Pthread stubs support isn't (yet) implemented in the
meson build, so add a TODO.
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
This allows a user to not care whether they're setting a tristate or a
boolean option, which is a nice user facing feature, and something I've
personally run into.
Suggested-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
If we don't want to use these deps, there's no good reason to search
for them in the first place. This should shave a bit of time for the
initial build.
Signed-off-by: Erik Faye-Lund <kusmabite@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
The u_format_other.c users sqrtf, which on some systems require
a math-library. So let's make sure we link with it.
Signed-off-by: Erik Faye-Lund <kusmabite@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Fixes regression in:
dEQP-VK.api.object_management.alloc_callback_fail.graphics_pipeline
Fixes: 1e84e53712 "radv: add cache items to in memory cache when reading from disk"
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This patch modifies the ARB_indirect_parameters logic in
brw_draw_prims, so that our implementation isn't affected if
another application attempts to use predicates. Previously we
were using a predicate with a DELTAS_EQUAL comparison operation
and relying on the MI_PREDICATE_DATA register being 0. Our code
to initialize MI_PREDICATE_DATA to 0 was incorrect, so we were
accidentally using whatever value was written there. Because the
kernel does not initialize the MI_PREDICATE_DATA register on
hardware context creation, we might inherit the value from whatever
context was last running on the GPU (likely another process).
The Haswell command parser also does not currently allow us to write
the MI_PREDICATE_DATA register. Rather than fixing this and requiring
an updated kernel, we switch to a different approach which uses a
SRCS_EQUAL predicate that makes no assumptions about the states of any
of the predicate registers.
Fixes Piglit's spec/arb_indirect_parameters/tf-count-arrays test.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103085
Signed-off-by: Plamena Manolova <plamena.manolova@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Due to a gaffe on my part, we were re-emitting all binding table entries
on every single draw call. The push_constant_packets atom listens to
BRW_NEW_DRAW_CALL, but skips emitting 3DSTATE_CONSTANT_XS for each stage
unless stage_state->push_constants_dirty is true. However, it flagged
BRW_NEW_SURFACES unconditionally at the end, by mistake.
Instead, it should only flag it if we actually emit 3DSTATE_CONSTANT_XS
for a stage. We can move it a few lines up, inside the loop - the early
continues will skip over it if push constants aren't dirty for a stage.
With INTEL_NO_HW=1 set, improves performance of GFXBench5 gl_driver_2
on Apollolake at 1280x720 by 1.01122% +/- 0.470723% (n=35).
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Groups containing fields smaller than a DWord were not being decoded
correctly. For example:
<group count="32" start="32" size="4">
<field name="Vertex Element Enables" start="0" end="3" type="uint"/>
</group>
gen_field_iterator_next would properly walk over each element of the
array, incrementing group_iter, and calling iter_group_offset_bits()
to advance to the proper DWord. However, the code to print the actual
values only considered iter->field->start/end, which are 0 and 3 in the
above example. So it would always fetch bits 3:0 of the current DWord
when printing values, instead of advancing to each element of the array,
printing bits 0-3, 4-7, 8-11, and so on.
To fix this, we add new iter->start/end tracking, which properly
advances for each instance of a group's field.
Caught by Matt Turner while working on 3DSTATE_VF_COMPONENT_PACKING,
with a patch to convert it to use an array of bitfields (the example
above).
This also fixes the decoding of 3DSTATE_SBE's "Attribute Active
Component Format" fields.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Fixes fbo-blending-formats on RGB8 and 565. We will still need to demote
blending to shader code in the MRT case to fix it in general, but that can
be added when we start doing 32F blending (which also needs to be done in
the shader).
The previous packing I did got us all the R*16F and R*32F formats, where
the pipe format basically matched the TLB's format, but since the clear
color will just be memcpyed to the TLB, we should be looking at its format
for deciding how to pack.
Fixes RGB565, RGB5_A1 and RGBA10 fbo-clear-formats tests and improves
4444.
The output formats are consistent with their channels appearing from low
to high in their name. Textures are interpreted the same way, but their
names may have the channels swapped around. I'm retaining the texture
names so that we are consistent with the documentation, but I want to
leave a warning for others.
In the case of fneg(0.0), we were getting back 0.0 instead of -0.0. We
were also needing an immediate 0 value for ineg, when there's an opcode to
do the job properly.
Fixes fs-floatBitsToInt-neg.shader_test.
We were storing the resolved pixels in all cases, but nr_samples > 0 means
we should be keeping the per-sample values.
We will probably want to change the job structure at some point, as we'll
want to recognize full-buffer resolves and do the resolved store in the
same job as the original rendering, meaning we'll need to track both the
MSAA and single-sample resources in the job. However, this will be enough
to build the rest of the MSAA support.
The HW has no native sampler support for multisample textures, but since
we only need to support txf_ms and the layout is UIF, we just need to
scale up the texcoords and then add in the sample.
This drops the old TEXTURE_MSAA_ADDR special uniform, since we're treating
MSAA textures as textures, rather than basically texbos like VC4 had to.
We just need to multiply width/height by 2 each, and always set them up as
UIF tiling, since that's how the TLB will store them in raw (per-sample)
mode.
We were handing the intra-byte padding fine, but with a 24-bit address
(bottom 8 bits implied 0) we would end up off by 8 bytes in our shift,
impacting vc5's load/store general packets (all other packets we have had
<8 bits of padding).
We only have 2x16 unpacking in our ALUs. To enable this, we also need
lower_fdiv for its new instructions, which had been handled at a higher
level previously.
I already had the texture's wrapping set up to use different behavior for
nearest or linear, so we just needed to saturate the coordinates in linear
mode to get the "proper" blend between the edge and border values.
1D is the exception to "all V3D textures are tiled", since tiling 1D
textures would just waste memory and cache space. This ended up being a
problem once we started actually marking 1D textures as 1D instead of 2D.
Like VC4, we need to at least have one element set up, but unlike VC4 it
seems we don't need to read it to keep the HW happy. Fixes GPU hangs with
glsl-no-vertex-attribs.shader_test.
Eric Engestrom
Dylan Baker
Andrey Grodzovsky
Erik Faye-Lund
Samuel Pitoiset
Timothy Arceri
Plamena Manolova
Kenneth Graunke
Ian Romanick
Eric Anholt