Commit Graph

9687 Commits

Author SHA1 Message Date
Rhys Perry fc39c3a0b1 aco: don't use opsel to fold constants into dot accumulation sources
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16296>
2022-07-05 16:39:56 +00:00
Rhys Perry ae74474509 aco: fix propagate_constants_vop3p with integer vop3p and 16-bit constants
This would have created a 1.0.xx operand from 0x3c00.xx or 0x3c003c00.xy
for vop3p instructions which have 32-bit operands.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16296>
2022-07-05 16:39:56 +00:00
Rhys Perry 9739c07d9e aco: fix single-alignbyte do_pack_2x16() path with fp inline constants
We were using a 16-bit inline constant with a 32-bit instruction and the
test would have created
"v1: %_:v[0] = v_alignbyte_b32 0.5, %_:v[1][16:32], 2" instead.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16296>
2022-07-05 16:39:56 +00:00
Rhys Perry 5d8f5615d0 aco: ignore precise flag when optimizing integer clamps
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16296>
2022-07-05 16:39:56 +00:00
Rhys Perry 61eb632775 aco: include _e64 variants of 16-bit min/max in minmax optimizations
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16296>
2022-07-05 16:39:56 +00:00
Rhys Perry f2a346eb40 aco: don't accept med3 opcodes in get_minmax_info()
I don't think the presence of med3 here breaks anything, but it shouldn't
be here anyway.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16296>
2022-07-05 16:39:56 +00:00
Rhys Perry f937c5be7c aco: add and use constantValue16()
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16296>
2022-07-05 16:39:56 +00:00
Samuel Pitoiset 184ae84a0a radv: always enable VK_EXT_debug_utils
Instead of enabling it conditionally for SQTT. Other Vulkan drivers
always expose it as well.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6772
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17355>
2022-07-05 12:20:13 +02:00
Samuel Pitoiset 053312ab87 radv: disable DCC for Melty Blood Actress Again Current Code
A D3D9 game that uses feedback loops again.

See https://github.com/ValveSoftware/Proton/issues/271

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17356>
2022-07-04 16:33:14 +02:00
Samuel Pitoiset b11158cc8b radv: remove old workaround for HTILE layers with F1 2021
Turns out this was likely a vkd3d-proton issue because it can no
longer be reproduced since it switched to dynamic rendering by default.
AMDGPU-PRO was also affected by the same issue at that time.

According to Hans-Kristian, some bugs related to that have also been
fixed at the same time.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17296>
2022-07-04 11:51:36 +00:00
Samuel Pitoiset 25d5ef0450 radv: do not abort if SPM isn't supported for the current GPU
In a mixed GFX9/GFX10 setup, this would crash for the GFX9 logical
device. Just print a message intead of aborting.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17292>
2022-07-04 13:08:32 +02:00
Samuel Pitoiset 06a48e599e radv: use LOAD_CONTEXT_REG to load the opaque buffer size on GFX10+
For unknown reasons, COPY_DATA can hang on GFX10+ while it doesn't
hang on GFX9. Adding PFP_SYNC_ME before/after the COPY_DATA doesn't
fix the hang either.

Using a LOAD_CONTEXT_REG_INDEX packet shouldn't be needed unless the
driver supports preemption (shadow memory) which RADV doesn't support.

I don't have a real explanation but PFP_SYNC_ME+LOAD_CONTEXT_REG_INDEX
fixes a GPU hang with Space Engineers (game uses a bunch of consecutive
calls to vkCmdDrawIndirectByteCountEXT without anything in-between).

Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5838
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17290>
2022-07-04 08:42:53 +02:00
Samuel Pitoiset 3e90eb4463 radv/ci: add CI lists for LLVM on NAVI21
Copied and adjusted from the ACO lists.

v2: Martin Roukala
 - add an extra test in the list of timeouts
 - add an extra test in the list of flakes
 - remove a fail

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16841>
2022-07-02 13:06:49 +03:00
Martin Roukala (né Peres) c0fbc31737 radv/ci: test the llvm backend on navi21
The LLVM backend is not officially supported by the RADV developers,
but it has been useful early during bring-up, or later when users are
experiencing what looks like a compiler bug. It is thus beneficial to
keep it working.

However, maintaining the vkcts expectations for every platform requires
more work and machine time than what we would like to commit to. This
is why we agreed that we would only keep LLVM tested on the latest
family of Radeon GPUs.

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16841>
2022-07-02 12:35:51 +03:00
Timur Kristóf ff13fc381d radv: Use NIR optimization to move discards to the top.
Fossil stats on Sienna Cichlid:

Totals from 1988 (1.55% of 128653) affected shaders:
VGPRs: 68096 -> 67928 (-0.25%); split: -0.61%, +0.36%
CodeSize: 5391936 -> 5391312 (-0.01%); split: -0.11%, +0.10%
MaxWaves: 53020 -> 52946 (-0.14%); split: +0.05%, -0.19%
Instrs: 992413 -> 992509 (+0.01%); split: -0.10%, +0.11%
Latency: 8643141 -> 8789295 (+1.69%); split: -0.31%, +2.00%
InvThroughput: 1680195 -> 1680605 (+0.02%); split: -0.04%, +0.07%
SClause: 50886 -> 51318 (+0.85%); split: -0.73%, +1.57%
Copies: 57017 -> 56741 (-0.48%); split: -1.28%, +0.80%
PreSGPRs: 66766 -> 67048 (+0.42%); split: -0.24%, +0.66%
PreVGPRs: 56832 -> 56935 (+0.18%); split: -0.44%, +0.62%

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13037>
2022-07-01 18:55:53 +00:00
Timur Kristóf 5d2a243dde radv: Add CULL_PRIMITIVE to special output mask.
It isn't compiled to an output param, so can be safely ignored
from the param assignment.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17244>
2022-07-01 18:09:07 +00:00
Timur Kristóf 7144d52d59 radv: Don't assign driver locations to mesh shader outputs.
Set all driver locations to zero.
These are ignored by ac_nir_lower_ngg anyway.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17244>
2022-07-01 18:09:07 +00:00
Timur Kristóf 8bfeb467bf ac/nir/ngg: Ignore driver location for mesh shader outputs.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17244>
2022-07-01 18:09:07 +00:00
Martin Roukala (né Peres) 66bd470922 ci/radv: enable vkcts testing on kabini
It seems like the hangs have been resolved on kabini, so let's allow
developers to run their tests on kabini, if they are *very* patient
(~10h).

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17129>
2022-07-01 16:44:14 +00:00
Konstantin Seurer 6a90d3832a radv: Use two bools for ahit_status
This avoids using a VGPR and uses two SGPRs
instead since we only need to store 2 bits.

Quake II RTX:

Totals from 7 (0.46% of 1513) affected shaders:
CodeSize: 229364 -> 229148 (-0.09%); split: -0.12%, +0.02%
Instrs: 41937 -> 41879 (-0.14%)
Latency: 977374 -> 976723 (-0.07%)
InvThroughput: 651582 -> 651148 (-0.07%)
Copies: 5064 -> 5033 (-0.61%)
PreSGPRs: 430 -> 433 (+0.70%)

Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17293>
2022-07-01 14:31:49 +00:00
Dave Airlie 68642e2c26 aco: drop radv_shader.h include
This shouldn't be used anymore

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16445>
2022-07-01 01:34:19 +00:00
Dave Airlie 9fe2b6b748 aco/radv: provide a vs prolog callback from aco to radv.
Avoid building the radv binary in aco, just callback with the
necessary info.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16445>
2022-07-01 01:34:19 +00:00
Dave Airlie 2dce77c239 aco/radv: provide a callback from aco shader building to build binary
This moves the radv specific code into radv, and calls back from
aco into radv.

This should allow easier radeonsi integration later.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16445>
2022-07-01 01:34:19 +00:00
Dave Airlie e5ec50b3c7 aco: refactor the radv binary builder out of the core aco fn.
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16445>
2022-07-01 01:34:19 +00:00
Rhys Perry 93fd97cec4 radv/ci: re-enable vega10 fossils testing
Should work now.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17295>
2022-06-30 19:30:55 +00:00
Rhys Perry 84f04fd080 aco/ra: update register file when updating phi definition
update_renames() fills in the wrong temp id.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes: 302cb5c900 ("aco/ra: remove some redundant code")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17295>
2022-06-30 19:30:55 +00:00
Konstantin Seurer e83bd87ee9 radv: Use nir_test_mask instead of i2b(iand)
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17242>
2022-06-30 18:00:32 +00:00
Daniel Schürmann 3ae0c39a58 radv: reorder some NIR passes
Totals from 6171 (4.57% of 134913) affected shaders: (GFX10.3)
CodeSize: 61916968 -> 61916676 (-0.00%); split: -0.01%, +0.01%
Instrs: 11473620 -> 11473797 (+0.00%); split: -0.01%, +0.01%
Latency: 161997216 -> 161997029 (-0.00%); split: -0.00%, +0.00%
InvThroughput: 29075944 -> 29075862 (-0.00%); split: -0.00%, +0.00%
VClause: 199793 -> 199790 (-0.00%); split: -0.01%, +0.00%
SClause: 418180 -> 418013 (-0.04%)
Copies: 786921 -> 786884 (-0.00%); split: -0.06%, +0.06%
Branches: 348058 -> 348106 (+0.01%); split: -0.04%, +0.06%
PreSGPRs: 604400 -> 604396 (-0.00%)
PreVGPRs: 469415 -> 469430 (+0.00%)

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17279>
2022-06-30 16:57:38 +00:00
Daniel Schürmann 7750281b43 radv: fix swizzles after nir_opt_algebraic_late
Fixes: 2e895f8b04 ('radv: vectorize nir_op_fabs')
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17279>
2022-06-30 16:57:38 +00:00
Timur Kristóf 2ac3e921e3 ac/nir/ngg: Refactor LDS instructions in NGG GS vertex emit and export.
Change NGG GS emit vertex code to emit combined shared stores,
also change the export vertex code to emit combined shared loads.
This results in more optimal code generation, ie. fewer LDS
instructions are generated.

GS vertices are stored using an odd stride to minimize the chance
of bank conflicts, which means that unfortunately
we still can't use an alignment higher than 4 here,
so the best we can get are some ds_read2_b32 instructions.

Fossil DB stats on Navi 21 (formerly Sienna Cichlid):

Totals from 135 (0.10% of 128653) affected shaders:
VGPRs: 6416 -> 6512 (+1.50%)
CodeSize: 529436 -> 503792 (-4.84%)
MaxWaves: 2952 -> 2924 (-0.95%)
Instrs: 93384 -> 90176 (-3.44%)
Latency: 290283 -> 293611 (+1.15%); split: -0.36%, +1.50%
InvThroughput: 81218 -> 82598 (+1.70%)
Copies: 6603 -> 6606 (+0.05%)
PreVGPRs: 5037 -> 5076 (+0.77%)

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11425>
2022-06-30 18:15:50 +02:00
Samuel Pitoiset 00cc5ec5cf radv: do not emit SQTT user data packets on the SDMA queue
They aren't supported and lead to GPU hangs.

Reported-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17256>
2022-06-29 06:41:31 +00:00
Konstantin Seurer 098b5804a0 radv: Refactor lower_rt_derefs
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17123>
2022-06-29 00:33:26 +00:00
Konstantin Seurer 9196fd3e1f radv: Fix the t comparison for triangles
The accept range is defined like this:
Triangles: tmin < t < tmax
AABBs: tmin <= t <= tmax

(See https://www.khronos.org/registry/vulkan/specs/1.3-extensions/html/vkspec.html#ray-intersection-candidate-determination)

Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17123>
2022-06-29 00:33:26 +00:00
Konstantin Seurer 1ec7e51997 radv: Introduce an enum for the any hit status
Use enum values instead of magic constants.

Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17123>
2022-06-29 00:33:26 +00:00
Boris Brezillon 6a491d1628 radv: Use vk_pipeline_hash_shader_stage()
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17186>
2022-06-28 09:07:32 +00:00
Boris Brezillon d2bb3b11e5 radv: Kill unused fs_m local var in radv_create_shaders()
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17186>
2022-06-28 09:07:32 +00:00
Daniel Schürmann 2e895f8b04 radv: vectorize nir_op_fabs
Totals from 4 (0.00% of 134913) affected shaders: (GFX10.3)
CodeSize: 37868 -> 36576 (-3.41%)
Instrs: 5332 -> 5169 (-3.06%)
Latency: 24452 -> 24174 (-1.14%)
InvThroughput: 9784 -> 9462 (-3.29%)
VClause: 54 -> 50 (-7.41%)
Copies: 520 -> 519 (-0.19%)
PreVGPRs: 266 -> 264 (-0.75%)

Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15176>
2022-06-27 15:07:27 +00:00
Daniel Schürmann b45a39c44b radv: vectorize nir_op_fdiv & nir_op_flrp & nir_op_ineg
These instructions are lowered to fmul/isub.
So, prevent scalarization.

Totals from 49 (0.04% of 134913) affected shaders: (GFX10.3)
VGPRs: 2576 -> 2568 (-0.31%)
SpillVGPRs: 1145 -> 1132 (-1.14%); split: -2.10%, +0.96%
CodeSize: 663968 -> 659376 (-0.69%); split: -1.08%, +0.38%
Scratch: 113664 -> 112640 (-0.90%)
Instrs: 110274 -> 109683 (-0.54%); split: -0.81%, +0.27%
Latency: 2904434 -> 2869588 (-1.20%); split: -1.64%, +0.44%
InvThroughput: 1414237 -> 1396600 (-1.25%); split: -1.69%, +0.44%
VClause: 2899 -> 2891 (-0.28%); split: -0.93%, +0.66%
SClause: 1520 -> 1537 (+1.12%); split: -0.07%, +1.18%
Copies: 28829 -> 28662 (-0.58%); split: -1.90%, +1.32%
Branches: 3560 -> 3564 (+0.11%)
PreVGPRs: 2550 -> 2427 (-4.82%)

Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15176>
2022-06-27 15:07:27 +00:00
Daniel Schürmann def3690447 radv: use callback for nir_lower_to_scalar
Now uses nir_lower_alu_width.
This avoids scalarization and re-vectorization of 16bit instructions.

Totals from 289 (0.21% of 134913) affected shaders: (GFX10.3)
VGPRs: 12864 -> 13072 (+1.62%); split: -0.50%, +2.11%
SpillSGPRs: 609 -> 505 (-17.08%)
SpillVGPRs: 946 -> 1145 (+21.04%)
CodeSize: 2537024 -> 2576976 (+1.57%); split: -0.10%, +1.67%
Scratch: 89088 -> 113664 (+27.59%)
MaxWaves: 7150 -> 7134 (-0.22%)
Instrs: 458352 -> 460830 (+0.54%); split: -0.45%, +0.99%
Latency: 6615279 -> 6844092 (+3.46%); split: -0.08%, +3.54%
InvThroughput: 1929504 -> 2044989 (+5.99%); split: -0.22%, +6.21%
VClause: 7186 -> 7338 (+2.12%); split: -0.08%, +2.20%
SClause: 13144 -> 13116 (-0.21%)
Copies: 46152 -> 50127 (+8.61%); split: -0.11%, +8.73%
Branches: 16530 -> 16572 (+0.25%); split: -0.02%, +0.27%
PreSGPRs: 14903 -> 14905 (+0.01%); split: -0.01%, +0.03%
PreVGPRs: 11806 -> 11730 (-0.64%); split: -1.83%, +1.19%

Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15176>
2022-06-27 15:07:27 +00:00
Daniel Schürmann 4235dd7b47 radv: don't lower vectorized instructions to 32bit
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15176>
2022-06-27 15:07:27 +00:00
Daniel Schürmann c298ab0d23 aco: correctly validate v_fma_mixhi_f16 register assignment
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15176>
2022-06-27 15:07:27 +00:00
Samuel Pitoiset fd997bde2f radv: dump UMR waves before UMR rings
Dumping UMR rings might be slow and dumping waves before would make it
more chance to dump them without reporting "No active waves".

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17183>
2022-06-27 08:36:49 +00:00
Samuel Pitoiset 4c908d4587 radv: fix command line for dumping waves with UMR
GFXOFF must be disabled before dumping waves and re-enabled after.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17183>
2022-06-27 08:36:49 +00:00
Samuel Pitoiset 915bc6a179 radv: use RADEON_FLAG_VA_UNCACHED for the trace BO
Figured this while debugging a GPU hang with a simple CTS test. This
is to make sure data written by the CP are coherent on the CPU.

This also explains spurious GPU hang reports generated for Hitman 3
that made no sense without it. Now it's clear that this game hangs
after a DRAW_INDEX_INDIRECT packet.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17183>
2022-06-27 08:36:49 +00:00
Samuel Pitoiset db7890637e radv: disable small primitive culling for user sample locations
The driver can't assume sample positions at (0.5, 0.5) when user
sample locations are used.

This doesn't fix anything in practice because NGGC is only enabled by
default on GFX10.3 and that extension is currently disabled on GFX10+,
but I would like to expose it at some point.

This fixes dEQP-VK.pipeline.*.sample_locations_ext.verify_location.*
(when the extension is enabled locally).

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17228>
2022-06-27 08:10:08 +00:00
Qiang Yu 04b15f88e7 radeonsi: replace llvm gs input handle with nir lowering
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
2022-06-27 11:32:50 +08:00
Qiang Yu 36197b8dc0 ac/llvm: get back nir_intrinsic_load_gs_vertex_offset_amd
Will be used by radeonsi.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
2022-06-27 11:32:46 +08:00
Qiang Yu e9f1f115fa ac/nir: add triangle_strip_adjacency_fix to gs input lower
From radeonsi.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
2022-06-27 11:32:43 +08:00
Qiang Yu 109eb378e5 ac/nir: change es output lower param to esgs_itemsize
radeonsi may add extra dword to the stride, so let's pass it
directly.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
2022-06-27 11:32:34 +08:00
Qiang Yu 8b5e8b2af7 ac/nir: remove unused param num_reserved_es_outputs from gs input lower
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
2022-06-27 11:32:30 +08:00
Qiang Yu 7ddd15f6c7 ac/nir: skip gl_ViewportIndex and gl_Layer write in ES
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
2022-06-27 11:32:21 +08:00
Qiang Yu 06d493dde2 radeonsi: implement two esgs ring nir intrinsic
nir_intrinsic_load_ring_esgs_amd
nir_intrinsic_load_ring_es2gs_offset_amd

Will be used by esgs lowering.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
2022-06-27 11:32:15 +08:00
Qiang Yu 9fc01f6e79 ac/llvm: fix code format alignment in visit_load_local_invocation_index
Used tab instead of space.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16788>
2022-06-27 11:32:00 +08:00
Qiang Yu 7847114343 radeonsi: replace llvm tes input load with nir lowering
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu 2b7e167bbd radeonsi: enable PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS
This can remove special handling of tessfactors which also benifit
the nir lower pass which does not handle these as system value.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu 7598bfd768 radeonsi: replace llvm tcs output with nir lower pass
Remove the store_tcs_outputs abi, we can use common output abi
to handle the tessfactor pass as vgpr.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu d00845faf4 ac/nir: add no_input_lds_space param to hs output lower
This is used by radeonsi to save some lds space when all LS output
is passed by register.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu 8f8d06bd05 ac/llvm: handle write mask for nir_intrinsic_store_buffer_amd
tess lowering may generate buffer store with partial write mask.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu baaeca7d1a radeonsi: implement nir_intrinsic_load_tess_rel_patch_id_amd for both tcs and tes
radv will lower this intrinsic before gets to llvm, so we just need to
implement it in radeonsi.

The tes version will be used in tess lower too.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu 3853dfcd44 radeonsi: implement nir_intrinsic_load_ring_tess_offchip(_offset)_amd
Used by tess lower latter.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu ae9b02b4d0 ac/nir: add wave_size parameter to ac_nir_lower_hs_outputs_to_mem
Used by radeonsi and radv to reflect true wave size used, not minimal size.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu 18d51831a8 ac/nir: add pass_tessfactors_by_reg param to hs output lower
radeonsi won't emit tess factor in the lower pass, need to keep
the output for llvm backend to pass it as parameter. This is used
by radeonsi for an optimization to save LDS write.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu 6ccb9634de ac/nir: use nir_intrinsic_load_hs_out_patch_data_offset_amd in tess lower
radeonsi load this from SGPR arg, can't use static value because TCS output
and TES input may not match (TCS output is not a key for TES) and
determined in runtime.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu fdf589321c ac/nir: add nir_intrinsic_load_hs_out_patch_data_offset_amd
Also add radv and radeonsi implementation. Will be used in tess lowering.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu 2ba6d2b107 ac/nir: remove unused parameter in tes input lower
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu 07e025a390 radeonsi: implement nir_intrinsic_load_tcs_num_patches_amd
Used by ac_nir_lower_tess_io_to_mem.c.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16705>
2022-06-27 02:38:21 +00:00
Qiang Yu 3aa70d92ce radv: no need to do gs_alloc_req for newer chips in ngg vs/tes
Copy from radeonsi.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17130>
2022-06-27 02:12:13 +00:00
Qiang Yu 74e596a5f0 ac/llvm: conditionally check wave id in gs sendmsg
nir lowering already call this with wave id check, no need to
check inside ac_build_sendmsg_gs_alloc_req again.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17130>
2022-06-27 02:12:13 +00:00
Bas Nieuwenhuizen e75f11625d radv: Deal with derefs from opaque types in function parameters.
Needs more copy propagation before nir_opt_derefs picks it up.

Note that the full general problem of opaque types stored in
intermediate variables is still open, but that seems like a whole
can of worms, and no sense to have gfxbench stay broken during the
time it takes to solve that.

Cc: mesa-stable
Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5945
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17012>
2022-06-27 01:23:43 +00:00
Rhys Perry 33641b2a26 aco: cleanup force-waitcnt output
If we don't reset ctx.vm_cnt/gpr_map/etc, this will spam a lot of
s_waitcnt instructions.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17207>
2022-06-24 12:44:55 +00:00
Georg Lehmann ed429af586 radv: Don't check if we need to copy immutable samplers for non push templates.
This should allow the compiler to optimize this out because it knows that
cmd_buffer is NULL.

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17166>
2022-06-24 06:32:43 +00:00
Andres Gomez 01a1af1819 radv/ci: update vkd3d-proton results for AMD's Kabini
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17184>
2022-06-24 05:32:53 +00:00
Rhys Perry 6fc2622abd aco: don't skip VS->TCS barrier if TCS output vertices doesn't match input
TCS invocations correspond to output patch vertices, not input. If they
differ, TCS invocations can be in a different subgroup than VS invocations
of the input patch.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6564
Fixes: 152092b8ea ("aco: skip s_barrier if TCS patches are within subgroup")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17174>
2022-06-23 10:08:02 +00:00
Samuel Pitoiset ad3d6d9c6e radv/llvm: always emit a null export even if the FS doesn't discard
Even with a noop FS, the color blend state can still be non-zero, and
then SPI color related registers won't be 0 and this would hang.

Fixes: bdf3797aeb ("ac,radeonsi: don't export null from PS if it has no effect on gfx10+")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17169>
2022-06-22 08:31:30 +02:00
Martin Roukala (né Peres) 677a42378b ci/radv: add a missing flake
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17131>
2022-06-21 13:11:05 +03:00
Martin Roukala (né Peres) f86e12743c ci/radv: move a test from the fail list to the flake list
The test was misidentified as a "fail", when it actually has a very
high failure rate (>95%). The test happened to pass twice within the
last week, so let's mark this test as a flake.

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17131>
2022-06-21 13:10:51 +03:00
Samuel Pitoiset 6cab999d6a radv,aco: rename radv_prolog_binary/radv_shader_prolog to shader_part
The same structures and functions will be re-used for PS epilogs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17084>
2022-06-21 08:04:50 +00:00
Vinson Lee 2b87073133 radv: Remove unnecessary null check.
Fix defect reported by Coverity Scan.

Dereference before null check (REVERSE_INULL)
check_after_deref: Null-checking subpass suggests that it may be null,
but it has already been dereferenced on all paths leading to the check.

Fixes: 779e09639b ("radv: configure DB_Z_INFO.NUM_SAMPLES correctly on GFX11")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17100>
2022-06-21 04:00:46 +00:00
Georg Lehmann 7afecd8ad8 radv: Check descriptor pool entry count before allocating a new set.
It's simpler and more efficient.

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17127>
2022-06-20 10:50:01 +00:00
Georg Lehmann ceb3ae2afb radv: Remove redundant memset in radv_descriptor_set_create.
The memset below also clears this memory, plus the descriptor set header.

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17127>
2022-06-20 10:50:01 +00:00
Samuel Pitoiset 5485bf7b1b aco: fix validation of SOP1 instructions without definitions
Like s_setpc_b64.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17082>
2022-06-20 07:08:28 +00:00
Samuel Pitoiset 6dd2699e9f radv/amdgpu: do not add "global" BO to the virtual BO list
To avoid dangling BO references if it's destroyed without being
previously unbound. This is under Vulkan spec clarification but it
looks like the "global" BO fix is simple enough to workaround the
issue for now.

This fixes a CPU hang with Halo Infinite because the kernel rejects
a submission (invalid BO handle found).

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17085>
2022-06-20 06:43:53 +00:00
Samuel Pitoiset b4cc10b342 radv/amdgpu: make sure to reset the number of BO when there is no ranges
If an application binds a sparse resource and then unbind it with NULL,
the number of "real" BOs in the virtual BO list should be reset to 0.
Otherwise, it might use a dangling BO reference if it's destroyed just
after being unbound.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17085>
2022-06-20 06:43:53 +00:00
Martin Roukala (né Peres) 8a9f7087a1 radv/ci: test vkd3d on kabini
The machine is extremely slow and fails to finish vkcts, but vkd3d may
still be used as a way to detect extreme regressions.

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17081>
2022-06-18 19:33:24 +03:00
Samuel Pitoiset 16c47ad347 radv: advertise VK_EXT_border_color_swizzle on GFX10+
On GFX9 and older, the driver needs to swizzle itself it seems.
Exposing it on GFX10+, allows us to test it with Zink, at least.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17057>
2022-06-16 18:31:33 +00:00
Samuel Pitoiset 9df7ad0320 radv/ci: add vkd3d-proton testing
The vkd3d-proton can be very useful, I recently found issues while
implementing VK_EXT_primitives_generated_query and
VK_KHR_fragment_shader_barycentric.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17050>
2022-06-16 06:36:36 +00:00
Samuel Pitoiset 3f2de5e662 radv/ci: refactor test machines and dEQP rules to reduce copy&paste config
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17050>
2022-06-16 06:36:36 +00:00
Ruijing Dong 515112eabd radeonsi/vcn: prepare for unified queue in vcn4
- apply unified queue ib headers to vcn4
  - re-use encoding queue as unified queue
  - define unified queue functions and structures

Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16911>
2022-06-16 03:30:47 +00:00
Rhys Perry 33e7ba2e3e aco: update SMEM offset workaround for LLVM 15
This isn't needed since LLVM 15's b0ccf38b018.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-By: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6663
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17036>
2022-06-16 00:47:51 +00:00
Marek Olšák ee7150da79 amd/gfx11: add PixelWaitSync packet fields
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16990>
2022-06-15 20:52:42 +00:00
Marek Olšák 7d8847d963 ac/llvm: fix tcs_wave_id unpacking on gfx11
no effect on behavior because the higher bits are always zero

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16990>
2022-06-15 20:52:42 +00:00
Timur Kristóf 08435b1c6f radv: Always use 3D block ID and grid size in task shaders.
These are needed to address the task draw and payload ring buffers
when the task shader dispatch is 3 dimensional.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17023>
2022-06-15 18:28:58 +00:00
Timur Kristóf 0fb9573c57 ac/nir/taskmesh: Preserve workgroup ID Y and Z when applying firstTask.
NV_mesh_shader workgroups are only 1 dimensional, so it's OK to
only add firstTask to the X dimension.
However, let's keep the Y and Z dimensions so this doesn't mess up
the workgroup ID for future 3 dimensional task shader dispatches.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17023>
2022-06-15 18:28:58 +00:00
Timur Kristóf b243e94f07 radv: Lower mesh shader 3D workgroup ID to 1D index.
This allows future mesh shaders to use a 3D workgroup ID.
Also changes how the NV_mesh_shader first_task is emulated.
The new code moves the responsibility from ac_nir into radv.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17023>
2022-06-15 18:28:58 +00:00
Timur Kristóf e05f63f56c ac/nir/ngg: Add mesh shader workgroup index.
This will allow lowering 3D workgroup ID to a 1D index.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17023>
2022-06-15 18:28:58 +00:00
Timur Kristóf 856a8acab0 radv: Enable NGG wave ID for mesh shader scratch ring.
This wave ID is used to address the scratch ring, so it should be
enabled when the scratch ring is used.

Note: the naming is confusing here, as this ID is actually the same
accross the whole workgroup. (It would be more appropriate to call
it workgroup ID instead.)

Fixes: 0280b526d5
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17022>
2022-06-15 18:05:51 +00:00
Samuel Pitoiset 8589230602 radv/ci: add GLES/GLCTS testing with Zink on NAVI10
This includes GLES{2,3,21} and GL46.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16975>
2022-06-15 13:14:17 +00:00
Samuel Pitoiset 8ffabb2511 ci/valve: split .b2c-test into .b2c-test-vk and .b2c-test-gl
We have to use a different test image for GL.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16975>
2022-06-15 13:14:17 +00:00
Samuel Pitoiset 4bd6519b6b radv: remove remaining unused pCreateInfo pointers
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16958>
2022-06-13 16:46:32 +00:00
Samuel Pitoiset 653ded5704 radv: update the check to determine if rasterization is enabled
Use radv_graphics_pipeline_info instead of pCreateInfo.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16958>
2022-06-13 16:46:32 +00:00
Samuel Pitoiset e8a0f514d4 radv: update the check to determine if dynamic sample location is needed
Use radv_graphics_pipeline_info instead of pCreateInfo.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16958>
2022-06-13 16:46:32 +00:00
Samuel Pitoiset 15586cdaf8 radv: update the check to determine if dynamic discard rectangle is needed
Use radv_graphics_pipeline_info instead of pCreateInfo.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16958>
2022-06-13 16:46:32 +00:00
Samuel Pitoiset a42190b647 radv: update radv_is_vrs_enabled() to use radv_graphics_pipeline_info
pCreateInfo pointers have to be completely replaced for graphics
pipeline library.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16958>
2022-06-13 16:46:32 +00:00
Samuel Pitoiset 839b1f4e91 radv: remove redundant check when importing vertex input info
It's already checked by the caller.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16958>
2022-06-13 16:46:32 +00:00
Marek Olšák 9490ae5561 ac/gpu_info: clamp gart_size_kb and vram_size_kb to fix buggy kernel driver
amdgpu returns 12 TB of GTT on Kaveri, which resulted in 0 KB of GTT
after the conversion to uint32_t, which caused us to report 0 as the UBO
size, which disabled UBOs and downgraded the driver to OpenGL 3.0.

Fixes: aee8ee17a5 - radeonsi: change max TBO/SSBO sizes again and rework max alloc size
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6642

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16885>
2022-06-11 11:14:16 +00:00
Marek Olšák bdf3797aeb ac,radeonsi: don't export null from PS if it has no effect on gfx10+
We just need to pass the uses_discard flag to the epilog.

The hw skips the export anyway. This will hang if SPI registers declare
an output format or KILL_ENABLE is set because those cases require
an export with done=1.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16885>
2022-06-11 11:14:16 +00:00
Konstantin Seurer 1592921c59 radv: Move some rt intrinsics to the top
We need to move tr intrinsics to the top of the
shader that might be overwritten by
nir_intrinsic_rt_trace_ray.

Fixes the Khronos reflection sample.

Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16889>
2022-06-11 09:30:56 +00:00
Georg Lehmann dcdd31ae96 aco: Remove r128_a16 MIMG builder option.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16969>
2022-06-10 15:51:26 +00:00
Georg Lehmann 0ca6653ada aco: Print r128/a16 MIMG bits separately.
These both exist since Navi and we can have instructions which are one but
not the other.

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16969>
2022-06-10 15:51:26 +00:00
Samuel Pitoiset 8f0e8808c0 radv/ci: rename deqp-XXX jobs to vkcts-XXX
This looks clearer and will avoid confusion with future Zink CI testing.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16943>
2022-06-10 15:16:11 +00:00
Jason Ekstrand e60ff7f1aa radv: Drop create_sync_for_memory
Also, stop setting wsi_device::signal_semaphore/fence_with_memory
because those cause the WSI code to call the function we just dropped.
Since the core WSI code is now setting dummy syncs by default, we don't
need any of this anymore.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4037>
2022-06-10 01:33:12 +00:00
Georg Lehmann 17818800d0 radv: Implement VK_EXT_non_seamless_cube_map.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12729>
2022-06-09 23:39:43 +00:00
Samuel Pitoiset 79877d5df5 radv: advertise VK_EXT_primitives_generated_query
Pass all dEQP-VK.transform_feedback.primitives_generated_query.*.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15639>
2022-06-09 08:02:39 +00:00
Samuel Pitoiset 1ebf463a5a radv: implement VK_EXT_primitives_generated_query
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15639>
2022-06-09 08:02:39 +00:00
Samuel Pitoiset e0edf8d240 radv: add few helpers related to streamout
Streamout must be enabled for the PRIMITIVES_GENERATED query to work.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15639>
2022-06-09 08:02:39 +00:00
Samuel Pitoiset f3daf7ce40 radv: flush the NGG query state when the argument is declared
When primitives generated query is used, the driver also needs to
emulate counting for NGG VS/TES.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15639>
2022-06-09 08:02:39 +00:00
Samuel Pitoiset fe57fe1fd8 ac/nir/ngg: count the number of generated primitives for VS and TES
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15639>
2022-06-09 08:02:39 +00:00
Samuel Pitoiset 60b07a0ab2 radv: declare the NGG query argument for primitives generated query
To emulare counting for NGG VS/TES.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15639>
2022-06-09 08:02:39 +00:00
Samuel Pitoiset 11734f935a radv: add primitives_generated_query to the graphics pipeline key
Different shader variants will be used to not hurt when the features
aren't enabled.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15639>
2022-06-09 08:02:39 +00:00
Samuel Pitoiset dc8cf44f60 radv: track if primitives generated query features are enabled
This will be used to conditionally declare the NGG query argument
for NGG VS/TES and also adjust the NGG shaders.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15639>
2022-06-09 08:02:39 +00:00
Samuel Pitoiset 3efbbf9588 radv: rename ngg_gs_state to ngg_query_state
This state will be used by NGG VS and NGG TES too.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15639>
2022-06-09 08:02:39 +00:00
Georg Lehmann 5ebb014bdf radv, aco: Round texture array layer in NIR.
Foz-DB Navi21:
Totals from 9100 (6.75% of 134913) affected shaders:
VGPRs: 609912 -> 610104 (+0.03%); split: -0.01%, +0.05%
SpillSGPRs: 1459 -> 1489 (+2.06%)
CodeSize: 66705920 -> 66620288 (-0.13%); split: -0.13%, +0.00%
MaxWaves: 148546 -> 148518 (-0.02%); split: +0.00%, -0.02%
Instrs: 12278485 -> 12255821 (-0.18%); split: -0.19%, +0.00%
Latency: 277414916 -> 277261192 (-0.06%); split: -0.08%, +0.02%
InvThroughput: 48431180 -> 48394637 (-0.08%); split: -0.11%, +0.03%
VClause: 250866 -> 251062 (+0.08%); split: -0.04%, +0.11%
SClause: 498377 -> 498173 (-0.04%); split: -0.08%, +0.04%
Copies: 652835 -> 655371 (+0.39%); split: -0.09%, +0.48%
Branches: 284367 -> 284371 (+0.00%); split: -0.00%, +0.00%
PreSGPRs: 498580 -> 498477 (-0.02%)
PreVGPRs: 558436 -> 558709 (+0.05%); split: -0.01%, +0.06%

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16871>
2022-06-08 20:57:22 +00:00
Konstantin Seurer 2cb0c9ea13 radv: Advertise VK_KHR_ray_tracing_maintenance1
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16430>
2022-06-08 20:20:21 +00:00
Konstantin Seurer 16585664cd radv: vkCmdTraceRaysIndirect2KHR
This changes the trace rays logic to always use
VkTraceRaysIndirectCommand2KHR and implements
vkCmdTraceRaysIndirect2KHR. I renamed the
load_sbt_amd to sbt_base_amd and moved the SBT
load lowering from ACO to NIR.

Note that we can not just upload one pointer to
all the trace parameters because that would
be incompatible with traceRaysIndirect.

Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16430>
2022-06-08 20:20:21 +00:00
Konstantin Seurer fea155348f radv: PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_COPY
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16430>
2022-06-08 20:20:21 +00:00
Konstantin Seurer e8ac9dd23f radv: ACCESS_2_SHADER_BINDING_TABLE_READ_BIT_KHR
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16430>
2022-06-08 20:20:21 +00:00
Konstantin Seurer 5d56c2cfc0 radv: Add accel struct queries for maintenance1
Implements the new
VK_QUERY_TYPE_ACCELERATION_STRUCTURE_SERIALIZATION_BOTTOM_LEVEL_POINTERS_KHR
and
VK_QUERY_TYPE_ACCELERATION_STRUCTURE_SIZE_KHR
query types.

The documentation is a bit lacking for now but
the fist type probably refers to the instance
count and the second type refers to the
acceleration structure size which we already
store in radv_acceleration_structure. To support
size queries, this commit adds a size member
to the acceleration structure header.

Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16430>
2022-06-08 20:20:21 +00:00
Konstantin Seurer d5dd0df65f radv: ray cull mask
Lower the cull_mask system value to rt variable
load and advertise the corresponding capability.

Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16430>
2022-06-08 20:20:21 +00:00
Marek Olšák aee8ee17a5 radeonsi: change max TBO/SSBO sizes again and rework max alloc size
Allow 1/4 of the max heap size, but maximum of 512 MB on 32-bit
architectures.

Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16901>
2022-06-08 10:23:20 +00:00
Timur Kristóf 0280b526d5 radv: Implement mesh shader scratch ring.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16737>
2022-06-08 08:43:51 +00:00
Timur Kristóf 6056583ae1 ac/nir/ngg: Use variables for outputs without cross-invocation access.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16737>
2022-06-08 08:43:51 +00:00
Timur Kristóf b664279755 ac/nir/ngg: Use mesh shader scratch ring when outputs don't fit LDS.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16737>
2022-06-08 08:43:51 +00:00
Timur Kristóf 304a0e948b ac/nir/ngg: Clean up mesh shader output LDS layout.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16737>
2022-06-08 08:43:51 +00:00
Timur Kristóf b730f91247 radv: Implement task shader draw and payload rings.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16737>
2022-06-08 08:43:51 +00:00
Timur Kristóf ac5ab8d227 ac: Add task shader ring information.
Similarly to tessellation rings information, move the task
rings info to ac_gpu_info.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16737>
2022-06-08 08:43:51 +00:00
Timur Kristóf 086e499b47 ac: Add RDNA2 task+mesh shader draw packet opcodes.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16737>
2022-06-08 08:43:51 +00:00
Georg Lehmann d8493e5310 radv, aco: Lower txf offset in NIR.
Foz-DB Navi21:
Totals from 384 (0.28% of 134913) affected shaders:
VGPRs: 29736 -> 29536 (-0.67%)
CodeSize: 2455796 -> 2452652 (-0.13%); split: -0.13%, +0.01%
MaxWaves: 6350 -> 6358 (+0.13%)
Instrs: 457743 -> 456273 (-0.32%); split: -0.33%, +0.01%
Latency: 6680266 -> 6730612 (+0.75%); split: -0.03%, +0.78%
InvThroughput: 1562936 -> 1599375 (+2.33%); split: -0.05%, +2.38%
VClause: 9258 -> 9291 (+0.36%); split: -0.14%, +0.50%
SClause: 15713 -> 15707 (-0.04%); split: -0.08%, +0.04%
Copies: 26878 -> 27021 (+0.53%); split: -0.03%, +0.56%
PreVGPRs: 27259 -> 27230 (-0.11%); split: -0.11%, +0.01%

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16869>
2022-06-08 08:13:01 +00:00
Jason Ekstrand 8d6b7eb5ce radv: Use vk_image_buffer_copy_layout
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16873>
2022-06-07 17:57:42 +00:00
Jason Ekstrand c144030f7e vulkan,radv: Steal some image offset/extent helpers from radv
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16873>
2022-06-07 17:57:42 +00:00
Jason Ekstrand 69e4d39d18 vulkan,radv: Move vk_format_get_plane_format to common code
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16873>
2022-06-07 17:57:42 +00:00
Jason Ekstrand 1436fa55a6 radv: Use the common image offset/extent sanitize helpers
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16873>
2022-06-07 17:57:41 +00:00
Konstantin Seurer b24216c52d radv: Fix the accel struct size calculation
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16874>
2022-06-07 12:26:02 +00:00
Rhys Perry 062b5a9ba1 ac: use ResetAllOptionOccurrences instead of ResetCommandLineParser
Fixes -amdgpu-atomic-optimizations=true option.

From CommandLine.h:
/// Reset all command line options to a state that looks as if they have
/// never appeared on the command line.  This is useful for being able to parse
/// a command line multiple times (especially useful for writing tests).
void ResetAllOptionOccurrences();

/// Reset the command line parser back to its initial state.  This
/// removes
/// all options, categories, and subcommands and returns the parser to a state
/// where no options are supported.
void ResetCommandLineParser();

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Fixes: 7e2874dc93 ("ac: reset LLVM command line parser")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16850>
2022-06-07 10:29:56 +00:00
Samuel Pitoiset f06da59fd7 radv: report the marketing name as part of the device name
This now reports something like "AMD Radeon RX 5700 XT (RADV NAVI10)".

This introduces a new variable for storing the marketing name because
the existing device name is used by the shaders cache and must remain
the same to avoid any issues with precompilation.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4802
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11027>
2022-06-07 07:48:07 +00:00
Samuel Pitoiset 42b3735716 radv/winsys: add get_chip_name() to the null winsys
Make it return "Null hardware", this is just for RADV_FORCE_FAMILY.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11027>
2022-06-07 07:48:07 +00:00
Qiang Yu 61c500ee9b radeonsi: replace llvm ls/hs interface lds ops with nir lowered ones
Use ac nir lower pass to generate these lds load/store ops explicitly.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16418>
2022-06-07 01:40:14 +00:00
Timur Kristóf f7f2770e72 ac/nir: Add remappability to tess and ESGS I/O lowering passes.
This will be used for radeonsi to map common I/O location to fixed
slots agreed by different shader stages.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16418>
2022-06-07 01:40:14 +00:00
Qiang Yu 666dbbf1a3 ac/nir: skip gl_Layer/gl_ViewportIndex write for LS
This is from radeonsi.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16418>
2022-06-07 01:40:14 +00:00
Qiang Yu 47dd3525fb radeonsi: implement load_lshs_vertex_stride abi
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16418>
2022-06-07 01:40:14 +00:00
Qiang Yu 6a95452ddf ac/nir: use nir_intrinsic_load_lshs_vertex_stride_amd
For radeonsi which pass this value by argument.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16418>
2022-06-07 01:40:14 +00:00
Qiang Yu e35ff669b5 ac/llvm: get back nir_intrinsic_load_tess_rel_patch_id_amd
radeonsi will use it. This can be removed again after radeonsi support
radv_nir_lower_abi like lower pass.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16418>
2022-06-07 01:40:13 +00:00
Rhys Perry 40db52488b aco: consider fma with multiplication by power-of-two unfused
fossil-db (Sienna Cichlid):
Totals from 700 (0.43% of 162353) affected shaders:
MaxWaves: 18986 -> 18990 (+0.02%)
Instrs: 546475 -> 539729 (-1.23%); split: -1.24%, +0.00%
CodeSize: 2823716 -> 2808504 (-0.54%); split: -0.55%, +0.01%
VGPRs: 25304 -> 25288 (-0.06%)
Latency: 2180102 -> 2168187 (-0.55%); split: -0.55%, +0.01%
InvThroughput: 466223 -> 457326 (-1.91%)
VClause: 6768 -> 6797 (+0.43%); split: -0.01%, +0.44%
SClause: 12235 -> 12237 (+0.02%); split: -0.22%, +0.24%
Copies: 34498 -> 34479 (-0.06%); split: -0.21%, +0.15%
PreVGPRs: 20968 -> 20958 (-0.05%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15862>
2022-06-06 19:06:01 +00:00
Rhys Perry f4c02d9116 aco: fix SMEM load_global with VGPR address and non-zero offset
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Fixes: 3e9517c757 ("aco: implement _amd global access intrinsics")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16775>
2022-06-06 17:47:59 +00:00
Rhys Perry 4d9f3fcf9c aco: fix SMEM load_global_amd with non-zero offset
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Fixes: 3e9517c757 ("aco: implement _amd global access intrinsics")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16775>
2022-06-06 17:47:59 +00:00
Konstantin Seurer e8da8fc5b7 radv: Require an alignment of 64 for accel structs
Top level acceleration structures need the bottom
6 bits to store the root ids of instances. If we
don't require that alignment, more "advanced"
allocators like VMA may sub allocate a buffer
which can lead to the 6 getting lost.

Fixes the Khronos ray tracing Vulkan samples.

Closes: #6598
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16870>
2022-06-06 13:49:24 +00:00
Konstantin Seurer ae19e9c292 radv: Some acceleration structure cleanups
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16782>
2022-06-03 13:28:37 +00:00
Konstantin Seurer 5c5021de27 radv: Add and use radv_cp_dma_wait_for_stages
Adds a small helper for handling cp dma sync. This
Also adds the missing handling for some stage
flags in write_event.

Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16782>
2022-06-03 13:28:37 +00:00
Samuel Pitoiset fe9f1d064a radv: enable radv_zero_vram for Hammerting
This native Vulkan game is broken, it has TON of Vulkan validation
errors and hangs without RADV_DEBUG=zerovram. Also tested with PRO
and AMDVLK.

The application name is also not really descriptive but the executable
name 'boot.exe' is worst.

https://github.com/ValveSoftware/Proton/issues/4347#issuecomment-1141415515

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16832>
2022-06-03 08:29:58 +00:00
Yonggang Luo 1d3727bcc6 radv: Remove usage of `cnd_monotonic.h`
Improve: 91fe0b5629 ("radv: Delete lots of sync code.")

As cnd_monotonic.h are include `util/os_time.h`, radv_debug.c and radv_debug.c needs `util/os_time.h`
So include in these files directly.

The compiling errors are:
```
../src/amd/vulkan/radv_debug.c:707:12: error: implicit declaration of function 'os_localtime' is invalid in C99 [-Werror,-Wimplicit-function-declaration]
   timep = os_localtime(&raw_time, &result);

../src/amd/vulkan/radv_device.c:97:11: error: implicit declaration of function 'os_time_get_nano' is invalid in C99 [-Werror,-Wimplicit-function-declaration]
   return os_time_get_nano();
          ^

../../src/amd/vulkan/radv_pipeline.c: In function 'radv_create_shaders':
../../src/amd/vulkan/radv_pipeline.c:4119:29: error: implicit declaration of function 'os_time_get_nano' [-Werror=implicit-function-declaration]
 4119 |    int64_t pipeline_start = os_time_get_nano();
```

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16536>
2022-06-03 06:46:38 +00:00
Samuel Pitoiset e680fe224a radv/ci: update list of failures for Pitcairn
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16836>
2022-06-02 17:03:59 +02:00
Rhys Perry be4c1a5f52 radv,aco: disable shader cache when ACO debug options are used
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14594>
2022-06-02 14:45:55 +00:00
Erik Faye-Lund df2dd474c7 include: drop c11_compat.h
We now require C11, and C++ supports static_assert just fine, which is
the only thing this header ever added support for. So let's get rid of
this needless header.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16812>
2022-06-02 13:09:16 +00:00
Martin Roukala (né Peres) 72cf18f54a radv/ci: try to guess failure expectations for Fiji/Raven/Navi14/Navi22
The guesses are based on other gpus from the same gfx version. We will
need actual runs on the GPUs to confirm this.

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16810>
2022-06-02 08:29:31 +00:00
Martin Roukala (né Peres) 205744b42d radv/ci: remove an expected fail from all families
dEQP-VK.glsl.builtin.precision_double.determinant.compute.mat3 was
failing because of a CTS bug, which got fixed in the latest update for
all our CI machines.

This commit assumes this got fixed for all families, even the ones we
did not try to run on.

Fixes: 836ce97f5e (ci: bump VK-GL-CTS to 1.3.2.0)
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16810>
2022-06-02 08:29:31 +00:00
Martin Roukala (né Peres) 91f93c97dd radv/ci: update the vkcts expectations for the CI machines
Fixes: 836ce97f5e (ci: bump VK-GL-CTS to 1.3.2.0)
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16810>
2022-06-02 08:29:31 +00:00
Martin Roukala (né Peres) e58c455ca9 radv/ci: bump the timeout of vangogh/renoir
The execution time of vkcts has drastically changed with the latest
update, especially for APUs. This commit bumps the timeout to give
them a chance to finish.

Fixes: 836ce97f5e (ci: bump VK-GL-CTS to 1.3.2.0)
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16810>
2022-06-02 08:29:31 +00:00
Samuel Pitoiset 5af1409c1b radv: fix lowering GS intrinsics if NGG is disabled per pipeline
If NGG is disabled per pipeline for extreme (or suboptimal) geometry
or with transform feedback, make sure to not lower GS intrinsics that
are only needed for NGG GS. This means we have to lower GS intrinsics
later in the compilation process to effectively know if the pipeline
uses NGG.

fossils-db (Navi21):
Totals from 8 (0.01% of 134913) affected shaders:
VGPRs: 512 -> 520 (+1.56%)
CodeSize: 58180 -> 65080 (+11.86%); split: -0.04%, +11.90%
MaxWaves: 128 -> 126 (-1.56%)
Instrs: 10525 -> 11779 (+11.91%); split: -0.05%, +11.96%
Latency: 62941 -> 49428 (-21.47%); split: -21.59%, +0.12%
InvThroughput: 16121 -> 12950 (-19.67%); split: -19.96%, +0.29%
VClause: 122 -> 123 (+0.82%); split: -0.82%, +1.64%
SClause: 130 -> 143 (+10.00%)
Copies: 566 -> 596 (+5.30%); split: -0.35%, +5.65%
Branches: 200 -> 208 (+4.00%)
PreSGPRs: 424 -> 422 (-0.47%)
PreVGPRs: 430 -> 424 (-1.40%); split: -1.63%, +0.23%

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15885>
2022-06-02 09:42:54 +02:00
Georg Lehmann 1d815548ab radv, aco: Packed usub_sat/isub_sat.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>
2022-06-01 17:09:25 +00:00
Georg Lehmann aa9d2d8893 radv: Enable VK_INTEL_shader_integer_functions2.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>
2022-06-01 17:09:25 +00:00
Georg Lehmann 55735ed728 radv: Lower 8bit isub_sat/usub_sat.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>
2022-06-01 17:09:25 +00:00
Georg Lehmann 4e6667ea87 radv: Lower hadd/hradd.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>
2022-06-01 17:09:25 +00:00
Georg Lehmann cc3f03b757 radv: Lower mul_32x16.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>
2022-06-01 17:09:25 +00:00
Georg Lehmann 83f51212c1 ac/llvm: Implement uclz.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>
2022-06-01 17:09:25 +00:00
Georg Lehmann 8671b866bf ac/llvm: Implement usub_sat and isub_sat.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>
2022-06-01 17:09:25 +00:00
Georg Lehmann d404f1964c aco: Implement isub_sat.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>
2022-06-01 17:09:25 +00:00
Georg Lehmann faa2a89487 aco: Implement usub_sat.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>
2022-06-01 17:09:25 +00:00
Georg Lehmann 529ec3d7dc aco: Implement uclz.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>
2022-06-01 17:09:25 +00:00
Martin Roukala (né Peres) 60c82453a1 radv/ci: allow polaris10 to retry more times
The Polaris10 in CI has been getting insta-hangs when starting dEQP.
Let's give it 5 attempts to get its act together, as it won't affect
the run time dramatically (max 5 minutes), but will provide more
reliable results for developers.

Tracking of hangs (and many other issues) is done through scrapping the
execution logs, processing them to find these issues, then pushing the
data to influxdb. This allows us to plot the failure rate over time,
and see if the situation is getting better or worse.

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16793>
2022-06-01 13:03:02 +00:00
Daniel Schürmann bd151a256e nir/opt_vectorize: add callback for max vectorization width
The callback allows to request different vectorization factors
per instruction depending on e.g. bitsize or opcode.

This patch also removes using the vectorize_vec2_16bit option
from nir_opt_vectorize().

Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13080>
2022-06-01 11:41:44 +00:00
Daniel Schürmann 8e41c66639 aco: fix spilling of phis without temp operands
These were spilled unconditionally.

Cc: mesa-stable
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16708>
2022-06-01 09:11:03 +00:00
Samuel Pitoiset b968b99c45 radv: reduce radv_discard_rectangle_info::count to 8-bit
DiscardRectangleCount must be less than or equal to
maxDiscardRectangles which is limited to 4.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16778>
2022-06-01 07:59:27 +00:00
Samuel Pitoiset b62f1cdee8 radv: reduce radv_rasterization_info::polygon_mode to 8-bit
It's large enough.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16778>
2022-06-01 07:59:27 +00:00
Samuel Pitoiset 38b6f2e0ce radv: reduce radv_input_assembly_info::primitive_topology to 8-bit
It's large enough.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16778>
2022-06-01 07:59:27 +00:00
Samuel Pitoiset 2f176f86c2 radv: reduce radv_tessellation_info::patch_control_points to 8-bit
The value must be less than or equal to maxTessellationPatchSize which
is limited to 32 with RADV.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16778>
2022-06-01 07:59:27 +00:00
Samuel Pitoiset c869a5d550 radv: ignore DYNAMIC_STENCIL_OP if stencil test isn't enabled
Like compare/write masks and reference.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16783>
2022-06-01 07:34:28 +00:00
Martin Roukala (né Peres) 2f7f4060ee radv/ci: update the list of flakes
This commit has been created by aggregating all the flakes found in the
last 2 weeks, excluding the ones seen once.

v2 (Martin Roukala):
 - stop trying to hardcode all the flakes, use a wildcard

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16777>
2022-06-01 05:26:12 +00:00
Jason Ekstrand 7003ff2e3a radv: Use nir_gather_xfb_info
Instead of gathering XFB info over and over again every time we even
want to know if the shader uses XFB, gather it once when we compile the
shader and refer to the copy in the NIR.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16750>
2022-05-31 23:09:30 +00:00
Jason Ekstrand 3e04432b3a nir: Rename nir_gather_xfb_info to nir_shader_get_xfb_info
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16750>
2022-05-31 23:09:30 +00:00
Rhys Perry 982cc9bcf5 aco/tests: update for GFX11's removal of SDWA
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16595>
2022-05-31 18:07:34 +00:00
Rhys Perry e68e6c75ca aco: use v_perm_b32 to copy 0xff00/0x00ff/0xff/0x00
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16595>
2022-05-31 18:07:34 +00:00
Rhys Perry dae1629778 aco: disable sdwa on gfx11
Instead of SDWA v_mov_b32/v_xor_b32, we can use a combination of
v_add_u16/v_sub_u16 (add/sub swap, similar to xor swap) and v_perm_b32
with a literal.

I don't know yet if GFX11 adds any new instructions which makes this
easier, but this approach should have full functionality.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16595>
2022-05-31 18:07:34 +00:00
Rhys Perry d51dd7527b aco/tests: fix gfx11 variants printed as gfx12
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16595>
2022-05-31 18:07:34 +00:00
Rhys Perry c8bde76a42 aco/tests: disable regalloc.subdword_alloc.reuse_16bit_operands on GFX11
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16595>
2022-05-31 18:07:34 +00:00
Rhys Perry 9b60a67841 aco: clarify a portion of do_pack_2x16
This confused me a bit when I first saw it.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16595>
2022-05-31 18:07:34 +00:00
Rhys Perry 8384189b6c aco: use p_parallelcopy for uniform reduction with zero source
I think v_mov_b32 was only used because a sub-dword p_parallelcopy
couldn't take constants on some gfx levels. That shouldn't be the case
anymore.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16595>
2022-05-31 18:07:34 +00:00
Juan A. Suarez Romero 836ce97f5e ci: bump VK-GL-CTS to 1.3.2.0
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Alyssa Rosenzweig <alyssa@collabora.com>
Acked-by: Alejandro Piñeiro <apinheiro@igalia.com>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16689>
2022-05-31 15:02:08 +00:00
Pierre-Eric Pelloux-Prayer 9776c1cff2 ac/llvm: add use_waterfall_for_divergent_tex_samplers option
GLSL says that indexing in a samplers array should be done with
a dynamically uniform value.

If the app doesn't obey this constraint, it'll get incorrect
results.

But there's one case where the app might be correct and yet
get incorrect result: if 2 consecutive draws are used, with no
state changes in between, the hardware might run them in the
same wave and the app will get incorrect result as-if it was
using non-dynamically uniform index.

To prevent this, this commit takes advantage of the divergence
analysis pass - if the index is marked as divergent, then it will
have the same effect as using ACCESS_NON_UNIFORM in SPIR-V.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16709>
2022-05-31 13:08:07 +00:00
Timur Kristóf 2027f28b30 ac/nir/taskmesh: Use 3 dimensional workgroup ID.
For the sake of consistency, do not rely on a 1-dimensional
workgroup ID anymore.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16721>
2022-05-31 08:24:48 +00:00
Timur Kristóf c6d12a510c ac/nir/taskmesh: Use task shader lowering from common NIR code.
This also implements task_payload atomics for RADV.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16721>
2022-05-31 08:24:48 +00:00
Timur Kristóf c69b771e35 radv, ac/nir: Fix multiview layer export for mesh shaders.
Unfortunately, radv_lower_multiview is not suitable for mesh shaders
because it can't know the mapping between API mesh shader
invocations and output primitives.

Additionally, when lowering view id to layer, it must be created
as a per-primitive PS input.

Fixes: d32656bc65
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16504>
2022-05-31 07:58:29 +00:00
Marek Olšák 05eb9530ca ac/gpu_info: always retile DCC on gfx10 and newer chips
Unaligned DCC doesn't work there.

Fixes: f8cf5ea982 - amd: add support for gfx1036 and gfx1037 chips

Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16726>
2022-05-31 05:34:25 +00:00
Vinson Lee b35991dbcb amd: Initialize Gfx11Lib members in constructor.
Fix defects reported by Coverity Scan.

Uninitialized scalar field (UNINIT_CTOR)
uninit_member: Non-static class member m_numPkrLog2 is not initialized in this constructor nor in any functions that it calls.
uninit_member: Non-static class member m_numSaLog2 is not initialized in this constructor nor in any functions that it calls.

Fixes: 4fdf42b3c2 ("amd: import gfx11 addrlib")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16679>
2022-05-31 03:36:53 +00:00
Konstantin Seurer 1727310ea1 radv: Use vk_buffer
Use vk_buffer as a base for radv_buffer and
replace manual handling of VK_WHOLE_SIZE with
vk_buffer_range.

Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16764>
2022-05-30 17:43:58 +00:00
Rhys Perry cd2b4c319a aco/ra: fix usage of invalidated iterator
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes: 58bd9a379e ("aco/ra: fix live-range splits of phi definitions")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16454>
2022-05-30 16:41:32 +00:00
Samuel Pitoiset 2981ee5c7b radv: init states from VkPipelineFragmentShadingRateState at only one place
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16672>
2022-05-30 12:21:14 +00:00
Samuel Pitoiset 8fdc4bf3ba radv: init states from VkPipelineDiscardRectangleState at only one place
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16672>
2022-05-30 12:21:14 +00:00
Samuel Pitoiset b36bee672f radv: init states from VkAttachmentSampleCountInfo at only one place
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16672>
2022-05-30 12:21:14 +00:00
Samuel Pitoiset 23ba9a6249 radv: init states from pColorBlendState at only one place
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16672>
2022-05-30 12:21:14 +00:00
Samuel Pitoiset 1dff2a9204 radv: use AMD values for computing blend related state
This will allow to translate the function and factors earlier.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16672>
2022-05-30 12:21:14 +00:00
Samuel Pitoiset d423d1c683 radv: init states from VkPipelineRenderingCreateInfo at only one place
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16672>
2022-05-30 12:21:14 +00:00
Samuel Pitoiset 6e8e926e1b radv: init states from pDepthStencilState at only one place
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16672>
2022-05-30 12:21:14 +00:00
Samuel Pitoiset 8e9b3fabc5 radv: init states from pMultisampleState at only one place
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16672>
2022-05-30 12:21:14 +00:00
Samuel Pitoiset 1f8db57023 radv: copy viewport/scissor when initializing radv_viewport_info
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16672>
2022-05-30 12:21:14 +00:00
Tatsuyuki Ishi 250b6eb908 radv/ci: skip image.sample_texture.*_compressed_format*
These tests are flaky due to missing barriers, exposed by 211db6d333
("radv: Fix redundant subpass barriers due to erroneous comparison").

Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16762>
2022-05-30 09:18:38 +00:00
Tatsuyuki Ishi 6eb5a110dd radv/ci: Move transient_attachment_bit from fail to skip list
These tests are flaky and should not be treated as expected-fail.

This also removes the duplicates from the fail list which was breaking CTS
runner.

Fixes: cd14431b8c ("radv/ci: skip dEQP-VK.fragment_operations.transient_attachment_bit")
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16762>
2022-05-30 09:18:38 +00:00
Konstantin Seurer 8aecb3ed58 radv: Ignore transformOffset if transformData is 0
There is also a hypothetical scenario where
transformData is 0 and transformOffset is not 0
and we end up reading from transformOffset because
transform_addr is not 0.
VkAccelerationStructureBuildRangeInfoKHR spec:

If VkAccelerationStructureGeometryTrianglesDataKHR::transformData is not NULL, a single VkTransformMatrixKHR structure is consumed from VkAccelerationStructureGeometryTrianglesDataKHR::transformData, at an offset of transformOffset. This matrix describes a transformation from the space in which the vertices for all triangles in this geometry are described to the space in which the acceleration structure is defined.

Which I think means, that we should ignore
transformOffset if transformData is NULL.

Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16719>
2022-05-30 00:00:53 +00:00
Konstantin Seurer 9be00573c4 radv: Fix handling of primitiveOffset
VkAccelerationStructureBuildRangeInfoKHR spec:
If the geometry uses indices, primitiveCount × 3 indices are consumed from VkAccelerationStructureGeometryTrianglesDataKHR::indexData, starting at an offset of primitiveOffset. The value of firstVertex is added to the index values before fetching vertices.

If the geometry does not use indices, primitiveCount × 3 vertices are consumed from VkAccelerationStructureGeometryTrianglesDataKHR::vertexData, starting at an offset of primitiveOffset + VkAccelerationStructureGeometryTrianglesDataKHR::vertexStride × firstVertex.

Meaning: We always add firstVertex * vertexStride
to the vertex address and add primitiveOffset
either to the vertex address or the index address,
depending on wether indices are used.

Also add missing handling with instances.

Fixes: 0dad88b ("radv: Implement device-side BVH building.")
Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16719>
2022-05-30 00:00:53 +00:00
Tatsuyuki Ishi cd14431b8c radv/ci: skip dEQP-VK.fragment_operations.transient_attachment_bit
Until the CTS bug is fixed.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16663>
2022-05-27 09:43:04 +00:00
Tatsuyuki Ishi 211db6d333 radv: Fix redundant subpass barriers due to erroneous comparison
We accidentally compared the stencil layout to the color/depth layout.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16663>
2022-05-27 09:43:04 +00:00
Timur Kristóf 77a67f1115 radv: Add mesh and task stage names to pipeline executable properties.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16712>
2022-05-27 08:46:29 +00:00
Samuel Pitoiset 1046c2a1c0 radv: fix writing buffer markers with non-zero memory offset
Found by insepction.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16698>
2022-05-26 08:23:52 +00:00
Samuel Pitoiset 6f854ac2f2 radv: use pipeline->slab_bo in more places
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16687>
2022-05-26 08:03:33 +00:00
Samuel Pitoiset 0393cba27b radv: disable attachementFragmentShadingRate on GFX11
The VRS image no longer uses HTILE like on GFX10.3 and I don't know
yet how to program it.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16557>
2022-05-26 07:43:38 +00:00
Samuel Pitoiset 4ffc7a50cb radv: disable VK_AMD_shader_fragment_mask on GFX11
No FMASK on GFX11 which means I don't think we can expose this ext.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16557>
2022-05-26 07:43:38 +00:00
Samuel Pitoiset 779e09639b radv: configure DB_Z_INFO.NUM_SAMPLES correctly on GFX11
It affects VRS and occlusion queries.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16557>
2022-05-26 07:43:38 +00:00
Samuel Pitoiset 00c649339b radv: fix VK_BLEND_FACTOR_CONSTANT_COLOR translation on GFX11
This one was missing.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16557>
2022-05-26 07:43:38 +00:00
Samuel Pitoiset 97dc28b177 radv: fix configuring COLOR_INVALID on GFX11
It's a different bitfield but this one was missing.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16557>
2022-05-26 07:43:38 +00:00
Samuel Pitoiset aa439d7f46 radv: report adjusted LDS size for fragment shaders on GFX11
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16557>
2022-05-26 07:43:38 +00:00
Samuel Pitoiset 2fd5aa79b2 radv: use the fragment resolve path by default on GFX11
GFX11 doesn't support CB_RESOLVE which means it doesn't support the
hardware resolve path. If necessary (for arrays or integer formats)
the driver will select the compute path.

No CTS regressions by forcing the fragment resolve path on GFX10.3

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16557>
2022-05-26 07:43:38 +00:00
Samuel Pitoiset f7b1ad7c06 radv: update VRS rates on GFX11
GFX11 uses enum instead of 2-bit integer numbers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
iReviewed-by: Timur Kristóf <timur.kristof@gmail.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16557>
2022-05-26 07:43:38 +00:00
Samuel Pitoiset e210ffb4d0 radv: update framebuffer registers on GFX11
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16557>
2022-05-26 07:43:38 +00:00
Samuel Pitoiset d88c859b4e radv: do not emit more non-existent registers on GFX11
Found these by diffing the list of registers between GFX10_3 and GFX11.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16557>
2022-05-26 07:43:38 +00:00
Samuel Pitoiset c5d8ef97fa radv: rename VERT_GRP_SIZE to VERTS_PER_SUBGRP on GFX11
Same bitfield but it has been renamed.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16557>
2022-05-26 07:43:38 +00:00
Timur Kristóf 55466ca506 radv: Disable predication for supass clear and image clears.
According to the Vulkan spec 21.4 "Conditional Rendering",
only clearing attachments with vkCmdClearAttachments is subject to
conditional rendering.

Subpass clear and vkCmdClearColorImage / vkCmdClearDepthStencilImage
should always be executed even if it happens in a
conditional rendering block.

Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16654>
2022-05-25 12:59:37 +00:00
Timur Kristóf 10459522eb radv: Remove trailing whitespace.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-by: Martin Roukala <martin.roukala@mupuf.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16702>
2022-05-25 12:29:30 +00:00
Timur Kristóf abcd0aa9e5 aco: Remove trailing whitespace.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-by: Martin Roukala <martin.roukala@mupuf.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16702>
2022-05-25 12:29:30 +00:00
Timur Kristóf 5e0615c512 ac: Remove trailing white space.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-by: Martin Roukala <martin.roukala@mupuf.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16702>
2022-05-25 12:29:30 +00:00
Pierre-Eric Pelloux-Prayer 7e2874dc93 ac: reset LLVM command line parser
In some scenario ac_init_llvm_target may be called twice,
but the LLVM library won't have been unloaded between
the 2 calls, leading to a LLVM warning being printed.

Example pseudo-code to trigger this for radeonsi:
   gbm_create_device();
   eglInitialize();
   eglTerminate();
   gbm_device_destroy();
   gbm_create_device();
   eglInitialize();
   eglTerminate();
   gbm_device_destroy();

To avoid the warning message from LLVM, clear the command line
parser state before calling LLVMParseCommandLineOptions.

This might fix https://gitlab.freedesktop.org/mesa/mesa/-/issues/5960

This is done only on LLVM 12+ because it seems to break some apps
on LLVM 11 (there has been some work post LLVM 11 release to refactor
CommandLine.cpp, see 42f588f39c5c and the following commits).

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16587>
2022-05-25 12:03:34 +00:00
Pierre-Eric Pelloux-Prayer 2172ddf2bf ac: export LLVM c++ ResetCommandLineParser method
This method isn't part of the C API but we can still use it and
avoid getting error messages from the command line parser:

   mesa: for the [...]: may only occur zero or one times

We could call it at the beginning of ac_init_llvm_target but
this may hide some real bugs so let drivers call it.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16587>
2022-05-25 12:03:34 +00:00
Samuel Pitoiset 4642e268e2 radv: move active_stages to radv_graphics_pipeline
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16688>
2022-05-25 11:39:20 +00:00
Samuel Pitoiset 2e53c69d88 radv: move streamout_shader to radv_graphics_pipeline
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16688>
2022-05-25 11:39:20 +00:00
Samuel Pitoiset 98f3727d56 radv: unify radv_pipeline_has_XXX() helpers
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16688>
2022-05-25 11:39:20 +00:00
Samuel Pitoiset 6fe6570e76 radv: rename radv_cmd_state::pipeline to graphics_pipeline
To be consistent with compute pipelines.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16688>
2022-05-25 11:39:20 +00:00
Samuel Pitoiset 35af86af8c radv: move HS info and task_num_entries to the physical device
They are not logical device properties.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16688>
2022-05-25 11:39:20 +00:00
Timur Kristóf 85a4c5b351 radv: Implement conditional rendering for async compute queue.
MEC (the compute queue firmware) does not support real
predication, so we have to emulate that using COND_EXEC
packets before each dispatch.

Additionally, COND_EXEC doesn't have an inverted mode, so
in order to support inverted mode conditional rendering, we
allocate a new piece of memory in which we invert the condition.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6533
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16653>
2022-05-25 11:18:51 +00:00
Yiwei Zhang 229538d6da radv: remove VkPhysicalDeviceMemoryProperties2 workaround
This reverts 03888bf09c

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16694>
2022-05-24 23:35:28 +00:00
Timur Kristóf 743f4b995d radv: Clarify emitting graphics shader pointers.
Rename radv_emit_global_shader_pointers to radv_emit_graphics_shader_pointers
and don't call it on compute queues. Note that the registers
that this function sets, are not available on the async compute
queue anyway.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16395>
2022-05-24 15:47:13 +00:00
Timur Kristóf 84089d8c8d radv: Refactor queue state to separate structure.
In the future we'll need a 1:N mapping between radv_queue objects and
HW queues, meaning that 1 radv_queue object will need to be able to
submit to multiple queues. To do that, we'll must also maintain a different
state for each HW queue.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16395>
2022-05-24 15:47:13 +00:00
Timur Kristóf 5d3c1f4b41 radv: Pass radv_device pointer to some functions.
This will be needed for a future refactor of these functions
where we won't pass radv_queue to them anymore.
Also remove the radv_queue pointer from functions which
don't actually need it.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16395>
2022-05-24 15:47:13 +00:00
Timur Kristóf 1f2bbfdfca radv: Use a ws variable during preamble creation.
This is to prevent excessive code repetition, and hopefully make the
code a bit easier to read.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16395>
2022-05-24 15:47:13 +00:00