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ac/nir: use nir_intrinsic_load_lshs_vertex_stride_amd 

For radeonsi which pass this value by argument.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16418>
This commit is contained in:
Qiang Yu 2022-05-07 17:38:04 +08:00 committed by Marge Bot
parent 33b4b923ee
commit 6a95452ddf
4 changed files with 25 additions and 31 deletions
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7
src/amd/common/ac_nir.h
View File

@ -62,13 +62,11 @@ bool ac_nir_optimize_outputs(nir_shader *nir, bool sprite_tex_disallowed,
void
ac_nir_lower_ls_outputs_to_mem(nir_shader *ls,
bool tcs_in_out_eq,
uint64_t tcs_temp_only_inputs,
unsigned num_reserved_ls_outputs);
uint64_t tcs_temp_only_inputs);
void
ac_nir_lower_hs_inputs_to_mem(nir_shader *shader,
bool tcs_in_out_eq,
unsigned num_reserved_tcs_inputs);
bool tcs_in_out_eq);
void
ac_nir_lower_hs_outputs_to_mem(nir_shader *shader,
@ -76,7 +74,6 @@ ac_nir_lower_hs_outputs_to_mem(nir_shader *shader,
bool tes_reads_tessfactors,
uint64_t tes_inputs_read,
uint64_t tes_patch_inputs_read,
unsigned num_reserved_tcs_inputs,
unsigned num_reserved_tcs_outputs,
unsigned num_reserved_tcs_patch_outputs,
bool emit_tess_factor_write);

30
src/amd/common/ac_nir_lower_tess_io_to_mem.c
View File

@ -140,10 +140,6 @@ typedef struct {
/* Whether TES reads the tess factors. */
bool tes_reads_tessfactors;
/* Number of inputs for which memory should be reserved.
* When compacted, this should be the number of linked inputs.
*/
unsigned tcs_num_reserved_inputs;
unsigned tcs_num_reserved_outputs;
unsigned tcs_num_reserved_patch_outputs;
@ -220,7 +216,7 @@ lower_ls_output_store(nir_builder *b,
b->cursor = nir_before_instr(instr);
nir_ssa_def *vertex_idx = nir_load_local_invocation_index(b);
nir_ssa_def *base_off_var = nir_imul_imm(b, vertex_idx, st->tcs_num_reserved_inputs * 16u);
nir_ssa_def *base_off_var = nir_imul(b, vertex_idx, nir_load_lshs_vertex_stride_amd(b));
nir_ssa_def *io_off = nir_build_calc_io_offset(b, intrin, nir_imm_int(b, 16u), 4u);
unsigned write_mask = nir_intrinsic_write_mask(intrin);
@ -272,15 +268,15 @@ hs_per_vertex_input_lds_offset(nir_builder *b,
lower_tess_io_state *st,
nir_intrinsic_instr *instr)
{
unsigned tcs_in_vertex_stride = st->tcs_num_reserved_inputs * 16u;
nir_ssa_def *tcs_in_vtxcnt = nir_load_patch_vertices_in(b);
nir_ssa_def *rel_patch_id = nir_load_tess_rel_patch_id_amd(b);
nir_ssa_def *tcs_in_patch_stride = nir_imul_imm(b, tcs_in_vtxcnt, tcs_in_vertex_stride);
nir_ssa_def *tcs_in_current_patch_offset = nir_imul(b, rel_patch_id, tcs_in_patch_stride);
nir_ssa_def *vertex_index = nir_get_io_arrayed_index_src(instr)->ssa;
nir_ssa_def *vertex_index_off = nir_imul_imm(b, vertex_index, tcs_in_vertex_stride);
nir_ssa_def *stride = nir_load_lshs_vertex_stride_amd(b);
nir_ssa_def *tcs_in_patch_stride = nir_imul(b, tcs_in_vtxcnt, stride);
nir_ssa_def *vertex_index_off = nir_imul(b, vertex_index, stride);
nir_ssa_def *tcs_in_current_patch_offset = nir_imul(b, rel_patch_id, tcs_in_patch_stride);
nir_ssa_def *io_offset = nir_build_calc_io_offset(b, instr, nir_imm_int(b, 16u), 4u);
@ -302,7 +298,7 @@ hs_output_lds_offset(nir_builder *b,
nir_ssa_def *tcs_in_vtxcnt = nir_load_patch_vertices_in(b);
nir_ssa_def *tcs_num_patches = nir_load_tcs_num_patches_amd(b);
nir_ssa_def *input_patch_size = nir_imul_imm(b, tcs_in_vtxcnt, st->tcs_num_reserved_inputs * 16u);
nir_ssa_def *input_patch_size = nir_imul(b, tcs_in_vtxcnt, nir_load_lshs_vertex_stride_amd(b));
nir_ssa_def *output_patch0_offset = nir_imul(b, input_patch_size, tcs_num_patches);
nir_ssa_def *off = intrin
@ -634,13 +630,11 @@ filter_any_input_access(const nir_instr *instr,
void
ac_nir_lower_ls_outputs_to_mem(nir_shader *shader,
bool tcs_in_out_eq,
uint64_t tcs_temp_only_inputs,
unsigned num_reserved_ls_outputs)
uint64_t tcs_temp_only_inputs)
{
assert(shader->info.stage == MESA_SHADER_VERTEX);
lower_tess_io_state state = {
.tcs_num_reserved_inputs = num_reserved_ls_outputs,
.tcs_in_out_eq = tcs_in_out_eq,
.tcs_temp_only_inputs = tcs_in_out_eq ? tcs_temp_only_inputs : 0,
};
@ -653,14 +647,12 @@ ac_nir_lower_ls_outputs_to_mem(nir_shader *shader,
void
ac_nir_lower_hs_inputs_to_mem(nir_shader *shader,
bool tcs_in_out_eq,
unsigned num_reserved_tcs_inputs)
bool tcs_in_out_eq)
{
assert(shader->info.stage == MESA_SHADER_TESS_CTRL);
lower_tess_io_state state = {
.tcs_in_out_eq = tcs_in_out_eq,
.tcs_num_reserved_inputs = num_reserved_tcs_inputs,
};
nir_shader_lower_instructions(shader,
@ -675,7 +667,6 @@ ac_nir_lower_hs_outputs_to_mem(nir_shader *shader,
bool tes_reads_tessfactors,
uint64_t tes_inputs_read,
uint64_t tes_patch_inputs_read,
unsigned num_reserved_tcs_inputs,
unsigned num_reserved_tcs_outputs,
unsigned num_reserved_tcs_patch_outputs,
bool emit_tess_factor_write)
@ -687,7 +678,6 @@ ac_nir_lower_hs_outputs_to_mem(nir_shader *shader,
.tes_reads_tessfactors = tes_reads_tessfactors,
.tes_inputs_read = tes_inputs_read,
.tes_patch_inputs_read = tes_patch_inputs_read,
.tcs_num_reserved_inputs = num_reserved_tcs_inputs,
.tcs_num_reserved_outputs = num_reserved_tcs_outputs,
.tcs_num_reserved_patch_outputs = num_reserved_tcs_patch_outputs,
.tcs_out_patch_fits_subgroup = 32 % shader->info.tess.tcs_vertices_out == 0,

10
src/amd/vulkan/radv_nir_lower_abi.c
View File

@ -182,6 +182,13 @@ lower_abi_instr(nir_builder *b, nir_instr *instr, void *state)
case nir_intrinsic_load_task_ib_stride:
return ac_nir_load_arg(b, &s->args->ac, s->args->task_ib_stride);
case nir_intrinsic_load_lshs_vertex_stride_amd: {
unsigned io_num = stage == MESA_SHADER_VERTEX ?
s->info->vs.num_linked_outputs :
s->info->tcs.num_linked_inputs;
return nir_imm_int(b, io_num * 16);
}
default:
unreachable("invalid NIR RADV ABI intrinsic.");
}
@ -225,7 +232,8 @@ filter_abi_instr(const nir_instr *instr,
intrin->intrinsic == nir_intrinsic_load_ring_task_payload_amd ||
intrin->intrinsic == nir_intrinsic_load_task_ring_entry_amd ||
intrin->intrinsic == nir_intrinsic_load_task_ib_addr ||
intrin->intrinsic == nir_intrinsic_load_task_ib_stride;
intrin->intrinsic == nir_intrinsic_load_task_ib_stride ||
intrin->intrinsic == nir_intrinsic_load_lshs_vertex_stride_amd;
}
void

9
src/amd/vulkan/radv_shader.c
View File

@ -1060,7 +1060,7 @@ radv_lower_io_to_mem(struct radv_device *device, struct radv_pipeline_stage *sta
if (nir->info.stage == MESA_SHADER_VERTEX) {
if (info->vs.as_ls) {
NIR_PASS_V(nir, ac_nir_lower_ls_outputs_to_mem, info->vs.tcs_in_out_eq,
info->vs.tcs_temp_only_input_mask, info->vs.num_linked_outputs);
info->vs.tcs_temp_only_input_mask);
return true;
} else if (info->vs.as_es) {
NIR_PASS_V(nir, ac_nir_lower_es_outputs_to_mem,
@ -1068,12 +1068,11 @@ radv_lower_io_to_mem(struct radv_device *device, struct radv_pipeline_stage *sta
return true;
}
} else if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
NIR_PASS_V(nir, ac_nir_lower_hs_inputs_to_mem, info->vs.tcs_in_out_eq,
info->tcs.num_linked_inputs);
NIR_PASS_V(nir, ac_nir_lower_hs_inputs_to_mem, info->vs.tcs_in_out_eq);
NIR_PASS_V(nir, ac_nir_lower_hs_outputs_to_mem, device->physical_device->rad_info.gfx_level,
info->tcs.tes_reads_tess_factors, info->tcs.tes_inputs_read,
info->tcs.tes_patch_inputs_read, info->tcs.num_linked_inputs,
info->tcs.num_linked_outputs, info->tcs.num_linked_patch_outputs, true);
info->tcs.tes_patch_inputs_read, info->tcs.num_linked_outputs,
info->tcs.num_linked_patch_outputs, true);
return true;
} else if (nir->info.stage == MESA_SHADER_TESS_EVAL) {