KonstantinSeurer
/
mesa
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

radv: use callback for nir_lower_to_scalar 

Now uses nir_lower_alu_width.
This avoids scalarization and re-vectorization of 16bit instructions.

Totals from 289 (0.21% of 134913) affected shaders: (GFX10.3)
VGPRs: 12864 -> 13072 (+1.62%); split: -0.50%, +2.11%
SpillSGPRs: 609 -> 505 (-17.08%)
SpillVGPRs: 946 -> 1145 (+21.04%)
CodeSize: 2537024 -> 2576976 (+1.57%); split: -0.10%, +1.67%
Scratch: 89088 -> 113664 (+27.59%)
MaxWaves: 7150 -> 7134 (-0.22%)
Instrs: 458352 -> 460830 (+0.54%); split: -0.45%, +0.99%
Latency: 6615279 -> 6844092 (+3.46%); split: -0.08%, +3.54%
InvThroughput: 1929504 -> 2044989 (+5.99%); split: -0.22%, +6.21%
VClause: 7186 -> 7338 (+2.12%); split: -0.08%, +2.20%
SClause: 13144 -> 13116 (-0.21%)
Copies: 46152 -> 50127 (+8.61%); split: -0.11%, +8.73%
Branches: 16530 -> 16572 (+0.25%); split: -0.02%, +0.27%
PreSGPRs: 14903 -> 14905 (+0.01%); split: -0.01%, +0.03%
PreVGPRs: 11806 -> 11730 (-0.64%); split: -1.83%, +1.19%

Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15176>
This commit is contained in:
Daniel Schürmann 2021-07-06 19:09:51 +02:00 committed by Marge Bot
parent 4235dd7b47
commit def3690447
2 changed files with 22 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
src/amd/vulkan/radv_pipeline.c
View File

@ -4055,6 +4055,11 @@ opt_vectorize_callback(const nir_instr *instr, const void *_)
if (instr->type != nir_instr_type_alu)
return 0;
const struct radv_device *device = _;
enum amd_gfx_level chip = device->physical_device->rad_info.gfx_level;
if (chip < GFX9)
return 1;
const nir_alu_instr *alu = nir_instr_as_alu(instr);
const unsigned bit_size = alu->dest.dest.ssa.bit_size;
if (bit_size != 16)
@ -4901,7 +4906,7 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_pipeline_layout
NIR_PASS(_, stages[i].nir, nir_opt_shrink_vectors);
NIR_PASS(_, stages[i].nir, nir_lower_alu_to_scalar, NULL, NULL);
NIR_PASS(_, stages[i].nir, nir_lower_alu_width, opt_vectorize_callback, device);
/* lower ALU operations */
NIR_PASS(_, stages[i].nir, nir_lower_int64);
@ -4967,7 +4972,7 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_pipeline_layout
NIR_PASS(_, stages[i].nir, nir_opt_dce);
}
NIR_PASS(_, stages[i].nir, nir_opt_vectorize, opt_vectorize_callback, NULL);
NIR_PASS(_, stages[i].nir, nir_opt_vectorize, opt_vectorize_callback, device);
}
/* cleanup passes */

16
src/amd/vulkan/radv_shader.c
View File

@ -121,6 +121,20 @@ radv_get_nir_options(struct radv_physical_device *device)
get_nir_options_for_stage(device, stage);
}
static uint8_t
vectorize_vec2_16bit(const nir_instr *instr, const void *_)
{
if (instr->type != nir_instr_type_alu)
return 0;
const nir_alu_instr *alu = nir_instr_as_alu(instr);
const unsigned bit_size = alu->dest.dest.ssa.bit_size;
if (bit_size == 16)
return 2;
else
return 1;
}
static bool
is_meta_shader(nir_shader *nir)
{
@ -171,7 +185,7 @@ radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively, bool
NIR_PASS(progress, shader, nir_opt_dead_write_vars);
NIR_PASS(_, shader, nir_lower_vars_to_ssa);
NIR_PASS(_, shader, nir_lower_alu_to_scalar, NULL, NULL);
NIR_PASS(_, shader, nir_lower_alu_width, vectorize_vec2_16bit, NULL);
NIR_PASS(_, shader, nir_lower_phis_to_scalar, true);
NIR_PASS(progress, shader, nir_copy_prop);