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ac/gpu_info: always retile DCC on gfx10 and newer chips 

Unaligned DCC doesn't work there.

Fixes: f8cf5ea982 - amd: add support for gfx1036 and gfx1037 chips

Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16726>
This commit is contained in:
Marek Olšák 2022-05-26 11:55:08 -04:00 committed by Marge Bot
parent b35991dbcb
commit 05eb9530ca
2 changed files with 2 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/amd/common/ac_gpu_info.c
View File

@ -1120,7 +1120,8 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
if ((info->drm_minor >= 31 && (info->family == CHIP_RAVEN || info->family == CHIP_RAVEN2 ||
info->family == CHIP_RENOIR)) ||
info->gfx_level >= GFX10_3) {
if (info->max_render_backends == 1)
/* GFX10+ requires retiling in all cases. */
if (info->max_render_backends == 1 && info->gfx_level == GFX9)
info->use_display_dcc_unaligned = true;
else
info->use_display_dcc_with_retile_blit = true;

19
src/amd/common/ac_surface.c
View File

@ -358,12 +358,6 @@ bool ac_get_supported_modifiers(const struct radeon_info *info,
AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B))
if (info->gfx_level >= GFX10_3) {
if (info->max_render_backends == 1) {
ADD_MOD(AMD_FMT_MOD | common_dcc |
AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B))
}
ADD_MOD(AMD_FMT_MOD | common_dcc |
AMD_FMT_MOD_SET(DCC_RETILE, 1) |
AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
@ -373,13 +367,6 @@ bool ac_get_supported_modifiers(const struct radeon_info *info,
if (info->family == CHIP_NAVI12 || info->family == CHIP_NAVI14 || info->gfx_level >= GFX10_3) {
bool independent_128b = info->gfx_level >= GFX10_3;
if (info->max_render_backends == 1) {
ADD_MOD(AMD_FMT_MOD | common_dcc |
AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, independent_128b) |
AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B))
}
ADD_MOD(AMD_FMT_MOD | common_dcc |
AMD_FMT_MOD_SET(DCC_RETILE, 1) |
AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
@ -454,12 +441,6 @@ bool ac_get_supported_modifiers(const struct radeon_info *info,
ADD_MOD(modifier_dcc_best | AMD_FMT_MOD_SET(DCC_PIPE_ALIGN, 1));
/* Displayable modifiers are next. */
/* These two will only be used by chips with 1 RB, and they are the best choice there. */
if (info->max_render_backends == 1) {
ADD_MOD(modifier_dcc_best)
ADD_MOD(modifier_dcc_4k)
}
/* Add other displayable DCC settings. (DCC_RETILE implies displayable on all chips) */
ADD_MOD(modifier_dcc_best | AMD_FMT_MOD_SET(DCC_RETILE, 1))
ADD_MOD(modifier_dcc_4k | AMD_FMT_MOD_SET(DCC_RETILE, 1))