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radv, aco: Packed usub_sat/isub_sat. 

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>
This commit is contained in:
Georg Lehmann 2022-01-20 20:50:15 +01:00 committed by Marge Bot
parent aa9d2d8893
commit 1d815548ab
3 changed files with 14 additions and 0 deletions
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10
src/amd/compiler/aco_instruction_selection.cpp
View File

@ -2102,6 +2102,11 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr)
break;
}
case nir_op_usub_sat: {
if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) {
Instruction* sub_instr = emit_vop3p_instruction(ctx, instr, aco_opcode::v_pk_sub_u16, dst);
sub_instr->vop3p().clamp = 1;
break;
}
Temp src0 = get_alu_src(ctx, instr->src[0]);
Temp src1 = get_alu_src(ctx, instr->src[1]);
if (dst.regClass() == s1) {
@ -2179,6 +2184,11 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr)
break;
}
case nir_op_isub_sat: {
if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) {
Instruction* sub_instr = emit_vop3p_instruction(ctx, instr, aco_opcode::v_pk_sub_i16, dst);
sub_instr->vop3p().clamp = 1;
break;
}
Temp src0 = get_alu_src(ctx, instr->src[0]);
Temp src1 = get_alu_src(ctx, instr->src[1]);
if (dst.regClass() == s1) {

2
src/amd/compiler/aco_instruction_selection_setup.cpp
View File

@ -560,6 +560,8 @@ init_context(isel_context* ctx, nir_shader* shader)
case nir_op_iadd_sat:
case nir_op_uadd_sat:
case nir_op_isub:
case nir_op_isub_sat:
case nir_op_usub_sat:
case nir_op_imul:
case nir_op_imin:
case nir_op_imax:

2
src/amd/vulkan/radv_pipeline.c
View File

@ -4068,6 +4068,8 @@ opt_vectorize_callback(const nir_instr *instr, const void *_)
case nir_op_iadd_sat:
case nir_op_uadd_sat:
case nir_op_isub:
case nir_op_isub_sat:
case nir_op_usub_sat:
case nir_op_imul:
case nir_op_imin:
case nir_op_imax: