KonstantinSeurer
/
mesa
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
128,092 Commits 1 Branch 0 Tags 356 MiB
Commit Graph

4664 Commits

Author SHA1 Message Date
Marek Olšák 9e2113c6dc radeonsi: set up IBs for preemption 
- Execute cs_preamble_state as a separate IB with different flags.
- Set the PREEMPT flag for the main IB.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5798>
 2020-07-22 12:08:33 -04:00
Marek Olšák b8892bc818 radeonsi: don't restore states at the beginning of IBs if they're shadowed 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5798>
 2020-07-22 12:08:33 -04:00
Marek Olšák 95c9048591 radeonsi: add debug code for register shadowing 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5798>
 2020-07-22 12:08:33 -04:00
Marek Olšák 8af0f91fd3 radeonsi: add reg shadowing codepaths to GS and tess ring setup 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5798>
 2020-07-22 12:08:33 -04:00
Marek Olšák 69014d8c94 radeonsi: implement CP register shadowing 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5798>
 2020-07-22 12:08:19 -04:00
Marek Olšák b84dbd2936 radeonsi: reorder code in update_gs_ring_buffers and init_tess_factor_ring 
to reduce the churn when adding codepaths for shadowed registers

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5798>
 2020-07-22 12:08:19 -04:00
Marek Olšák babd87f2e0 radeonsi: make cs_preamble_state optional 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5798>
 2020-07-22 12:08:19 -04:00
Marek Olšák 976edae839 radeonsi: sort registers in si_init_cs_preamble_state according to GPU gen 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5798>
 2020-07-22 12:08:19 -04:00
Marek Olšák 88fe9dea7a radeonsi: sort registers in si_emit_initial_compute_regs according to GPU gen 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5798>
 2020-07-22 12:08:19 -04:00
Marek Olšák 1c6eca23fd radeonsi/gfx10: set the correct value for OFFCHIP_BUFFERING 
Copied from PAL. Higher values break tessellation, which I was only able
to reproduce with register shadowing enabled.

Fixes: 0bf3e6fae7 "radeonsi/gfx10: double the number of tessellation offchip buffers per SE"

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5798>
 2020-07-22 12:08:19 -04:00
Marek Olšák d244a25c07 radeonsi: add missing initialization of registers 
(random initial gfx10 commit:)
Fixes: 78cdf9a99f - amd/addrlib: add gfx10 support

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5798>
 2020-07-22 12:08:19 -04:00
Bas Nieuwenhuizen 7b7917a424 radeonsi: Inhibit clock-gating for perf counters. 
Otherwise most counters return 0. Should be much more user friendly
than having to totally disable clock-gating on the kernel cmdline.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5972>
 2020-07-20 23:56:26 +00:00
Pierre-Eric Pelloux-Prayer d2a3ca289f radeonsi: adjust epitch for PIPE_FORMAT_R8G8_R8B8_UNORM 
This fix si_compute_copy_image for yuyv image (so using PIPE_FORMAT_R8G8_R8B8_UNORM).

With this change, the following gst pipeline produce the expected results for various
image sizes (with or without AMD_DEBUG=nodma):

gst-launch-1.0 filesrc location=input.jpg ! jpegparse ! vaapijpegdec ! filesink location=output.yuv

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5841>
 2020-07-20 10:32:44 +00:00
Thong Thai 045711dc1c radeonsi: use PIPE_FORMAT_P010 for 10-bit VP9 decoding 
Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Leo Liu <leoliu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5848>
 2020-07-16 17:52:20 +00:00
Marek Olšák 081691b5ae radeonsi: prevent a gfx10_ngg_calculate_subgroup_info failure for TES+NGG GS 
arb_tessellation_shader-tes-gs-max-output -small -scan 1 50 -auto -fbo
doesn't pass, but at least all shaders are compiled successfully.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5700>
 2020-07-16 04:04:52 +00:00
Timothy Arceri bba766d85d radeonsi: fix SI_NUM_ATOMS 
This is not used anywhere so maybe we should just drop it instead.

Fixes: 639b673fc3 ("radeonsi: don't use an indirect table for state atoms")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5766>
 2020-07-08 03:04:03 +00:00
Timothy Arceri 4686a95621 r600/radeonsi: silence zero-length-bounds gcc warnings 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5766>
 2020-07-08 03:04:03 +00:00
Marek Olšák 75b59bb1d6 gallium: add PIPE_SHADER_CAP_GLSL_16BIT_TEMPS for LowerPrecisionTemporaries 
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5746>
 2020-07-07 22:02:06 -04:00
Timothy Arceri cb5fafd617 radeonsi: add missing fallthrough comment 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5705>
 2020-07-02 23:52:52 +00:00
Marek Olšák 50d7553600 radeonsi: add a debug option to enable NGG culling for tessellation 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5524>
 2020-06-30 10:56:41 +00:00
Marek Olšák b0c77a5f1d radeonsi: don't try to enable NGG culling for GS 
It doesn't do anything.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5524>
 2020-06-30 10:56:41 +00:00
Marek Olšák 90cf741d31 radeonsi: always use Wave64 for HS/GS/VS shader stages (except GS fast launch) 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5524>
 2020-06-30 10:56:41 +00:00
Marek Olšák 9049e39804 radeonsi: always use Wave32 for GS fast launch, because Wave64 hangs 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5524>
 2020-06-30 10:56:41 +00:00
Marek Olšák 8fff9beb44 radeonsi: fix NGG culling for Wave64 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5524>
 2020-06-30 10:56:41 +00:00
Marek Olšák 1401fc055c radeonsi: don't flush in fence_server_sync 
This reverts commit 50b06cbc10 and fixes
an Android performance regression.

Fixes: 50b06cbc10 "radeonsi: fix fence_server_sync() holding up extra work v2"

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5602>
 2020-06-30 06:38:50 -04:00
Pierre-Eric Pelloux-Prayer 5a05f9714b radeonsi: bump SI_NUM_SHADER_BUFFERS to 32 
Some app uses more than 8 SSBOs (https://gitlab.freedesktop.org/mesa/mesa/-/issues/2946),
so increase SI_NUM_SHADER_BUFFERS to 32 (which allows 16 SSBOs).

Since we're now using a 64 bits number to track buffers, we could bump
SI_NUM_SHADER_BUFFERS to 48 but that would conflict with Mesa's
MAX_COMBINED_ATOMIC_BUFFERS limit (= 90).

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2122
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5632>
 2020-06-30 09:23:14 +02:00
Marek Olšák 71794567f9 radeonsi: remove tabs 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
 2020-06-26 07:02:57 +00:00
Marek Olšák 0cdec11d95 radeonsi: clear per-context buffers at the end of si_create_context 
We don't want any packets before CONTEXT_CONTROL.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
 2020-06-26 07:02:57 +00:00
Marek Olšák da78d50bc8 radeonsi: make si_pm4_cmd_begin/end static and simplify all usages 
There is no longer the confusing trailing si_pm4_cmd_end call.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
 2020-06-26 07:02:57 +00:00
Marek Olšák 7b2a0f880b radeonsi: disallow adding BOs into si_pm4_state except 1 shader BO per state 
The si_shader pointer is already there, so use it and remove the array
of BOs.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
 2020-06-26 07:02:57 +00:00
Marek Olšák 3b1e42d2c2 radeonsi: make wait_mem_scratch unmappable 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
 2020-06-26 07:02:57 +00:00
Marek Olšák 428360662f radeonsi: don't add the tess ring buffers into the cs_preamble state 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
 2020-06-26 07:02:57 +00:00
Marek Olšák 1c1d34a67a radeonsi: rename init_config states to cs_preamble states 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
 2020-06-26 07:02:57 +00:00
Marek Olšák bbc0a2d51d radeonsi: don't add the border color buffer into the init_config state 
We might have to replace init_config for preemption.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
 2020-06-26 07:02:57 +00:00
Marek Olšák f8e8701cf1 radeonsi: replace ctx->screen with sscreen in si_flush_gfx_cs 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5506>
 2020-06-23 09:12:16 +00:00
Marek Olšák 470b319813 radeonsi: don't wait for idle at the end of gfx IBs 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5506>
 2020-06-23 09:12:16 +00:00
Marek Olšák 3fec2f67c3 radeonsi: compact MRTs to save PS export memory space 
If there are holes between color outputs (e.g. a shader exports MRT1, but
not MRT0), we can remove the holes by moving higher MRTs lower.

The hardware will remap the MRTs to their correct locations if we remove
holes in SPI_SHADER_COL_FORMAT but not CB_SHADER_MASK.

This is a performance optimization, but MRTs with holes are pretty rare,
so there is most likely no effect on any app.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5535>
 2020-06-23 00:23:51 -04:00
Eric Engestrom 2ef983dca6 driconf: drop now unused translation facility 
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5440>
 2020-06-22 21:50:12 +00:00
Neil Roberts bb5fc90135 gallium: Add pipe cap for primitive restart with fixed index 
Adds PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX which is a subset of the
primitive restart cap for when the hardware can only support the fixed
indices specified in GLES.

The switch statements were automatically modified with this command:

find \( \( -name \*.cpp -o -name \*.c \) \! -type l \) \
 -exec sed -i -r \
 's/^(\s*case\s+PIPE_CAP_PRIMITIVE_RESTART)\s*:.*$/\0\n\1_FIXED_INDEX:/' \
 {} \;

v2: Add a note in screen.rst

Reviewed-by: Eric Anholt <eric@anholt.net> (v1)
Reviewed by: Erik Faye-Lund <erik.faye-lund@collabora.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5559>
 2020-06-22 12:41:56 +00:00
Thong Thai 9d5d4f9eaa radeon/vcn: add vcn 3.0 encode support 
Signed-off-by: Thong Thai <thong.thai@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5501>
 2020-06-18 09:58:03 -04:00
Samuel Pitoiset 013d096d15 ac: add ac_choose_spi_color_formats() to common code 
It's similar between RADV and RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5436>
 2020-06-15 08:16:07 +02:00
Marek Olšák bd553f0546 ac/surface: cache DCC retile maps (v2) 
This reduces overhead when resizing windows or when allocating
similar image sizes over and over again.

v2: optimize the memory footprint of the cache

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5398>
 2020-06-10 15:35:46 +00:00
Pierre-Eric Pelloux-Prayer 24ceb6a594 radeonsi/ngg: try GS multi-cycling mode if default mode failed 
If gsprim_lds_size is larger than target_lds_size then gfx10_ngg_calculate_subgroup_info
will fail.

This commit adds a logic to try the multi-cycling in this case because it's
using less memory.

This fix glsl-1.50-gs-max-output when using NGG.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5401>
 2020-06-10 09:33:58 +02:00
Pierre-Eric Pelloux-Prayer ce7692fc19 radeonsi: add return value to gfx10_ngg_calculate_subgroup_info 
gfx10_ngg_calculate_subgroup_info uses assert to detect invalid configuration,
but if asserts are disabled it will continue its execution.

This commits adds a boolean return value to let the caller know that something
went wrong and that the results mustn't be used.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3103
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5401>
 2020-06-10 09:33:48 +02:00
Marek Olšák 0795241dde radeonsi: require LLVM 11 for gfx10.3 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5383>
 2020-06-09 16:17:36 +00:00
Marek Olšák 789cdab3b6 ac: align num_vgprs for gfx10.3 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5383>
 2020-06-09 16:17:36 +00:00
Marek Olšák 2cc4bfbe01 radeonsi: don't set any XNACK options on gfx10.3 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5383>
 2020-06-09 16:17:36 +00:00
Marek Olšák 430d384c31 radeonsi: set BIG_PAGE fields on gfx10.3 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5383>
 2020-06-09 16:17:36 +00:00
Marek Olšák 7edf15ad47 radeonsi: move L2_CACHE_CONTROL registers into si_emit_framebuffer_state 
the next commit will set more fields.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5383>
 2020-06-09 16:17:36 +00:00
Marek Olšák 788696c7b2 radeonsi: implement R9G9B9E5 render target and image store support on gfx10.3 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5383>
 2020-06-09 16:17:36 +00:00
Marek Olšák a54bcb9429 radeonsi: enable larger SDMA clears and copies on gfx10.3 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5383>
 2020-06-09 16:17:36 +00:00
Marek Olšák c4b5fd9ab0 radeonsi: honor a user-specified pitch on gfx10.3 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5383>
 2020-06-09 16:17:36 +00:00
Marek Olšák a23802bcb9 ac,radeonsi: start adding support for gfx10.3 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5383>
 2020-06-09 16:17:36 +00:00
Marek Olšák a1602516d7 ac,radeonsi: replace == GFX10 with >= GFX10 where it's needed 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5383>
 2020-06-09 16:17:36 +00:00
Timothy Arceri 04dbf709ed nir: add callback to nir_remove_dead_variables() 
This allows us to do API specific checks before removing variable
without filling nir_remove_dead_variables() with API specific code.

In the following patches we will use this to support the removal
of dead uniforms in GLSL.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4797>
 2020-06-03 02:22:23 +00:00
Bas Nieuwenhuizen b351a50763 radeonsi: Define gfx10_format in the common header. 
So we don't have to have multiple definitions of the struct when
sharing with radv.

While at it put the table properly in a C file so we don't have to
deal with multiple definitions, and the struct definition isn't
in generated source.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5291>
 2020-06-03 00:17:00 +00:00
Bas Nieuwenhuizen c98e52f88a amd/common,radeonsi: Move gfx10_format_table to common. 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5291>
 2020-06-03 00:17:00 +00:00
Bas Nieuwenhuizen d936f69677 radeonsi: Explicitly map Z16_UNORM_S8_UINT to None for GFX10. 
We should always use separate planes for textures with this format.

Fixes: 273ead81f1 "util/format: Add VK_FORMAT_D16_UNORM_S8_UINT."
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5291>
 2020-06-03 00:17:00 +00:00
Marek Olšák fe3947632c radeonsi: add a hack to disable TRUNC_COORD for shadow samplers 
This fixes dEQP-GLES3.functional.shaders.texture_functions.textureprojlodoffset.sampler2dshadow_vertex.

This is probably a dEQP bug.

Fixes: d573d1d825

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5209>
 2020-06-02 20:47:49 +00:00
Marek Olšák 85a6bcca61 radeonsi: pass at most 3 images and/or shader buffers via user SGPRs for compute 
This should slightly decrease shader lifetime.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5209>
 2020-06-02 20:47:49 +00:00
Marek Olšák 877c56bfdc radeonsi: remove const_buffers_declared hacks 
This was a bug that was uncovered by 4553fc66a5.

Piglit: spec@arb_uniform_buffer_object@maxblocks

Fixes: 4553fc66a5

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5209>
 2020-06-02 20:47:49 +00:00
Marek Olšák ce4575b3b5 radeonsi: remove unused leftover code for INDIRECT_BUFFER inside IBs 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5209>
 2020-06-02 20:47:49 +00:00
Marek Olšák cac24bee62 nir: gather which images are MSAA 
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5209>
 2020-06-02 20:47:49 +00:00
Marek Olšák c3e0ba52a0 ac/nir: support 16-bit data in buffer_load_format opcodes 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5003>
 2020-06-02 16:29:25 -04:00
Marek Olšák b819ba949b ac/nir: remove type and num_channels args from ac_build_buffer_store_common 
They were only used for type overloading where we can just use
the type of data.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5003>
 2020-06-02 16:29:25 -04:00
Marek Olšák e5ea87cde8 ac/nir: use more types from ac_llvm_context 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5003>
 2020-06-02 16:29:25 -04:00
Marek Olšák 1af8fe4ed5 gallium: add shader caps INT16 and FP16_DERIVATIVES 
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5002>
 2020-06-02 20:01:18 +00:00
Dylan Baker a8e2d79e02 meson: use gnu_symbol_visibility argument 
This uses a meson builtin to handle -fvisibility=hidden. This is nice
because we don't need to track which languages are used, if C++ is
suddenly added meson just does the right thing.

Acked-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4740>
 2020-06-01 18:59:18 +00:00
Marek Olšák 38a4b86145 radeonsi/gfx10: implement most performance counters 
PAL has all of them.

GE perf counters don't work - no idea why.
I only tested the few that I like to use.

There is no documentation, though most of the enums had already been
in the headers.

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5184>
 2020-05-26 06:00:54 -04:00
Marek Olšák 2a3806ffa3 amd: replace SH -> SA (shader array) in comments 
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5184>
 2020-05-26 06:00:54 -04:00
Marek Olšák 2cf46f2e3d ac/gpu_info: replace num_good_cu_per_sh with min/max_good_cu_per_sa 
Perf counters use the new max number.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5184>
 2020-05-26 06:00:54 -04:00
Marek Olšák 8c3fe285c9 radeonsi: don't hardcode most perf counter block counts 
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5184>
 2020-05-26 06:00:54 -04:00
Eric Engestrom 444138d6d9 tree-wide: fix deprecated GitLab URLs 
They will stop working in the next GitLab release, so let's update them
ASAP to make sure things are propagated to everyone by then.

See:
https://about.gitlab.com/releases/2020/05/06/gitlab-com-13-0-breaking-changes/#removal-of-deprecated-project-paths

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5111>
 2020-05-23 15:33:50 +00:00
Marek Olšák 9375e72d8d radeonsi/gfx8: enable TC-compatible HTILE from the beginning as before 
Fixes: 0d83e7f4b9 - radeonsi: enable TC-compatible HTILE on demand for best Z/S performance
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2921
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2967

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5095>
 2020-05-23 03:45:07 -04:00
Marek Olšák d30e1e486d radeonsi: don't enable TC-compatible HTILE for stencil if stencil doesn't use it 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5095>
 2020-05-23 03:45:09 -04:00
Marek Olšák caeb44aa24 radeonsi: split si_all_descriptors_begin_new_cs and rename functions 
A future commit will extend it.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5095>
 2020-05-23 03:45:07 -04:00
Marek Olšák 7b6b35c6b5 radeonsi: move resetting tracked registers into a new function 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5095>
 2020-05-23 03:45:07 -04:00
Marek Olšák 3509d3bd53 ac: update register and packet definitions for preemption 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5095>
 2020-05-23 03:45:07 -04:00
Marek Olšák 56af131f33 Revert "radeonsi: don't wait for idle at the end of gfx IBs" 
This reverts commit 266fec1307.

The kernel doesn't wait for idle as part of implicit sync.

Fixes: 266fec1307
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2950

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5095>
 2020-05-23 03:44:44 -04:00
Marek Olšák 3f1f23239a radeonsi: decrease the max GS invocation count to 32 
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5095>
 2020-05-23 03:44:44 -04:00
Marek Olšák 3cd96b5109 radeonsi: don't use INDIRECT_BUFFER within IBs 
It's fragile. If I change the size or alignment, it hangs. Better safe than
sorry.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5095>
 2020-05-23 03:44:44 -04:00
Pierre-Eric Pelloux-Prayer e75effc629 radeonsi/sdma: remove useless compare 
clang warning:
   result of comparison of constant 65536 with expression of type 'uint16_t'
   (aka 'unsigned short') is always true

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5119>
 2020-05-22 09:12:18 +02:00
Pierre-Eric Pelloux-Prayer d92ab0e763 radeonsi: fix inversed arguments in si_test_gds_memory_management 
clang warning:
   implicit conversion from enumeration type 'enum radeon_bo_usage'
   to different enumeration type 'enum radeon_bo_domain'

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5119>
 2020-05-22 09:12:06 +02:00
Michel Dänzer 2a6811f0f9 Revert "ac,radeonsi: fix compilations issues with LLVM 11" 
This reverts commit 42b1696ef6.

The corresponding LLVM changes were reverted.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5087>
 2020-05-19 07:19:35 +00:00
Marek Olšák c9ccceff10 radeonsi: test uncached clear/copy buffer performance with compute shaders 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4935>
 2020-05-15 22:12:35 +00:00
Marek Olšák 5acf99e81f radeonsi: compute perf tests - don't test 1 wave/SA limit, test no limit first 
1 wave/SA is always slow and thus not useful

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4935>
 2020-05-15 22:12:35 +00:00
Marek Olšák c45a2145f5 radeonsi: disable the L2 cache for CPU read mappings of buffers 
for faster copying over PCIe and no need to flush L2

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4935>
 2020-05-15 22:12:35 +00:00
Marek Olšák 7356144fe4 radeonsi: disable the L2 cache for most CPU mappings of textures 
for faster blits over PCIe and no need to flush L2

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4935>
 2020-05-15 22:12:35 +00:00
Marek Olšák cbbc18bc67 radeonsi: use display_dcc_offset for setting displayable_dcc_cb_mask 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4935>
 2020-05-15 22:12:35 +00:00
Marek Olšák b5ac9d18d8 radeonsi: use vi_dcc_enabled instead of using tex->surface.dcc_offset directly 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4935>
 2020-05-15 22:12:35 +00:00
Marek Olšák 2c4c1b0499 radeonsi: rename SI_RESOURCE_FLAG_TRANSFER to FORCE_LINEAR 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4935>
 2020-05-15 22:12:35 +00:00
Marek Olšák 4907bb44c3 radeonsi: simplify setting resource usage for si_init_temp_resource_from_box 
usage was set twice, once in the function, and then after the function

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4935>
 2020-05-15 22:12:35 +00:00
Marek Olšák f57276309b radeonsi: tweak clear/copy_buffer limits when to use compute 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4935>
 2020-05-15 22:12:35 +00:00
Marek Olšák b158b117e1 radeonsi: optimize access pattern for compute blits with linear textures 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4935>
 2020-05-15 22:12:35 +00:00
Marek Olšák 9f8089139f radeonsi: use correct clear value size for EQAA in expand_fmask 
based on the fmask_expand_values array.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4935>
 2020-05-15 22:12:35 +00:00
Joshua Ashton d573d1d825 radeonsi: Use TRUNC_COORD on samplers 
The default behaviour (0) is: "round-nearest-even to n.6 and drop fraction when point sampling" whereas the OpenGL spec simply wants us to floor it (1) "truncate when point sampling".
See 8.14.2 in the OpenGL spec:

https://www.khronos.org/registry/OpenGL/specs/gl/glspec46.core.pdf

The Direct3D spec also mandates this (https://microsoft.github.io/DirectX-Specs/d3d/archive/D3D11_3_FunctionalSpec.htm#7.18.7%20Point%20Sample%20Addressing)

On WineD3D:
This fixes some point-sampling texture precision issues in some Direct3D 9 titles such as Guild Wars 2 and htoL#NiQ: The Firefly Diary that are not present on other vendors.

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3953>
 2020-05-15 21:56:44 +00:00
Marek Olšák f80d653d70 radeonsi: don't expose 16xAA on chips with 1 RB due to an occlusion query issue 
Only Stoney and Raven2 are affected.

Cc: 20.0 20.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5047>
 2020-05-15 21:04:55 +00:00
Marek Olšák 1152af2eda radeonsi: also enable tgsi_to_nir caching for compute shaders 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4993>
 2020-05-13 19:43:05 +00:00
Axel Davy 45e69e7d11 radeonsi: Enable tgsi to nir disk cache 
Enable the tgsi to nir cache for radeonsi.

Signed-off-by: Axel Davy <davyaxel0@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4993>
 2020-05-13 19:43:05 +00:00
Axel Davy 522bd414f3 ttn: Add new allow_disk_cache parameter 
For now this parameter doesn't do anything.
It means the implementation is allowed to use
a cache on disk.

Signed-off-by: Axel Davy <davyaxel0@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4993>
 2020-05-13 19:43:05 +00:00