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radeonsi: sort registers in si_emit_initial_compute_regs according to GPU gen 

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5798>
This commit is contained in:
Marek Olšák 2020-07-07 00:02:19 -04:00
parent 1c6eca23fd
commit 88fe9dea7a
1 changed files with 25 additions and 31 deletions
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56
src/gallium/drivers/radeonsi/si_compute.c
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@ -351,7 +351,7 @@ static void si_set_global_binding(struct pipe_context *ctx, unsigned first, unsi
void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf *cs)
{
uint64_t bc_va;
uint64_t bc_va = sctx->border_color_buffer->gpu_address;
radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
/* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1,
@ -359,6 +359,20 @@ void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf
radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
if (sctx->chip_class == GFX6) {
/* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
* and is now per pipe, so it should be handled in the
* kernel if we want to use something other than the default value.
*
* TODO: This should be:
* (number of compute units) * 4 * (waves per simd) - 1
*/
radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID, 0x190 /* Default value */);
if (sctx->screen->info.si_TA_CS_BC_BASE_ADDR_allowed)
radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR, bc_va >> 8);
}
if (sctx->chip_class >= GFX7) {
/* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
radeon_set_sh_reg_seq(cs, R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
@ -370,40 +384,11 @@ void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf
radeon_set_sh_reg(cs, R_00B82C_COMPUTE_PERFCOUNT_ENABLE, 0);
radeon_set_sh_reg(cs, R_00B878_COMPUTE_THREAD_TRACE_ENABLE, 0);
}
}
if (sctx->chip_class >= GFX10) {
radeon_set_sh_reg(cs, R_00B890_COMPUTE_USER_ACCUM_0, 0);
radeon_set_sh_reg(cs, R_00B894_COMPUTE_USER_ACCUM_1, 0);
radeon_set_sh_reg(cs, R_00B898_COMPUTE_USER_ACCUM_2, 0);
radeon_set_sh_reg(cs, R_00B89C_COMPUTE_USER_ACCUM_3, 0);
radeon_set_sh_reg(cs, R_00B8A0_COMPUTE_PGM_RSRC3, 0);
radeon_set_sh_reg(cs, R_00B9F4_COMPUTE_DISPATCH_TUNNEL, 0);
}
/* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
* and is now per pipe, so it should be handled in the
* kernel if we want to use something other than the default value,
* which is now 0x22f.
*/
if (sctx->chip_class <= GFX6) {
/* XXX: This should be:
* (number of compute units) * 4 * (waves per simd) - 1 */
radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID, 0x190 /* Default value */);
}
/* Set the pointer to border colors. */
bc_va = sctx->border_color_buffer->gpu_address;
if (sctx->chip_class >= GFX7) {
/* Set the pointer to border colors. */
radeon_set_uconfig_reg_seq(cs, R_030E00_TA_CS_BC_BASE_ADDR, 2);
radeon_emit(cs, bc_va >> 8); /* R_030E00_TA_CS_BC_BASE_ADDR */
radeon_emit(cs, S_030E04_ADDRESS(bc_va >> 40)); /* R_030E04_TA_CS_BC_BASE_ADDR_HI */
} else {
if (sctx->screen->info.si_TA_CS_BC_BASE_ADDR_allowed) {
radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR, bc_va >> 8);
}
}
/* cs_preamble_state initializes this for the gfx queue, so only do this
@ -414,6 +399,15 @@ void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf
radeon_set_uconfig_reg(cs, R_0301EC_CP_COHER_START_DELAY,
sctx->chip_class >= GFX10 ? 0x20 : 0);
}
if (sctx->chip_class >= GFX10) {
radeon_set_sh_reg(cs, R_00B890_COMPUTE_USER_ACCUM_0, 0);
radeon_set_sh_reg(cs, R_00B894_COMPUTE_USER_ACCUM_1, 0);
radeon_set_sh_reg(cs, R_00B898_COMPUTE_USER_ACCUM_2, 0);
radeon_set_sh_reg(cs, R_00B89C_COMPUTE_USER_ACCUM_3, 0);
radeon_set_sh_reg(cs, R_00B8A0_COMPUTE_PGM_RSRC3, 0);
radeon_set_sh_reg(cs, R_00B9F4_COMPUTE_DISPATCH_TUNNEL, 0);
}
}
static bool si_setup_compute_scratch_buffer(struct si_context *sctx, struct si_shader *shader,