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amd/addrlib: add gfx10 support 

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Marek Olšák 2019-06-19 20:42:18 -04:00
parent 112bf7f900
commit 78cdf9a99f
19 changed files with 12176 additions and 40 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/amd/Makefile.sources
View File

@ -23,6 +23,10 @@ ADDRLIB_FILES = \
addrlib/src/core/coord.h \
addrlib/src/gfx9/gfx9addrlib.cpp \
addrlib/src/gfx9/gfx9addrlib.h \
addrlib/src/gfx10/gfx10addrlib.cpp \
addrlib/src/gfx10/gfx10addrlib.h \
addrlib/src/gfx10/gfx10SwizzlePattern.h \
addrlib/src/chip/gfx10/gfx10_gb_reg.h \
addrlib/src/chip/gfx9/gfx9_gb_reg.h \
addrlib/src/chip/r800/si_gb_reg.h \
addrlib/src/r800/ciaddrlib.cpp \

10
src/amd/addrlib/inc/addrinterface.h
View File

@ -2266,17 +2266,17 @@ ADDR_E_RETURNCODE ADDR_API AddrComputeDccInfo(
/**
****************************************************************************************************
* ADDR_GET_MAX_ALINGMENTS_OUTPUT
* ADDR_GET_MAX_ALIGNMENTS_OUTPUT
*
* @brief
* Output structure of AddrGetMaxAlignments
****************************************************************************************************
*/
typedef struct _ADDR_GET_MAX_ALINGMENTS_OUTPUT
typedef struct _ADDR_GET_MAX_ALIGNMENTS_OUTPUT
{
UINT_32 size; ///< Size of this structure in bytes
UINT_32 baseAlign; ///< Maximum base alignment in bytes
} ADDR_GET_MAX_ALINGMENTS_OUTPUT;
} ADDR_GET_MAX_ALIGNMENTS_OUTPUT;
/**
****************************************************************************************************
@ -2288,7 +2288,7 @@ typedef struct _ADDR_GET_MAX_ALINGMENTS_OUTPUT
*/
ADDR_E_RETURNCODE ADDR_API AddrGetMaxAlignments(
ADDR_HANDLE hLib,
ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut);
ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut);
/**
****************************************************************************************************
@ -2300,7 +2300,7 @@ ADDR_E_RETURNCODE ADDR_API AddrGetMaxAlignments(
*/
ADDR_E_RETURNCODE ADDR_API AddrGetMaxMetaAlignments(
ADDR_HANDLE hLib,
ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut);
ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut);
/**
****************************************************************************************************

7
src/amd/addrlib/meson.build
View File

@ -37,7 +37,11 @@ files_addrlib = files(
'src/core/coord.h',
'src/gfx9/gfx9addrlib.cpp',
'src/gfx9/gfx9addrlib.h',
'src/gfx10/gfx10addrlib.cpp',
'src/gfx10/gfx10addrlib.h',
'src/gfx10/gfx10SwizzlePattern.h',
'src/amdgpu_asic_addr.h',
'src/chip/gfx10/gfx10_gb_reg.h',
'src/chip/gfx9/gfx9_gb_reg.h',
'src/chip/r800/si_gb_reg.h',
'src/r800/ciaddrlib.cpp',
@ -54,8 +58,9 @@ libamdgpu_addrlib = static_library(
include_directories : [
include_directories(
'inc', 'src', 'src/core', 'src/chip/gfx9', 'src/chip/r800',
'src/chip/gfx10',
),
inc_amd_common, inc_common, inc_src,
],
cpp_args : cpp_vis_args,
cpp_args : [cpp_vis_args, '-Wno-unused-variable'],
)

4
src/amd/addrlib/src/addrinterface.cpp
View File

@ -1070,7 +1070,7 @@ ADDR_E_RETURNCODE ADDR_API AddrComputePrtInfo(
*/
ADDR_E_RETURNCODE ADDR_API AddrGetMaxAlignments(
ADDR_HANDLE hLib, ///< address lib handle
ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut) ///< [out] output structure
ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut) ///< [out] output structure
{
Addr::Lib* pLib = Lib::GetLib(hLib);
@ -1101,7 +1101,7 @@ ADDR_E_RETURNCODE ADDR_API AddrGetMaxAlignments(
*/
ADDR_E_RETURNCODE ADDR_API AddrGetMaxMetaAlignments(
ADDR_HANDLE hLib, ///< address lib handle
ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut) ///< [out] output structure
ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut) ///< [out] output structure
{
Addr::Lib* pLib = Lib::GetLib(hLib);

6
src/amd/addrlib/src/amdgpu_asic_addr.h
View File

@ -43,6 +43,7 @@
#define FAMILY_CZ 0x87
#define FAMILY_AI 0x8D
#define FAMILY_RV 0x8E
#define FAMILY_NV 0x8F
// AMDGPU_FAMILY_IS(familyId, familyName)
#define FAMILY_IS(f, fn) (f == FAMILY_##fn)
@ -55,6 +56,7 @@
#define FAMILY_IS_CZ(f) FAMILY_IS(f, CZ)
#define FAMILY_IS_AI(f) FAMILY_IS(f, AI)
#define FAMILY_IS_RV(f) FAMILY_IS(f, RV)
#define FAMILY_IS_NV(f) FAMILY_IS(f, NV)
#define AMDGPU_UNKNOWN 0xFF
@ -92,6 +94,8 @@
#define AMDGPU_RAVEN_RANGE 0x01, 0x81
#define AMDGPU_RAVEN2_RANGE 0x81, 0xFF
#define AMDGPU_NAVI10_RANGE 0x01, 0xFF
#define AMDGPU_EXPAND_FIX(x) x
#define AMDGPU_RANGE_HELPER(val, min, max) ((val >= min) && (val < max))
#define AMDGPU_IN_RANGE(val, ...) AMDGPU_EXPAND_FIX(AMDGPU_RANGE_HELPER(val, __VA_ARGS__))
@ -134,4 +138,6 @@
#define ASICREV_IS_RAVEN(r) ASICREV_IS(r, RAVEN)
#define ASICREV_IS_RAVEN2(r) ASICREV_IS(r, RAVEN2)
#define ASICREV_IS_NAVI10_P(r) ASICREV_IS(r, NAVI10)
#endif // _AMDGPU_ASIC_ADDR_H

72
src/amd/addrlib/src/chip/gfx10/gfx10_gb_reg.h Normal file
View File

@ -0,0 +1,72 @@
/*
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
#if !defined (__GFX10_GB_REG_H__)
#define __GFX10_GB_REG_H__
/*
* gfx10_gb_reg.h
*
* Register Spec Release: 1.0
*
*/
//
// Make sure the necessary endian defines are there.
//
#include "util/u_endian.h"
#if defined(PIPE_ARCH_LITTLE_ENDIAN)
#define LITTLEENDIAN_CPU
#elif defined(PIPE_ARCH_BIG_ENDIAN)
#define BIGENDIAN_CPU
#endif
union GB_ADDR_CONFIG
{
struct
{
#if defined(LITTLEENDIAN_CPU)
unsigned int NUM_PIPES : 3;
unsigned int PIPE_INTERLEAVE_SIZE : 3;
unsigned int MAX_COMPRESSED_FRAGS : 2;
unsigned int NUM_PKRS : 3;
unsigned int : 21;
#elif defined(BIGENDIAN_CPU)
unsigned int : 21;
unsigned int NUM_PKRS : 3;
unsigned int MAX_COMPRESSED_FRAGS : 2;
unsigned int PIPE_INTERLEAVE_SIZE : 3;
unsigned int NUM_PIPES : 3;
#endif
} bitfields, bits;
unsigned int u32All;
int i32All;
float f32All;
};
#endif

25
src/amd/addrlib/src/chip/gfx9/gfx9_gb_reg.h
View File

@ -1,6 +1,3 @@
#if !defined (__GFX9_GB_REG_H__)
#define __GFX9_GB_REG_H__
/*
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
@ -27,6 +24,19 @@
* of the Software.
*/
#if !defined (__GFX9_GB_REG_H__)
#define __GFX9_GB_REG_H__
/*
* gfx9_gb_reg.h
*
* Register Spec Release: 1.0
*
*/
//
// Make sure the necessary endian defines are there.
//
#include "util/u_endian.h"
#if defined(PIPE_ARCH_LITTLE_ENDIAN)
@ -35,15 +45,6 @@
#define BIGENDIAN_CPU
#endif
//
// Make sure the necessary endian defines are there.
//
#if defined(LITTLEENDIAN_CPU)
#elif defined(BIGENDIAN_CPU)
#else
#error "BIGENDIAN_CPU or LITTLEENDIAN_CPU must be defined"
#endif
union GB_ADDR_CONFIG {
struct {
#if defined(LITTLEENDIAN_CPU)

26
src/amd/addrlib/src/chip/r800/si_gb_reg.h
View File

@ -1,6 +1,3 @@
#if !defined (__SI_GB_REG_H__)
#define __SI_GB_REG_H__
/*
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
@ -27,6 +24,20 @@
* of the Software.
*/
#if !defined (__SI_GB_REG_H__)
#define __SI_GB_REG_H__
/*****************************************************************************************************************
*
* si_gb_reg.h
*
* Register Spec Release: Chip Spec 0.28
*
*****************************************************************************************************************/
//
// Make sure the necessary endian defines are there.
//
#include "util/u_endian.h"
#if defined(PIPE_ARCH_LITTLE_ENDIAN)
@ -35,15 +46,6 @@
#define BIGENDIAN_CPU
#endif
//
// Make sure the necessary endian defines are there.
//
#if defined(LITTLEENDIAN_CPU)
#elif defined(BIGENDIAN_CPU)
#else
#error "BIGENDIAN_CPU or LITTLEENDIAN_CPU must be defined"
#endif
/*
* GB_ADDR_CONFIG struct
*/

1
src/amd/addrlib/src/core/addrcommon.h
View File

@ -241,6 +241,7 @@ enum ChipFamily
ADDR_CHIP_FAMILY_CI,
ADDR_CHIP_FAMILY_VI,
ADDR_CHIP_FAMILY_AI,
ADDR_CHIP_FAMILY_NAVI,
};
/**

11
src/amd/addrlib/src/core/addrlib.cpp
View File

@ -223,6 +223,9 @@ ADDR_E_RETURNCODE Lib::Create(
case FAMILY_RV:
pLib = Gfx9HwlInit(&client);
break;
case FAMILY_NV:
pLib = Gfx10HwlInit(&client);
break;
default:
ADDR_ASSERT_ALWAYS();
break;
@ -384,14 +387,14 @@ Lib* Lib::GetLib(
****************************************************************************************************
*/
ADDR_E_RETURNCODE Lib::GetMaxAlignments(
ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut ///< [out] output structure
ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut ///< [out] output structure
) const
{
ADDR_E_RETURNCODE returnCode = ADDR_OK;
if (GetFillSizeFieldsFlags() == TRUE)
{
if (pOut->size != sizeof(ADDR_GET_MAX_ALINGMENTS_OUTPUT))
if (pOut->size != sizeof(ADDR_GET_MAX_ALIGNMENTS_OUTPUT))
{
returnCode = ADDR_PARAMSIZEMISMATCH;
}
@ -424,14 +427,14 @@ ADDR_E_RETURNCODE Lib::GetMaxAlignments(
****************************************************************************************************
*/
ADDR_E_RETURNCODE Lib::GetMaxMetaAlignments(
ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut ///< [out] output structure
ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut ///< [out] output structure
) const
{
ADDR_E_RETURNCODE returnCode = ADDR_OK;
if (GetFillSizeFieldsFlags() == TRUE)
{
if (pOut->size != sizeof(ADDR_GET_MAX_ALINGMENTS_OUTPUT))
if (pOut->size != sizeof(ADDR_GET_MAX_ALIGNMENTS_OUTPUT))
{
returnCode = ADDR_PARAMSIZEMISMATCH;
}

5
src/amd/addrlib/src/core/addrlib.h
View File

@ -282,9 +282,9 @@ public:
BOOL_32 GetExportNorm(const ELEM_GETEXPORTNORM_INPUT* pIn) const;
ADDR_E_RETURNCODE GetMaxAlignments(ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut) const;
ADDR_E_RETURNCODE GetMaxAlignments(ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut) const;
ADDR_E_RETURNCODE GetMaxMetaAlignments(ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut) const;
ADDR_E_RETURNCODE GetMaxMetaAlignments(ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut) const;
UINT_32 GetBpe(AddrFormat format) const;
@ -409,6 +409,7 @@ private:
Lib* SiHwlInit (const Client* pClient);
Lib* CiHwlInit (const Client* pClient);
Lib* Gfx9HwlInit (const Client* pClient);
Lib* Gfx10HwlInit(const Client* pClient);
} // Addr
#endif

4
src/amd/addrlib/src/core/addrlib2.h
View File

@ -104,6 +104,8 @@ enum AddrBlockSet
AddrBlockSetLinear = 1 << AddrBlockLinear,
AddrBlockSetMacro = AddrBlockSetMacro4KB | AddrBlockSetMacro64KB,
AddrBlockSet2dGfx10 = AddrBlockSetMicro | AddrBlockSetMacro,
AddrBlockSet3dGfx10 = AddrBlockSetMacro,
};
enum AddrSwSet
@ -114,6 +116,8 @@ enum AddrSwSet
AddrSwSetR = 1 << ADDR_SW_R,
AddrSwSetAll = AddrSwSetZ | AddrSwSetS | AddrSwSetD | AddrSwSetR,
AddrSwSet3dThinGfx10 = AddrSwSetZ | AddrSwSetR,
AddrSwSetColorGfx10 = AddrSwSetS | AddrSwSetD | AddrSwSetR,
};
/**

1
src/amd/addrlib/src/core/coord.cpp
View File

@ -1,3 +1,4 @@
/*
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.

7429
src/amd/addrlib/src/gfx10/gfx10SwizzlePattern.h Normal file
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File diff suppressed because it is too large Load Diff

4038
src/amd/addrlib/src/gfx10/gfx10addrlib.cpp Normal file
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File diff suppressed because it is too large Load Diff

569
src/amd/addrlib/src/gfx10/gfx10addrlib.h Normal file
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@ -0,0 +1,569 @@
/*
* Copyright © 2007-2019 Advanced Micro Devices, Inc.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
************************************************************************************************************************
* @file gfx10addrlib.h
* @brief Contains the Gfx10Lib class definition.
************************************************************************************************************************
*/
#ifndef __GFX10_ADDR_LIB_H__
#define __GFX10_ADDR_LIB_H__
#include "addrlib2.h"
#include "coord.h"
namespace Addr
{
namespace V2
{
/**
************************************************************************************************************************
* @brief GFX10 specific settings structure.
************************************************************************************************************************
*/
struct Gfx10ChipSettings
{
struct
{
UINT_32 reserved1 : 32;
// Misc configuration bits
UINT_32 isDcn2 : 1;
UINT_32 supportRbPlus : 1;
UINT_32 dsMipmapHtileFix : 1;
UINT_32 dccUnsup3DSwDis : 1;
UINT_32 reserved2 : 28;
};
};
/**
************************************************************************************************************************
* @brief GFX10 data surface type.
************************************************************************************************************************
*/
enum Gfx10DataType
{
Gfx10DataColor,
Gfx10DataDepthStencil,
Gfx10DataFmask
};
const UINT_32 Gfx10LinearSwModeMask = (1u << ADDR_SW_LINEAR);
const UINT_32 Gfx10Blk256BSwModeMask = (1u << ADDR_SW_256B_S) |
(1u << ADDR_SW_256B_D);
const UINT_32 Gfx10Blk4KBSwModeMask = (1u << ADDR_SW_4KB_S) |
(1u << ADDR_SW_4KB_D) |
(1u << ADDR_SW_4KB_S_X) |
(1u << ADDR_SW_4KB_D_X);
const UINT_32 Gfx10Blk64KBSwModeMask = (1u << ADDR_SW_64KB_S) |
(1u << ADDR_SW_64KB_D) |
(1u << ADDR_SW_64KB_S_T) |
(1u << ADDR_SW_64KB_D_T) |
(1u << ADDR_SW_64KB_Z_X) |
(1u << ADDR_SW_64KB_S_X) |
(1u << ADDR_SW_64KB_D_X) |
(1u << ADDR_SW_64KB_R_X);
const UINT_32 Gfx10ZSwModeMask = (1u << ADDR_SW_64KB_Z_X);
const UINT_32 Gfx10StandardSwModeMask = (1u << ADDR_SW_256B_S) |
(1u << ADDR_SW_4KB_S) |
(1u << ADDR_SW_64KB_S) |
(1u << ADDR_SW_64KB_S_T) |
(1u << ADDR_SW_4KB_S_X) |
(1u << ADDR_SW_64KB_S_X);
const UINT_32 Gfx10DisplaySwModeMask = (1u << ADDR_SW_256B_D) |
(1u << ADDR_SW_4KB_D) |
(1u << ADDR_SW_64KB_D) |
(1u << ADDR_SW_64KB_D_T) |
(1u << ADDR_SW_4KB_D_X) |
(1u << ADDR_SW_64KB_D_X);
const UINT_32 Gfx10RenderSwModeMask = (1u << ADDR_SW_64KB_R_X);
const UINT_32 Gfx10XSwModeMask = (1u << ADDR_SW_4KB_S_X) |
(1u << ADDR_SW_4KB_D_X) |
(1u << ADDR_SW_64KB_Z_X) |
(1u << ADDR_SW_64KB_S_X) |
(1u << ADDR_SW_64KB_D_X) |
(1u << ADDR_SW_64KB_R_X);
const UINT_32 Gfx10TSwModeMask = (1u << ADDR_SW_64KB_S_T) |
(1u << ADDR_SW_64KB_D_T);
const UINT_32 Gfx10XorSwModeMask = Gfx10XSwModeMask |
Gfx10TSwModeMask;
const UINT_32 Gfx10Rsrc1dSwModeMask = Gfx10LinearSwModeMask |
Gfx10RenderSwModeMask |
Gfx10ZSwModeMask;
const UINT_32 Gfx10Rsrc2dSwModeMask = Gfx10LinearSwModeMask |
Gfx10Blk256BSwModeMask |
Gfx10Blk4KBSwModeMask |
Gfx10Blk64KBSwModeMask;
const UINT_32 Gfx10Rsrc3dSwModeMask = (1u << ADDR_SW_LINEAR) |
(1u << ADDR_SW_4KB_S) |
(1u << ADDR_SW_64KB_S) |
(1u << ADDR_SW_64KB_S_T) |
(1u << ADDR_SW_4KB_S_X) |
(1u << ADDR_SW_64KB_Z_X) |
(1u << ADDR_SW_64KB_S_X) |
(1u << ADDR_SW_64KB_D_X) |
(1u << ADDR_SW_64KB_R_X);
const UINT_32 Gfx10Rsrc2dPrtSwModeMask = (Gfx10Blk4KBSwModeMask | Gfx10Blk64KBSwModeMask) & ~Gfx10XSwModeMask;
const UINT_32 Gfx10Rsrc3dPrtSwModeMask = Gfx10Rsrc2dPrtSwModeMask & ~Gfx10DisplaySwModeMask;
const UINT_32 Gfx10Rsrc3dThinSwModeMask = (1u << ADDR_SW_64KB_Z_X) |
(1u << ADDR_SW_64KB_R_X);
const UINT_32 Gfx10MsaaSwModeMask = Gfx10ZSwModeMask |
Gfx10RenderSwModeMask;
const UINT_32 Dcn2NonBpp64SwModeMask = (1u << ADDR_SW_LINEAR) |
(1u << ADDR_SW_4KB_S) |
(1u << ADDR_SW_64KB_S) |
(1u << ADDR_SW_64KB_S_T) |
(1u << ADDR_SW_4KB_S_X) |
(1u << ADDR_SW_64KB_S_X) |
(1u << ADDR_SW_64KB_R_X);
const UINT_32 Dcn2Bpp64SwModeMask = (1u << ADDR_SW_4KB_D) |
(1u << ADDR_SW_64KB_D) |
(1u << ADDR_SW_64KB_D_T) |
(1u << ADDR_SW_4KB_D_X) |
(1u << ADDR_SW_64KB_D_X) |
Dcn2NonBpp64SwModeMask;
/**
************************************************************************************************************************
* @brief This class is the GFX10 specific address library
* function set.
************************************************************************************************************************
*/
class Gfx10Lib : public Lib
{
public:
/// Creates Gfx10Lib object
static Addr::Lib* CreateObj(const Client* pClient)
{
VOID* pMem = Object::ClientAlloc(sizeof(Gfx10Lib), pClient);
return (pMem != NULL) ? new (pMem) Gfx10Lib(pClient) : NULL;
}
protected:
Gfx10Lib(const Client* pClient);
virtual ~Gfx10Lib();
virtual BOOL_32 HwlIsStandardSwizzle(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode) const
{
return m_swizzleModeTable[swizzleMode].isStd;
}
virtual BOOL_32 HwlIsDisplaySwizzle(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode) const
{
return m_swizzleModeTable[swizzleMode].isDisp;
}
virtual BOOL_32 HwlIsThin(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode) const
{
return ((IsTex1d(resourceType) == TRUE) ||
(IsTex2d(resourceType) == TRUE) ||
((IsTex3d(resourceType) == TRUE) &&
(m_swizzleModeTable[swizzleMode].isStd == FALSE) &&
(m_swizzleModeTable[swizzleMode].isDisp == FALSE)));
}
virtual BOOL_32 HwlIsThick(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode) const
{
return ((IsTex3d(resourceType) == TRUE) &&
(m_swizzleModeTable[swizzleMode].isStd || m_swizzleModeTable[swizzleMode].isDisp));
}
virtual ADDR_E_RETURNCODE HwlComputeHtileInfo(
const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn,
ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlComputeCmaskInfo(
const ADDR2_COMPUTE_CMASK_INFO_INPUT* pIn,
ADDR2_COMPUTE_CMASK_INFO_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlComputeDccInfo(
const ADDR2_COMPUTE_DCCINFO_INPUT* pIn,
ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlComputeCmaskAddrFromCoord(
const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn,
ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut);
virtual ADDR_E_RETURNCODE HwlComputeHtileAddrFromCoord(
const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn,
ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut);
virtual ADDR_E_RETURNCODE HwlComputeHtileCoordFromAddr(
const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn,
ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut);
virtual ADDR_E_RETURNCODE HwlComputeDccAddrFromCoord(
const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn,
ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut);
virtual UINT_32 HwlGetEquationIndex(
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
virtual UINT_32 HwlGetEquationTableInfo(const ADDR_EQUATION** ppEquationTable) const
{
*ppEquationTable = m_equationTable;
return m_numEquations;
}
virtual ADDR_E_RETURNCODE HwlComputePipeBankXor(
const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn,
ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlComputeSlicePipeBankXor(
const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn,
ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlComputeSubResourceOffsetForSwizzlePattern(
const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn,
ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlGetPreferredSurfaceSetting(
const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn,
ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoSanityCheck(
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoTiled(
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoLinear(
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
virtual ADDR_E_RETURNCODE HwlComputeSurfaceAddrFromCoordTiled(
const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const;
// Initialize equation table
VOID InitEquationTable();
ADDR_E_RETURNCODE ComputeSurfaceInfoMacroTiled(
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ComputeSurfaceInfoMicroTiled(
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoordMacroTiled(
const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const;
ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoordMicroTiled(
const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const;
UINT_32 ComputeOffsetFromSwizzlePattern(
const UINT_64* pPattern,
UINT_32 numBits,
UINT_32 x,
UINT_32 y,
UINT_32 z,
UINT_32 s) const;
UINT_32 ComputeOffsetFromEquation(
const ADDR_EQUATION* pEq,
UINT_32 x,
UINT_32 y,
UINT_32 z) const;
ADDR_E_RETURNCODE ComputeStereoInfo(
const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
UINT_32 blkHeight,
UINT_32* pAlignY,
UINT_32* pRightXor) const;
Dim3d GetDccCompressBlk(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode,
UINT_32 bpp) const
{
UINT_32 index = Log2(bpp >> 3);
Dim3d compressBlkDim;
if (IsThin(resourceType, swizzleMode))
{
compressBlkDim.w = Block256_2d[index].w;
compressBlkDim.h = Block256_2d[index].h;
compressBlkDim.d = 1;
}
else
{
compressBlkDim = Block256_3d[index];
}
return compressBlkDim;
}
static UINT_32 ShiftCeil(
UINT_32 a,
UINT_32 b)
{
return (a >> b) + (((a & ((1 << b) - 1)) != 0) ? 1 : 0);
}
static void GetMipSize(
UINT_32 mip0Width,
UINT_32 mip0Height,
UINT_32 mip0Depth,
UINT_32 mipId,
UINT_32* pMipWidth,
UINT_32* pMipHeight,
UINT_32* pMipDepth = NULL)
{
*pMipWidth = ShiftCeil(Max(mip0Width, 1u), mipId);
*pMipHeight = ShiftCeil(Max(mip0Height, 1u), mipId);
if (pMipDepth != NULL)
{
*pMipDepth = ShiftCeil(Max(mip0Depth, 1u), mipId);
}
}
const UINT_64* GetSwizzlePattern(
AddrSwizzleMode swizzleMode,
AddrResourceType resourceType,
UINT_32 log2Elem,
UINT_32 numFrag) const;
VOID ConvertSwizzlePatternToEquation(
UINT_32 elemLog2,
AddrResourceType rsrcType,
AddrSwizzleMode swMode,
const UINT_64* pPattern,
ADDR_EQUATION* pEquation) const;
static INT_32 GetMetaElementSizeLog2(Gfx10DataType dataType);
static INT_32 GetMetaCacheSizeLog2(Gfx10DataType dataType);
void GetBlk256SizeLog2(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode,
UINT_32 elemLog2,
UINT_32 numSamplesLog2,
Dim3d* pBlock) const;
void GetCompressedBlockSizeLog2(
Gfx10DataType dataType,
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode,
UINT_32 elemLog2,
UINT_32 numSamplesLog2,
Dim3d* pBlock) const;
INT_32 GetMetaOverlapLog2(
Gfx10DataType dataType,
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode,
UINT_32 elemLog2,
UINT_32 numSamplesLog2) const;
INT_32 Get3DMetaOverlapLog2(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode,
UINT_32 elemLog2) const;
UINT_32 GetMetaBlkSize(
Gfx10DataType dataType,
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode,
UINT_32 elemLog2,
UINT_32 numSamplesLog2,
BOOL_32 pipeAlign,
Dim3d* pBlock) const;
BOOL_32 IsEquationCompatibleThick(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode) const
{
return IsThick(resourceType, swizzleMode) &&
((m_settings.supportRbPlus == 0) || (swizzleMode != ADDR_SW_64KB_D_X));
}
INT_32 GetPipeRotateAmount(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode) const;
INT_32 GetEffectiveNumPipes() const
{
return ((m_settings.supportRbPlus == FALSE) ||
((m_numSaLog2 + 1) >= m_pipesLog2)) ? m_pipesLog2 : m_numSaLog2 + 1;
}
BOOL_32 IsRbAligned(
AddrResourceType resourceType,
AddrSwizzleMode swizzleMode) const
{
const BOOL_32 isRtopt = IsRtOptSwizzle(swizzleMode);
const BOOL_32 isZ = IsZOrderSwizzle(swizzleMode);
const BOOL_32 isDisplay = IsDisplaySwizzle(swizzleMode);
return (IsTex2d(resourceType) && (isRtopt || isZ)) ||
(IsTex3d(resourceType) && isDisplay);
}
static const Dim3d Block256_3d[MaxNumOfBpp];
static const Dim3d Block64K_3d[MaxNumOfBpp];
static const Dim3d Block4K_3d[MaxNumOfBpp];
static const Dim3d Block64K_Log2_3d[MaxNumOfBpp];
static const Dim3d Block4K_Log2_3d[MaxNumOfBpp];
static const Dim2d Block64K_2d[MaxNumOfBpp];
static const Dim2d Block4K_2d[MaxNumOfBpp];
static const Dim2d Block64K_Log2_2d[MaxNumOfBpp];
static const Dim2d Block4K_Log2_2d[MaxNumOfBpp];
static const SwizzleModeFlags SwizzleModeTable[ADDR_SW_MAX_TYPE];
// Max number of swizzle mode supported for equation
static const UINT_32 MaxSwMode = 32;
// Max number of resource type (2D/3D) supported for equation
static const UINT_32 MaxRsrcType = 2;
// Max number of bpp (8bpp/16bpp/32bpp/64bpp/128bpp)
static const UINT_32 MaxElementBytesLog2 = 5;
// Almost all swizzle mode + resource type support equation
static const UINT_32 EquationTableSize = MaxElementBytesLog2 * MaxSwMode * MaxRsrcType;
// Equation table
ADDR_EQUATION m_equationTable[EquationTableSize];
// Number of equation entries in the table
UINT_32 m_numEquations;
// Equation lookup table according to bpp and tile index
UINT_32 m_equationLookupTable[MaxRsrcType][MaxSwMode][MaxElementBytesLog2];
// Number of packers log2
UINT_32 m_numPkrLog2;
// Number of shader array log2
UINT_32 m_numSaLog2;
private:
virtual UINT_32 HwlComputeMaxBaseAlignments() const;
virtual UINT_32 HwlComputeMaxMetaBaseAlignments() const;
virtual BOOL_32 HwlInitGlobalParams(const ADDR_CREATE_INPUT* pCreateIn);
virtual ChipFamily HwlConvertChipFamily(UINT_32 uChipFamily, UINT_32 uChipRevision);
BOOL_32 IsValidDisplaySwizzleMode(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
UINT_32 GetMaxNumMipsInTail(UINT_32 blockSizeLog2, BOOL_32 isThin) const;
static ADDR2_BLOCK_SET GetAllowedBlockSet(ADDR2_SWMODE_SET allowedSwModeSet)
{
ADDR2_BLOCK_SET allowedBlockSet = {};
allowedBlockSet.micro = (allowedSwModeSet.value & Gfx10Blk256BSwModeMask) ? TRUE : FALSE;
allowedBlockSet.macro4KB = (allowedSwModeSet.value & Gfx10Blk4KBSwModeMask) ? TRUE : FALSE;
allowedBlockSet.macro64KB = (allowedSwModeSet.value & Gfx10Blk64KBSwModeMask) ? TRUE : FALSE;
allowedBlockSet.linear = (allowedSwModeSet.value & Gfx10LinearSwModeMask) ? TRUE : FALSE;
return allowedBlockSet;
}
static ADDR2_SWTYPE_SET GetAllowedSwSet(ADDR2_SWMODE_SET allowedSwModeSet)
{
ADDR2_SWTYPE_SET allowedSwSet = {};
allowedSwSet.sw_Z = (allowedSwModeSet.value & Gfx10ZSwModeMask) ? TRUE : FALSE;
allowedSwSet.sw_S = (allowedSwModeSet.value & Gfx10StandardSwModeMask) ? TRUE : FALSE;
allowedSwSet.sw_D = (allowedSwModeSet.value & Gfx10DisplaySwModeMask) ? TRUE : FALSE;
allowedSwSet.sw_R = (allowedSwModeSet.value & Gfx10RenderSwModeMask) ? TRUE : FALSE;
return allowedSwSet;
}
BOOL_32 IsInMipTail(
Dim3d mipTailDim,
UINT_32 maxNumMipsInTail,
UINT_32 mipWidth,
UINT_32 mipHeight,
UINT_32 numMipsToTheEnd) const
{
BOOL_32 inTail = ((mipWidth <= mipTailDim.w) &&
(mipHeight <= mipTailDim.h) &&
(numMipsToTheEnd <= maxNumMipsInTail));
return inTail;
}
UINT_32 GetBankXorBits(UINT_32 blockBits) const
{
return (blockBits > m_pipeInterleaveLog2 + m_pipesLog2 + ColumnBits) ?
Min(blockBits - m_pipeInterleaveLog2 - m_pipesLog2 - ColumnBits, BankBits) : 0;
}
BOOL_32 ValidateNonSwModeParams(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
BOOL_32 ValidateSwModeParams(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
static const UINT_32 ColumnBits = 2;
static const UINT_32 BankBits = 4;
Gfx10ChipSettings m_settings;
UINT_32 m_colorBaseIndex;
UINT_32 m_htileBaseIndex;
};
} // V2
} // Addr
#endif

1
src/amd/addrlib/src/gfx9/gfx9addrlib.h
View File

@ -62,6 +62,7 @@ struct Gfx9ChipSettings
// Display engine IP version name
UINT_32 isDce12 : 1;
UINT_32 isDcn1 : 1;
UINT_32 reserved1 : 30;
// Misc configuration bits
UINT_32 metaBaseAlignFix : 1;

1
src/amd/addrlib/src/r800/egbaddrlib.cpp
View File

@ -23,7 +23,6 @@
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*/
/**
****************************************************************************************************
* @file egbaddrlib.cpp

2
src/amd/common/ac_surface.c
View File

@ -68,7 +68,7 @@ ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info,
ADDR_CREATE_OUTPUT addrCreateOutput = {0};
ADDR_REGISTER_VALUE regValue = {0};
ADDR_CREATE_FLAGS createFlags = {{0}};
ADDR_GET_MAX_ALINGMENTS_OUTPUT addrGetMaxAlignmentsOutput = {0};
ADDR_GET_MAX_ALIGNMENTS_OUTPUT addrGetMaxAlignmentsOutput = {0};
ADDR_E_RETURNCODE addrRet;
addrCreateInput.size = sizeof(ADDR_CREATE_INPUT);