Commit Graph

3456 Commits

Author SHA1 Message Date
Konrad Dybcio d3b38213e5 freedreno: Enable A619
Enable A619 as found in various SKUs of the SM Lagoon SoC, such as
SM6350 and SM7225.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17495>
2022-07-21 00:16:32 +00:00
Danylo Piliaiev 7b0fcd8932 turnip: Disable LRZ fast-clear for gen1 and gen2
LRZ fast-clear works on all gens, however blob disables it on
gen1 and gen2. We also elect to disable fast-clear on these gens
because for close to none gains it adds complexity and seem to work
a bit differently from gen3+. Which creates at least one edge case:
if first draw which uses LRZ fast-clear doesn't lock LRZ direction
the fast-clear value is undefined.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6829

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17599>
2022-07-20 02:58:44 +00:00
Emma Anholt 7e381ba9fc ci/freedreno: Switch a630 to manual/disabled for lab maintenance.
We're getting several more 630s in the lab, but need a bit of time to swap
out some broken old ones and stabilize the new ones.  Fritz thinks this
should be done in an hour or so, but I want to turn off the CI for main so
that we don't block anyone else.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17641>
2022-07-20 02:00:43 +00:00
Jason Ekstrand b510ee0d22 Use vk_foreach_struct_const where needed
We're about to make it so that the compiler warns/errors if you use the
wrong iterator macro.  Fix up a bunch of places where someone used the
wrong one before we break anything.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17630>
2022-07-19 19:55:17 +00:00
Hyunjun Ko 4bccee123f turnip: expose VK_EXT_shader_module_identifier
Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17614>
2022-07-19 16:12:15 +00:00
Hyunjun Ko d046d6e9e0 turnip: Remove an unnecessary assert.
The assertion is already in the common implementation.

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17614>
2022-07-19 16:12:15 +00:00
Emma Anholt 3d62a41dcc freedreno/ir3: Enable core NIR's 16-bit ALU optimizations.
In addition to hopefully generating shorter code, this optimizes out a
comparison of a mediump-cast value in
dEQP-GLES2.functional.shaders.algorithm.rgb_to_hsl_fragment passed
through ANGLE, and allows the test to pass.  We believe it to be a
test bug, but emitting better code like apparently everyone else does
is also a fine result.

No change on GLES gfxbench shaders.

Fixes: #6585
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17546>
2022-07-18 22:41:18 +00:00
Konstantin Seurer fc26fbde3d vulkan: Common vk_format_get_component_bits
RADV and PowerVR use the same implementation.
Turnip does use a slightly modified version but the helper only has one
use -> just inline it and get rid of turnip's vk_format.h.

Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17515>
2022-07-18 22:14:06 +00:00
Daniel Stone cdb7a3b0e2 Revert "CI: Disable Collabora lab"
This reverts commit 7a336c97ef692ed96cc93394596a7d0650983874.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17563>
2022-07-16 11:44:26 +00:00
Daniel Stone 02d9d1557b CI: Disable Collabora lab
It's everyone's favourite day, infrastructure maintenance Friday.

This includes manual disables for a618-vk and zink-anv-tgl, because
apparently the disable-on-variable rules don't carry through to those
jobs for ... some reason.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17553>
2022-07-15 13:26:42 +00:00
Connor Abbott 67c9ca2319 tu: Use incoherent CCU write for buffer accesses
Unlike image writes, buffer writes may access the same memory in
different ways, which we've seen in the past can cause problems. Use an
incoherent access to force flush/invalidate between accesses to the same
buffer, unless we know the barrier applies to images only.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17193>
2022-07-14 17:23:39 +00:00
Emma Anholt 43579901be ir3: Fix the no-emitted-vertex condition emission in geom lowering.
The if statement we insert would insert a new block before the end block
(and remove the old pre-end-block).  If the new block ended up later in
the HT due to its pointer's hash value, you'd emit another copy of the if
statement after the last one.  I saw this happen up to 4 times in testing.
The worst case would be if all those additions and removals ended up
reallocating the HT, at which point we might use-after-free.

Fixes inconsistent shader-db results with geometry shaders.

Cc: mesa-stable.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17501>
2022-07-13 18:16:45 +00:00
Adam Jackson 768238fdc0 glx: Fix drawable refcounting for naked Windows
driFetchDrawable is only ever called from the MakeCurrent path, which
means it has to handle the case of pre-GLX-1.3 Windows being named as
the drawable. When it finds the drawable in the hash, it increments its
refcount before returning it, so for a GLXWindow it would be 2 on first
return, one from glXCreateWindow and one from glXMakeCurrent. But when
it does not find the drawable and creates one for the naked Window, the
reference count on first return would only be 1. As a result, if this
context was then ever bound to a different drawable, the old Window's
DRI drawable state (like the back buffer) would be destroyed.

Fixes piglit's glx-multi-window-single-context and glx-make-current for
a variety of drivers.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6713
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17479>
2022-07-13 12:25:30 -04:00
Georg Lehmann d9fb1b05eb ir3: Implement [iu]sub_sat.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17468>
2022-07-13 07:34:09 +00:00
Danylo Piliaiev b059cdad40 turnip: Add TU_GPU_TRACEPOINT envvar to toggle tracepoints
All tracepoints are enabled by default.

Example:
 TU_GPU_TRACEPOINT=-sysmem_clear

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16781>
2022-07-12 22:24:19 +00:00
Danylo Piliaiev d903c6c7f3 turnip: Refactor tracepoints generation to reduce duplication
This way we will not need to repeat arguments for "start" and "end"
tracepoints.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16781>
2022-07-12 22:24:19 +00:00
Emma Anholt e9d4c29f6a ci/freedreno: Mark an occasional flake pass that happens on a530.
This MR just saw it happen for the second time I've noticed.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17470>
2022-07-12 21:57:23 +00:00
Connor Abbott cf0cfd572e freedreno/a6xx: VPC_SO_NCOMP is actually VPC_SO_BUFFER_STRIDE
This answers the question in a comment in turnip, and fixes some GL46
tests and piglit tests.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17494>
2022-07-12 17:57:07 +00:00
Eric Engestrom 2c99dc5b22 turnip: use updated tokens from vk.xml
Signed-off-by: Eric Engestrom <eric@igalia.com>
Acked-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Reviewed-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17342>
2022-07-12 15:53:11 +00:00
Emma Anholt 4822058b1c ir3: Use non-persp interpolation when appropriate for interpolateAtOffset.
Fixes dEQP-VK.draw.renderpass.linear_interpolation.offset_min_4_samples.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17322>
2022-07-11 16:56:05 +00:00
Emma Anholt c5eb7ef246 ir3: Clarify what's happening in the interpolateAtOffset() math.
nir_builder lets us build much cleaner code than we had (assuming that we
get a scalarizing after this).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17322>
2022-07-11 16:56:05 +00:00
Emma Anholt 240a98297d freedreno: Rename the "SIZE" regs for interpolateAtOffset to "CENTERRHW"
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17322>
2022-07-11 16:56:05 +00:00
Emma Anholt 0e1fb2d984 nir+ir3: Rename load_size_ir3 to load_center_rhw_ir3.
Now that we know what it does, it also explains what it's doing in
interpolateAtOffset in ir3.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17322>
2022-07-11 16:56:05 +00:00
Emma Anholt 9dcb94e0e1 ir3: Make sure to pass the interp_mode through in our load_bary lowering.
Fixes dEQP-VK.draw.renderpass.linear_interpolation.* in vkcts 1.3.3.0

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17322>
2022-07-11 16:56:05 +00:00
Emma Anholt 4b404e22d0 turnip: Refactor vertex input setup a little.
The repeated reservation code could be moved into the function.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17102>
2022-07-11 16:32:03 +00:00
Emma Anholt ec5984c0d4 turnip: Fix the reservation for vertex inputs.
It was too large since 2cd30266f1 ("tu: Refactor VS DECODE/DEST to be
emitted in two pkt4"), so fix it and also give it a name next to the code
it relates to.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17102>
2022-07-11 16:32:03 +00:00
Emma Anholt 12314067c4 turnip: Fix up per-stage additional size accounting.
input_size is the dwords emitted (hard to tell because of all of the * 4 /
4 going on), and constant_data is emitted with the emit_program call too.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17102>
2022-07-11 16:32:03 +00:00
Emma Anholt 7d9a824d27 turnip: Account for additional_cs_reserve_size for both bin and render.
Both emit_program() calls will use this space.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17102>
2022-07-11 16:32:03 +00:00
İlhan Atahan 4bd128f748 Add Adreno 616 and 620 to use turnip on these GPU's .
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17441>
2022-07-10 15:36:52 +00:00
Marek Olšák c9ca8abe4f Change all debug_assert calls to assert
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17403>
2022-07-10 00:50:35 +00:00
Rob Clark c2c2da91a8 freedreno/a6xx: Do clip-plane lowering in backend
Our GS-lowered-to-quasi-VS confuses core nir passes, so handle clip-
plane lowering ourself.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17341>
2022-07-08 20:32:35 +00:00
Rob Clark 8f77187e3e freedreno/ir3: Fix GS clip-plane lowering
And also handle tess.  In all cases, we want to use the VS lowering pass
on the last geometry stage.  We don't make a special exception for GS
like other drivers, because GS gets lowered into a quasi-VS.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17341>
2022-07-08 20:32:35 +00:00
Rob Clark f2d9805f9b freedreno/ir3: Add more tess varying slots
Fixes some piglits that I stumbled across by mistake.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17341>
2022-07-08 20:32:35 +00:00
Rob Clark ff22be1110 freedreno/ir3: Copy vars if needed on EndPrimitive()
If we didn't EmitPrimitive() then the shadow (old) outputs would not
get copied to the emit temps (to eventually be copied back to the real
outputs.  This isn't so bad except that means the realy vertex_flags
output has an undefined value.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17341>
2022-07-08 20:32:35 +00:00
Rob Clark 1fdddb1424 freedreno/ir3: Add copy_vars() helper
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17341>
2022-07-08 20:32:35 +00:00
Rob Clark 5434de7ab6 freedreno/ir3: Don't lower_gs multiple times
At least with gallium, this can be called multiple times via
pipe_screen::finalize_nir().  But it is not designed to be called
multiple times, and can result in vertex_flags getting 'optimized'
away.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6720
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17341>
2022-07-08 20:32:35 +00:00
Rob Clark 62c5d428bc turnip: assert valid vertex_flag reg
If this somehow gets optimized out, the GS will run forever.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17341>
2022-07-08 20:32:35 +00:00
Danylo Piliaiev bf4c160909 tu: Fix prim gen query and pipeline stats query interaction
Fixed:
- VK_QUERY_TYPE_PRIMITIVES_GENERATED_EXT was able to stop prim counter
  when pipeline stats query is running.
  - This may have happened when prim gen query was in secondary cmdbuf.
- VK_QUERY_TYPE_PRIMITIVES_GENERATED_EXT counting geometry in each tile.
- VK_QUERY_TYPE_PRIMITIVES_GENERATED_EXT counting geometry in each tile
  when pipeline stats query is started inside prim gen query and inside
  a renderpass.

The matter of VK_QUERY_TYPE_PRIMITIVES_GENERATED_EXT and pipeline stats
interaction is solved by tracking whether pipeline stats query is
running both on CPU (for non secondary cmdbuf case) and on GPU (for
secondary cmdbuf).

Note, prim gen query is not allowed with secondary command buffers, so
only pipeline stats query is tracked on gpu.
See https://gitlab.khronos.org/vulkan/vulkan/-/issues/3142

Counting geometry per each tile is solved by:
- Conditionally executing START/STOP_PRIMITIVE_CTRS to not run in tiling
  pass. Solves the case when prim gen query is inside a renderpass.
- Stop prim counters before executing `draw_cs` and restarting them
  afterwards. Solves prim gen query being outside a renderpass.

Fixes GL CTS tests with Zink + `TU_DEBUG=gmem`:
 GTF-GL46.gtf30.GL3Tests.transform_feedback.transform_feedback_max_separate
 GTF-GL46.gtf40.GL3Tests.transform_feedback2.transform_feedback2_basic
 GTF-GL46.gtf40.GL3Tests.transform_feedback2.transform_feedback2_framebuffer
 GTF-GL46.gtf40.GL3Tests.transform_feedback3.transform_feedback3_streams_overflow
 GTF-GL46.gtf40.GL3Tests.transform_feedback3.transform_feedback3_streams_queried
 GTF-GL46.gtf40.GL3Tests.transform_feedback2.transform_feedback2_states

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6602

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17163>
2022-07-08 11:14:18 +03:00
Danylo Piliaiev 465e7c303b tu,freedreno: Refactored START/STOP events for pipeline stats
For a5xx+ renamed:
- RST_PIX_CNT -> START_FRAGMENT_CTRS
- RST_VTX_CNT -> STOP_FRAGMENT_CTRS
- TILE_FLUSH  -> START_COMPUTE_CTRS
- STAT_EVENT  -> STOP_COMPUTE_CTRS
I'm not sure about a5xx itself but I'll take a chance of it being
similar to a6xx in this regard.

Knowing this emit_begin_stat_query/emit_end_stat_query can now emit
only events that are needed for the pool's flags.

Also primitive generated query clearly doesn't need fragment and
compute counters.

Passes tests:
 dEQP-VK.query_pool.statistics_query.*
 dEQP-VK.transform_feedback.primitives_generated_query.*

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17163>
2022-07-08 11:14:18 +03:00
Pierre-Eric Pelloux-Prayer 8856379a03 mesa/st: don't guess the internal format if it's known
This fixes tests using imageLoad/imageStore on texture
created using glEGLImageTargetTexture2DOES.

Before this change, the format was guessed as GL_RGBA,
which would be rejected by _mesa_get_shader_image_format.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16662>
2022-07-07 12:25:05 +00:00
Emma Anholt 00ad29dd23 ci: Uprev deqp to 1.3.3.0.
New tests, dEQP line rasterization test fix that lets Intel pass.

Clears out bogus xfails from 1.3.2.0 uprev on a630, which I suspect were
"we lost the device twice on a full run once, and those fails got pasted
in without checking if it happened a full run again" (since we haven't
seen them in other full run attempts).

Also clears out the a630 vk asan xfails (essentially all tests run) by
turning off leak detection which was just catching leaks in vkcts.

Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17304>
2022-07-05 17:02:33 +00:00
Emma Anholt 01988667fd ir3: Retire the cp postsched pass now that we do RA in SSA.
Before, we needed CP post-sched to copy-propagate references to NIR
registers produced by out-of-ssa.  Now that we're in SSA, this pass ends
up not doing anything useful, and actually gets in the way by occasionally
creating a cycle in the DAG.

The entire shader-db impact is:

instructions HURT:   shaders/closed/steam/tropico-5/78.shader_test FRAG: 238 -> 242 (1.68%)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17320>
2022-07-04 22:15:58 +00:00
David Heidelberg fb2266631f Revert "ci/freedreno: temporary disable AmnesiaTDD"
This reverts commit f77695d13f.

Acked-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17353>
2022-07-04 18:46:57 +02:00
Rob Clark 9e1bf8e7ac freedreno/registers: Small cleanup
Whitespace fix plus move a couple regs that ended split apart from the
rest of the VFD regs.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17317>
2022-07-03 23:20:46 +00:00
Rob Clark bc6f1afc79 freedreno: Add pkt4 assert
Add assert to catch places where we overflow max PKT4 size

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17317>
2022-07-03 23:20:46 +00:00
Jonathan Marek b41620f9ed freedreno/registers: add missing varset="chip" for new enum values
Fixes: de8c769d11 ("freedreno/registers: add a7xx registers for drm/msm kernel driver")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6788
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17351>
2022-07-03 18:01:17 +00:00
David Heidelberg 1bcb883ea5 ci/freedreno: disable SpecOps trace, each run flaky
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17336>
2022-07-01 15:47:09 +00:00
Jonathan Marek de8c769d11 freedreno/registers: add a7xx registers for drm/msm kernel driver
Most of this is taken directly from the downstream kernel driver.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15602>
2022-07-01 15:11:28 +00:00
David Heidelberg 6f2a991f78 ci/freedreno: disable Stellaris trace
Revert when it gets fixed on CI runner (works on OnePlus 6T with
5.18 kernel).

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17167>
2022-07-01 15:04:04 +02:00
David Heidelberg f77695d13f ci/freedreno: temporary disable AmnesiaTDD
Revert when https://gitlab.freedesktop.org/mesa/mesa/-/issues/6763 get fixed.

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17167>
2022-07-01 15:04:04 +02:00
David Heidelberg 74da4dc216 ci/freedreno: add more restricted traces
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17167>
2022-07-01 15:04:03 +02:00
Danylo Piliaiev c655387a02 ir3: Use NIR's info.writes_memory to detect when when to force late-z
Better than maintaining our old checks.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16818>
2022-07-01 11:37:17 +00:00
Emma Anholt 05b41f9207 ci/freedreno: Filter when we run test jobs for VK or GL changes.
Not only runs less testing when only one driver is impacted, but also
makes sure zink+turnip is turned off when the farm is.

Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Acked-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17287>
2022-06-30 18:31:21 +00:00
Hyunjun Ko f4b72fa26d turnip: keep the depth_clip_disable state at the pipeline builder.
So we could later decide whether to enable Z_CLIP_DISABLE on not.

Closes: #6732

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17248>
2022-06-30 01:08:17 +00:00
Hyunjun Ko 6cb41c5188 freedreno,ir3: rename Z_CLAMP_ENABLE to Z_CLIP_DISABLE
UNK5 of GRAS_CL_CNTL is still unclear though.

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17248>
2022-06-30 01:08:17 +00:00
Hyunjun Ko d2e769c1b6 turnip: fix wrong size for lrz cs when lrz_track_quirk is enabled.
Fixes: 4b5f0d98fd ("tu: Overhaul LRZ, implement on-GPU dir tracking and
LRZ fast-clear")

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17289>
2022-06-29 11:15:23 +00:00
Connor Abbott 8183a728a2 tu: Fix stencil border color with has_z24uint_s8uint
On a650+ we use the new Z24UINT_S8UINT format to sample the stencil
aspect of D24S8, which returns stencil in the second component and also
uses the second integer component for the border color. However Vulkan
mandates that the first component is used for the stencil border color.
There's no workaround we know of, so we have to fall back to the old
behavior where there is a workaround. If we know the format, we can
fixup the border color ourselves though.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17177>
2022-06-29 03:00:56 +00:00
Connor Abbott e135c03446 freedreno/fdl: Note border color constraints
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17177>
2022-06-29 03:00:56 +00:00
Connor Abbott 4901a8f86e freedreno/a6xx: Use fdl format swizzle
This makes sure that we use a consistent swizzle between computing the
border color and the texture descriptor, and lets us delete the gallium
version.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17177>
2022-06-29 03:00:56 +00:00
Connor Abbott 39c64a4b53 freedreno/a6xx: Fix border color swizzling
From the API's point of view, border color replacement looks like this:

       --------------------
       | API Border Color |
       --------------------
               |
-----------    |    ----------------      ----------
| API fmt |-------->| User Swizzle |----->| Shader |
-----------         ----------------      ----------

From the HW point of view, it looks like this:

                    -------------------
                    | HW Border Color |
                    -------------------
                             |
----------     -----------   |   ---------------      ----------
| HW fmt |-----| HW swap |------>| Tex Swizzle |----->| Shader |
----------     -----------       ---------------      ----------

When the HW fmt + HW swap isn't enough to represent an API format, we
need to prepend our own swizzle to the the user's swizzle, so the tex
swizzle is a "format swizzle" composed with the user swizzle. However,
we don't want this format swizzle to be applied to border colors, so
there's a workaround in freedreno which is meant to undo the format
swizzle so that the HW border color with the format swizzle applied
equals the API border color, and everything is ok. However, on a6xx at
least it was incorrectly undoing the entire tex swizzle. This broke
border color with a user swizzle, because it was now effectively not
getting applied for the border color. It also made it seem like the user
swizzle is required for the workaround, which would have implications
for VK_EXT_border_color_swizzle with turnip, but it's not.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17177>
2022-06-29 03:00:56 +00:00
Connor Abbott 2a928ae325 freedreno/a6xx: Document border color/swizzle interaction
Make it clear that the swap happens before border color replacment but
the swizzle happens after.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17177>
2022-06-29 03:00:56 +00:00
Danylo Piliaiev 4b5f0d98fd tu: Overhaul LRZ, implement on-GPU dir tracking and LRZ fast-clear
On-GPU LRZ direction tracking allows LRZ to support secondary cmdbufs,
reusing LRZ between renderpasses, and in future to support LRZ when
VK_KHR_dynamic_rendering is used.

With on-gpu tracking we have to be careful keeping LRZ state in sync
with underlying depth image, which means we should invalidate LRZ
when underlying image is changed or the view of image is different
from previous renderpass.

All of this resulted in LRZ logic being thinly spread through the code,
making it hard to understand. So most of it was moved to tu_lrz.c.

For more details on past and new LRZ features see comment at the
top of tu_lrz.c.

Note about blob:
- Blob is much more happy to do LRZ_FLUSH, it flushes at the start
  of the renderpass, after binning, and at the end of the renderpass.
- Blob seem not to care about changes in depth image done via
  vkCmdCopyImage.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6347

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16251>
2022-06-28 17:23:16 +00:00
Danylo Piliaiev 70f1d70ddd freedreno: document GRAS_UNKNOWN_810A
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16251>
2022-06-28 17:23:16 +00:00
Connor Abbott 1cd91fdec3 freedreno: Document a650-specific CP_REG_WRITE flag
v2: Danylo: clarified previously unknown GRAS_LRZ_CNTL field.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16251>
2022-06-28 17:23:16 +00:00
Danylo Piliaiev 5592c366cf freedreno: Document rest of GRAS_LRZ_CNTL, clarify UNK_25 event
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16251>
2022-06-28 17:23:16 +00:00
Boris Brezillon 02384ca13c tu: Use vk_pipeline_hash_shader_stage()
Acked-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17186>
2022-06-28 09:07:32 +00:00
Emma Anholt f93bee19d9 ci/turnip: Trim the a630 VK run a bit.
We have a lot of spilling coverage in a618 pre-merge, don't do it all (~2
minutes) here.  Also, force-gmem touch testing should probably test less than
the default run does!

This should help make up for having added the tu-zink run.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17125>
2022-06-27 22:38:54 +00:00
Emma Anholt 523ed9521b ci/turnip: Test traces on turnip using zink.
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17125>
2022-06-27 22:38:54 +00:00
Emma Anholt 8e53194f44 ci/freedreno: Add vulkan+gl integration testing in piglit.
The libvulkan-dev was needed for building zink, which ended up turning on
the vulkan tests in piglit.  Split them out here.

Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17125>
2022-06-27 22:38:54 +00:00
Danylo Piliaiev 5aeefe8d75 tu: Don't count 3d blits in QUERY_TYPE_PRIMITIVES_GENERATED
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17164>
2022-06-24 14:10:56 +00:00
Danylo Piliaiev 97ef19e6ce tu: Use hw binning or sysmem with QUERY_TYPE_PRIMITIVES_GENERATED
Without hw binning in gmem primitives generated query result could be
multiplied by tile count, which is not expected by OpenGL users for
GL_PRIMITIVES_GENERATED.

See https://gitlab.khronos.org/vulkan/vulkan/-/issues/3131

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17164>
2022-06-24 14:10:56 +00:00
Vinson Lee b1df00cb79 tu: Check dereferenced value of rop_reads_dst.
Fix defect reported by Coverity Scan.

Dereference before null check (REVERSE_INULL)
check_after_deref: Null-checking rop_reads_dst suggests that it may be
null, but it has already been dereferenced on all paths leading to the
check.

Fixes: 94be0dd0b8 ("tu: Implement extendedDynamicState2LogicOp")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17099>
2022-06-23 11:11:56 +00:00
Connor Abbott 7d706af76b ir3: Fix vectorizer condition for SSBOs
SSBO access works very differently from UBO access. Straddling
loads/stores isn't an issue, loads/stores instead must be aligned to the
element size and can have up to 4 components.

We support 16-bit access with SSBOs on a650+, and sometimes the
vectorizer tries to create a misaligned 32-bit access when combining
32-bit and 16-bit accesses. The UBO-focused logic didn't reject this,
which is now fixed. This fixes a number of VK-CTS regressions on a650+.

Fixes: bf49d4a084 ("freedreno/ir3: Enable load/store vectorization for SSBO access, too.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17040>
2022-06-23 10:46:31 +00:00
Jason Ekstrand deb36dc6c2 turnip: Use the new border color helpers
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15359>
2022-06-23 00:01:41 +00:00
Emma Anholt 13bf36588d ci/bare-metal: Consolidate needs declarations in .baremetal-test-*.
We had it set up for arm64 asan already, do it for everyone else too.  In
cleaning up the duplication, this fixes a pasteo in rpi3 which had the
"artifacts: false" on the wrong job, causing it to do a slow download of
the mesa build from gitlab.

Doing this required also moving the ".use-debian/arm_test" in as well, so
that its "needs:" didn't overwrite ours if it appeared after us in the
consumer's "extends:"

Should save about 20 seconds on rpi3 jobs.

Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17146>
2022-06-22 20:59:54 +00:00
Emma Anholt 69cad6dcb7 ci/freedreno: Turn a530 back on by default and update expectations.
I think it should be fixed since I redid how we manage serial around
restarts.  Haven't seen a fail in the manual runs I've done.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17004>
2022-06-22 20:07:36 +00:00
Emma Anholt 4e3c51cbd8 freedreno/a5xx: Set the buffer bit appropriately in XS_CTRL_REG0.
This seems to be how the bit gets used, from grepping my blob traces.
Hopefully this helps stabilize some stuff.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17004>
2022-06-22 20:07:36 +00:00
Emma Anholt 6cf2b24eaf freedreno/ir3: Disable image/ssbo 16-bit conversion folding pre-a6xx.
I don't see it in blob dumps, and the reordered args tripped up validation.

Fixes: 49dc60efa1 ("freedreno/ir3: Fold 16-bit conversions into image load/store src/dsts.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17004>
2022-06-22 20:07:36 +00:00
Connor Abbott d455838081 tu: Fix linemode for tessellation with isolines
Fixes: 542211676c ("turnip: enable VK_EXT_line_rasterization")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17190>
2022-06-22 17:57:53 +00:00
Danylo Piliaiev f1c1b9687e tu: Do not expose storage image/buffer features for PACK16 formats
We don't support storing into them.

Fixes GL CTS tests running through ZINK:
 KHR-GL46.packed_pixels.pbo_rectangle.*

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17168>
2022-06-22 14:39:47 +00:00
Connor Abbott c601ba332b ir3/sched: Fix could_sched() determination
This needs to be accurate so that when we split and then schedule a new
a0.x/a1.x/p0.x write we will eventually make progress. It wasn't taking
the kill_path into account which could create an infinite loop as we
keep scheduling writes whose uses are blocked because they are memory
instructions not on the kill_path.

Closes: #6413
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16635>
2022-06-22 10:09:13 +00:00
Danylo Piliaiev a8671b2182 meson/tu: Don't compile libdrm paths if KGSL is selected
Even if there is libdrm we shouldn't use it if KGSL is selected.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17173>
2022-06-22 11:52:36 +03:00
Emma Anholt 5f09b1ebe9 ci/bare-metal: Add test phase timeouts to all boards.
This should help with "marge got stuck for an hour and all I got was this
failed job with no results/" when a system intermittently wedges.

This replaces the BM_POE_TIMEOUT ("did we get something on serial in the
last 3 minutes?") that rpi had, in favor of checking that the whole test
job gets through in 20 minutes.

Acked-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17096>
2022-06-21 21:38:25 +00:00
Danylo Piliaiev 909e7aaf57 tu: Reset xfb_used at the end of a renderpass
Otherwise xfb_used could be true until the end of command buffer,
which is not what we intended it to be.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17162>
2022-06-21 21:15:10 +00:00
Emma Anholt 086faecbba turnip: Document some fields about resolves.
I noticed the unk12 pattern, and cwabbott and danylo had figured out some
more details.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17126>
2022-06-21 19:40:58 +00:00
Danylo Piliaiev 48540caec9 tu: Disable sample counting for 3d blits during occlusion query
Per Vulkan spec only "Draw" commands should be counted towards
occlusion query.

Apparently RB_SAMPLE_COUNT_CONTROL::UNK0 bool controls whether
sample counting is enabled, so we could use it to disable
sample counting for 3d blits which are sometimes used for
clear/copy/blit/gmem-store/resolve operations.

Fixes GL CTS tests running through Zink:
 dEQP-GLES3.functional.occlusion_query.depth_clear
 dEQP-GLES3.functional.occlusion_query.depth_clear_stencil_clear
 dEQP-GLES3.functional.occlusion_query.scissor_depth_clear_stencil_clear
 dEQP-GLES3.functional.occlusion_query.scissor_stencil_clear
 dEQP-GLES3.functional.occlusion_query.stencil_clear

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6559

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17138>
2022-06-21 13:13:36 +00:00
David Heidelberg 57ad38c2fc ci/freedreno: disable non-existing trace
Never existed in the repository.

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17137>
2022-06-20 16:36:10 +00:00
David Heidelberg dfe9b856cb ci/freedreno: update restricted traces to the brotli compressed version
Save some space on proxies and speedup network transfer to the runners.

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17016>
2022-06-20 12:42:41 +00:00
Chia-I Wu 858cd2797c freedreno/fdl: use XYZW swap for PIPE_FORMAT_X24S8_UINT
We used to use WZYX and apply swizzles.  Because swizzles apply for
border colors as well, the gallium driver un-swizzled the border colors
to cancel out swizzles.  That did not work for turnip because turnip
advertises customBorderColorWithoutFormat and does not know when to
un-swizzle.

This change replaces WZYX by XYZW and removes the swizzles.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6516
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16647>
2022-06-17 18:39:47 +00:00
Danylo Piliaiev 10f6191fb5 turnip: copy disasm strings for pipeline executables
A single compiled_shaders instance could be reused by several
pipelines, but strings from disasm info could be stolen only once.
So now we have to copy them.

Fixes crashes when using RenderDoc.

Fixes: 05329d7f9a
("tu: Implement pipeline caching with shared Vulkan cache")

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17053>
2022-06-16 08:45:34 +00:00
Connor Abbott cba6da2b21 tu: Save/restore *_BIN_CONTROL in 3d GMEM store path
These are normally only set once because it's constant across the entire
renderpass, but they're trashed by the 3d store path because it needs to
store to CCU instead of GMEM. Therefore we need to save/restore them. Do
it in a way compatible with #5181.

Fixes: b157a5d ("tu: Implement non-aligned multisample GMEM STORE_OP_STORE")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17058>
2022-06-16 01:10:24 +00:00
Connor Abbott a9d7b47613 tu: Add missing WFI to the 3d GMEM store path
Similar to the 2d path.

Fixes: b157a5d ("tu: Implement non-aligned multisample GMEM STORE_OP_STORE")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17058>
2022-06-16 01:10:24 +00:00
Connor Abbott 705c0d0373 tu: Fix 3d GMEM store swizzle in texture descriptor
Even though image views for attachments must use the identity swizzle,
there are cases where we have to add in our own swizzle, in particular
for D24S8 when the view is depth-only/stencil-only. Therefore we have to
reset it to the identity, similar to what we do with input attachments.

Fixes: b157a5d ("tu: Implement non-aligned multisample GMEM STORE_OP_STORE")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17058>
2022-06-16 01:10:24 +00:00
Connor Abbott 6dfabab08f freedreno/a6xx: Support more 3-component formats
These should be trivially enableable. This gets us some test coverage on
turnip because there are no tests of RGB32 texel buffers.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16980>
2022-06-15 22:48:38 +00:00
Connor Abbott 2e63c570dd tu: Enable uniform texture buffers with NPOT formats
This is enough for zink to expose ARB_texture_buffer_object_rgb32 and
therefore GL 4.0. We could enable sampled images with a few more
workarounds, but the blob doesn't bother and there isn't any need at the
moment.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16980>
2022-06-15 22:48:38 +00:00
Chia-I Wu af0080c4ef turnip: advertise VK_EXT_border_color_swizzle
We already support the functionality so just advertise it.  Pass all
dEQP-VK*border_swizzle*.

v2: update freedreno-a630-fails.txt

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17019>
2022-06-15 15:48:47 +00:00
Connor Abbott 169e03800d tu: Implement VK_EXT_color_write_enable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16936>
2022-06-14 23:18:17 +00:00
Connor Abbott 94be0dd0b8 tu: Implement extendedDynamicState2LogicOp
Because this impacts most of the registers in the BLEND draw state, we
make the entire draw state dynamic so that it all gets re-emitted when
the logicOp changes. This also lays the groundwork for
VK_EXT_color_write_enable.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16936>
2022-06-14 23:18:17 +00:00
Connor Abbott c23eb99357 tu: Fix partial-write LRZ determination
There were a few problems with this:

- It wasn't considering logic op at all, which is another source of
  reading from the destination.
- It was conditioned on the blend_enable_mask, so it was missing the
  case where there's no blending but some of the outputs were masked
  out.
- It wasn't considering attachments with less than 4 components (for
  example, normals in a typical deferred rendering setup) and would
  always consider them partially written unless the user added extra
  unnecessary components.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16936>
2022-06-14 23:18:17 +00:00
David Heidelberg a7f7f2a1dd ci/freedreno: fix A530 glmark2@ideas:speed=10000 trace
Just one-pixel change in rendering, look correct to me.

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16909>
2022-06-14 11:52:45 +00:00