tu: Disable sample counting for 3d blits during occlusion query

Per Vulkan spec only "Draw" commands should be counted towards
occlusion query.

Apparently RB_SAMPLE_COUNT_CONTROL::UNK0 bool controls whether
sample counting is enabled, so we could use it to disable
sample counting for 3d blits which are sometimes used for
clear/copy/blit/gmem-store/resolve operations.

Fixes GL CTS tests running through Zink:
 dEQP-GLES3.functional.occlusion_query.depth_clear
 dEQP-GLES3.functional.occlusion_query.depth_clear_stencil_clear
 dEQP-GLES3.functional.occlusion_query.scissor_depth_clear_stencil_clear
 dEQP-GLES3.functional.occlusion_query.scissor_stencil_clear
 dEQP-GLES3.functional.occlusion_query.stencil_clear

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6559

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17138>
This commit is contained in:
Danylo Piliaiev 2022-06-20 15:59:36 +03:00 committed by Marge Bot
parent 0c3fae4e6e
commit 48540caec9
3 changed files with 15 additions and 5 deletions

View File

@ -2166,7 +2166,7 @@ to upconvert to 32b float internally?
<!-- 0x888a-0x888f invalid -->
<reg32 offset="0x8890" name="RB_WINDOW_OFFSET" type="a6xx_reg_xy"/>
<reg32 offset="0x8891" name="RB_SAMPLE_COUNT_CONTROL">
<bitfield name="UNK0" pos="0" type="boolean"/>
<bitfield name="DISABLE" pos="0" type="boolean"/>
<bitfield name="COPY" pos="1" type="boolean"/>
</reg32>
<!-- 0x8892-0x8897 invalid -->

View File

@ -1113,6 +1113,9 @@ r3d_setup(struct tu_cmd_buffer *cmd,
tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_SC_CNTL,
A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE(2));
/* Disable sample counting in order to not affect occlusion query. */
tu_cs_emit_regs(cs, A6XX_RB_SAMPLE_COUNT_CONTROL(.disable = true));
if (cmd->state.predication_active) {
tu_cs_emit_pkt7(cs, CP_DRAW_PRED_ENABLE_LOCAL, 1);
tu_cs_emit(cs, 0);
@ -1148,6 +1151,9 @@ r3d_teardown(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
tu_cs_emit_pkt7(cs, CP_DRAW_PRED_ENABLE_LOCAL, 1);
tu_cs_emit(cs, 1);
}
/* Re-enable sample counting. */
tu_cs_emit_regs(cs, A6XX_RB_SAMPLE_COUNT_CONTROL(.disable = false));
}
/* blit ops - common interface for 2d/shader paths */
@ -2351,6 +2357,9 @@ tu_clear_sysmem_attachments(struct tu_cmd_buffer *cmd,
r3d_common(cmd, cs, false, clear_rts, false, cmd->state.subpass->samples);
/* Disable sample counting in order to not affect occlusion query. */
tu_cs_emit_regs(cs, A6XX_RB_SAMPLE_COUNT_CONTROL(.disable = true));
tu_cs_emit_regs(cs,
A6XX_SP_FS_RENDER_COMPONENTS(.dword = clear_components));
tu_cs_emit_regs(cs,
@ -2423,6 +2432,9 @@ tu_clear_sysmem_attachments(struct tu_cmd_buffer *cmd,
}
}
/* Re-enable sample counting. */
tu_cs_emit_regs(cs, A6XX_RB_SAMPLE_COUNT_CONTROL(.disable = false));
trace_end_sysmem_clear_all(&cmd->trace,
cs, mrt_count, rect_count);
}
@ -3047,6 +3059,8 @@ store_3d_blit(struct tu_cmd_buffer *cmd,
r3d_run(cmd, cs);
r3d_teardown(cmd, cs);
/* Draws write to the CCU, unlike CP_EVENT_WRITE::BLIT which writes to
* sysmem, and we generally assume that GMEM renderpasses leave their
* results in sysmem, so we need to flush manually here. The 3d blit path

View File

@ -60,10 +60,6 @@ KHR-Single-GL46.arrays_of_arrays_gl.SubroutineFunctionCalls2,Crash
KHR-Single-GL46.enhanced_layouts.xfb_capture_inactive_output_block_member,Fail
KHR-Single-GL46.enhanced_layouts.xfb_capture_struct,Fail
KHR-Single-GL46.enhanced_layouts.xfb_vertex_streams,Fail
dEQP-GLES3.functional.occlusion_query.depth_clear_stencil_clear,Fail
dEQP-GLES3.functional.occlusion_query.scissor_depth_clear_stencil_clear,Fail
dEQP-GLES3.functional.occlusion_query.scissor_stencil_clear,Fail
dEQP-GLES3.functional.occlusion_query.stencil_clear,Fail
dEQP-GLES31.functional.blend_equation_advanced.barrier.colorburn,Fail
dEQP-GLES31.functional.blend_equation_advanced.barrier.colordodge,Fail
dEQP-GLES31.functional.blend_equation_advanced.barrier.darken,Fail