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turnip: Document some fields about resolves. 

I noticed the unk12 pattern, and cwabbott and danylo had figured out some
more details.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17126>
This commit is contained in:
Emma Anholt 2022-06-07 14:08:52 -07:00 committed by Marge Bot
parent d4c664a670
commit 086faecbba
4 changed files with 15 additions and 7 deletions
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2
src/freedreno/common/freedreno_dev_info.h
View File

@ -70,7 +70,7 @@ struct fd_dev_info {
bool supports_multiview_mask;
/* info for setting RB_CCU_CNTL */
bool ccu_cntl_gmem_unk2;
bool concurrent_resolve;
bool has_z24uint_s8uint;
bool tess_use_shared;

2
src/freedreno/common/freedreno_devices.py
View File

@ -207,7 +207,7 @@ a6xx_gen1 = dict(
fibers_per_sp = 128 * 16,
reg_size_vec4 = 96,
instr_cache_size = 64,
ccu_cntl_gmem_unk2 = True,
concurrent_resolve = True,
indirect_draw_wfm_quirk = True,
depth_bounds_require_depth_test_quirk = True,
magic = dict(

14
src/freedreno/registers/adreno/a6xx.xml
View File

@ -2233,8 +2233,15 @@ to upconvert to 32b float internally?
then probably a component mask, I always see 0xf
</doc>
<bitfield name="CLEAR_MASK" low="4" high="7"/>
<bitfield name="UNK8" low="8" high="9"/>
<bitfield name="UNK12" low="12" high="15"/>
<!-- set when this is the last resolve on a650+ -->
<bitfield name="LAST" low="8" high="9"/>
<!--
a618 GLES: color render target number being resolved for RM6_RESOLVE, 0x8 for depth, 0x9 for separate stencil.
a618 VK: 0x8 for depth RM6_RESOLVE, 0x9 for separate stencil, 0 otherwise.
We believe this is related to concurrent resolves
-->
<bitfield name="BUFFER_ID" low="12" high="15"/>
</reg32>
<!-- 0x88e4-0x88ef invalid -->
<!-- always 0x0 ? -->
@ -2339,7 +2346,8 @@ to upconvert to 32b float internally?
<!-- GMEM offset of CCU depth cache -->
<bitfield name="DEPTH_OFFSET" low="12" high="20" shr="12" type="hex"/>
<bitfield name="GMEM" pos="22" type="boolean"/> <!-- set for GMEM path -->
<bitfield name="UNK2" pos="2" type="boolean"/> <!-- sometimes set with GMEM? -->
<!-- concurrent resolves are apparently a 2-bit enum on a650+ -->
<bitfield name="CONCURRENT_RESOLVE" pos="2" type="boolean"/>
<!--TODO: valid mask 0xfffffc1f -->
</reg32>
<reg32 offset="0x8e08" name="RB_NC_MODE_CNTL">

4
src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
View File

@ -762,7 +762,7 @@ emit_binning_pass(struct fd_batch *batch) assert_dt
OUT_REG(ring,
A6XX_RB_CCU_CNTL(.color_offset = screen->ccu_offset_gmem,
.gmem = true,
.unk2 = screen->info->a6xx.ccu_cntl_gmem_unk2));
.concurrent_resolve = screen->info->a6xx.concurrent_resolve));
}
static void
@ -830,7 +830,7 @@ fd6_emit_tile_init(struct fd_batch *batch) assert_dt
OUT_REG(ring,
A6XX_RB_CCU_CNTL(.color_offset = screen->ccu_offset_gmem,
.gmem = true,
.unk2 = screen->info->a6xx.ccu_cntl_gmem_unk2));
.concurrent_resolve = screen->info->a6xx.concurrent_resolve));
emit_zs(ring, pfb->zsbuf, batch->gmem_state);
emit_mrt(ring, pfb, batch->gmem_state);