tu: Implement VK_EXT_color_write_enable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16936>
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@ -532,7 +532,7 @@ Khronos extensions that are not part of any Vulkan version:
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VK_EXT_border_color_swizzle DONE (anv, lvp)
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VK_EXT_buffer_device_address DONE (radv)
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VK_EXT_calibrated_timestamps DONE (anv, lvp, radv)
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VK_EXT_color_write_enable DONE (anv, lvp, radv, v3dv)
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VK_EXT_color_write_enable DONE (anv, lvp, radv, tu, v3dv)
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VK_EXT_conditional_rendering DONE (anv, lvp, radv, tu)
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VK_EXT_conservative_rasterization DONE (anv/gen9+, radv)
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VK_EXT_custom_border_color DONE (anv, lvp, radv, tu, v3dv)
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@ -2855,6 +2855,22 @@ tu_CmdSetLineStippleEXT(VkCommandBuffer commandBuffer,
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tu_stub();
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}
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VKAPI_ATTR void VKAPI_CALL
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tu_CmdSetColorWriteEnableEXT(VkCommandBuffer commandBuffer, uint32_t attachmentCount,
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const VkBool32 *pColorWriteEnables)
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{
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TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
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uint32_t color_write_enable = 0;
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for (unsigned i = 0; i < attachmentCount; i++) {
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if (pColorWriteEnables[i])
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color_write_enable |= BIT(i);
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}
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cmd->state.color_write_enable = color_write_enable;
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cmd->state.dirty |= TU_CMD_DIRTY_BLEND;
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}
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static void
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tu_flush_for_access(struct tu_cache_state *cache,
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enum tu_cmd_access_mask src_mask,
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@ -3819,6 +3835,10 @@ tu6_calculate_lrz_state(struct tu_cmd_buffer *cmd,
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cmd->state.logic_op_enabled && cmd->state.rop_reads_dst)
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gras_lrz_cntl.lrz_write = false;
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if ((cmd->state.pipeline->dynamic_state_mask & BIT(TU_DYNAMIC_STATE_COLOR_WRITE_ENABLE)) &&
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cmd->state.color_write_enable != MASK(cmd->state.pipeline->num_rts))
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gras_lrz_cntl.lrz_write = false;
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/* LRZ is disabled until it is cleared, which means that one "wrong"
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* depth test or shader could disable LRZ until depth buffer is cleared.
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*/
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@ -4053,6 +4073,10 @@ tu6_emit_blend(struct tu_cs *cs, struct tu_cmd_buffer *cmd)
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struct tu_pipeline *pipeline = cmd->state.pipeline;
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uint32_t color_write_enable = cmd->state.pipeline_color_write_enable;
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if (pipeline->dynamic_state_mask &
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BIT(TU_DYNAMIC_STATE_COLOR_WRITE_ENABLE))
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color_write_enable &= cmd->state.color_write_enable;
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for (unsigned i = 0; i < pipeline->num_rts; i++) {
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tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_CONTROL(i), 2);
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if (color_write_enable & BIT(i)) {
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@ -4069,7 +4093,8 @@ tu6_emit_blend(struct tu_cs *cs, struct tu_cmd_buffer *cmd)
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uint32_t blend_enable_mask =
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(cmd->state.logic_op_enabled && cmd->state.rop_reads_dst) ?
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color_write_enable : cmd->state.pipeline_blend_enable;
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color_write_enable : (cmd->state.pipeline_blend_enable &
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cmd->state.color_write_enable);
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tu_cs_emit_pkt4(cs, REG_A6XX_SP_BLEND_CNTL, 1);
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tu_cs_emit(cs, cmd->state.sp_blend_cntl |
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@ -232,6 +232,7 @@ get_device_extensions(const struct tu_physical_device *device,
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.IMG_filter_cubic = device->info->a6xx.has_tex_filter_cubic,
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.VALVE_mutable_descriptor_type = true,
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.EXT_image_2d_view_of_3d = true,
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.EXT_color_write_enable = true,
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};
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}
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@ -886,6 +887,12 @@ tu_GetPhysicalDeviceFeatures2(VkPhysicalDevice physicalDevice,
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features->sampler2DViewOf3D = true;
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break;
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}
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case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COLOR_WRITE_ENABLE_FEATURES_EXT: {
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VkPhysicalDeviceColorWriteEnableFeaturesEXT *features =
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(VkPhysicalDeviceColorWriteEnableFeaturesEXT *)ext;
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features->colorWriteEnable = true;
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break;
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}
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default:
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break;
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@ -2155,6 +2155,17 @@ tu6_emit_rb_mrt_controls(struct tu_pipeline *pipeline,
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bool *rop_reads_dst,
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uint32_t *color_bandwidth_per_sample)
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{
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const VkPipelineColorWriteCreateInfoEXT *color_info =
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vk_find_struct_const(blend_info->pNext,
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PIPELINE_COLOR_WRITE_CREATE_INFO_EXT);
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/* The static state is ignored if it's dynamic. In that case assume
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* everything is enabled and then the appropriate registers will be zero'd
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* dynamically.
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*/
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if (pipeline->dynamic_state_mask & BIT(TU_DYNAMIC_STATE_COLOR_WRITE_ENABLE))
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color_info = NULL;
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*rop_reads_dst = false;
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*color_bandwidth_per_sample = 0;
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@ -2174,7 +2185,8 @@ tu6_emit_rb_mrt_controls(struct tu_pipeline *pipeline,
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uint32_t rb_mrt_control = 0;
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uint32_t rb_mrt_blend_control = 0;
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if (format != VK_FORMAT_UNDEFINED) {
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if (format != VK_FORMAT_UNDEFINED &&
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(!color_info || color_info->pColorWriteEnables[i])) {
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const bool has_alpha = vk_format_has_alpha(format);
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rb_mrt_control =
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@ -3149,6 +3161,17 @@ tu_pipeline_builder_parse_dynamic(struct tu_pipeline_builder *builder,
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pipeline->dynamic_state_mask |= BIT(TU_DYNAMIC_STATE_BLEND);
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pipeline->dynamic_state_mask |= BIT(TU_DYNAMIC_STATE_LOGIC_OP);
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break;
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case VK_DYNAMIC_STATE_COLOR_WRITE_ENABLE_EXT:
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pipeline->sp_blend_cntl_mask &= ~A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK;
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pipeline->rb_blend_cntl_mask &= ~A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK;
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pipeline->dynamic_state_mask |= BIT(TU_DYNAMIC_STATE_BLEND);
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/* Dynamic color write enable doesn't directly change any of the
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* registers, but it causes us to make some of the registers 0, so we
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* set this dynamic state instead of making the register dynamic.
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*/
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pipeline->dynamic_state_mask |= BIT(TU_DYNAMIC_STATE_COLOR_WRITE_ENABLE);
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break;
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default:
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assert(!"unsupported dynamic state");
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break;
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@ -3615,7 +3638,8 @@ tu_pipeline_builder_parse_multisample_and_color_blend(
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VkFormat format = builder->color_attachment_formats[i];
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unsigned mask = MASK(vk_format_get_nr_components(format));
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if (format != VK_FORMAT_UNDEFINED &&
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(blendAttachment.colorWriteMask & mask) != mask) {
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((blendAttachment.colorWriteMask & mask) != mask ||
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!(pipeline->color_write_enable & BIT(i)))) {
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pipeline->lrz.force_disable_mask |= TU_LRZ_FORCE_DISABLE_WRITE;
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}
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}
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@ -701,6 +701,7 @@ enum tu_dynamic_state
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TU_DYNAMIC_STATE_PRIMITIVE_TOPOLOGY = TU_DYNAMIC_STATE_COUNT,
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TU_DYNAMIC_STATE_PRIMITIVE_RESTART_ENABLE,
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TU_DYNAMIC_STATE_LOGIC_OP,
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TU_DYNAMIC_STATE_COLOR_WRITE_ENABLE,
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/* re-use the line width enum as it uses GRAS_SU_CNTL: */
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TU_DYNAMIC_STATE_GRAS_SU_CNTL = VK_DYNAMIC_STATE_LINE_WIDTH,
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};
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@ -1169,6 +1170,7 @@ struct tu_cmd_state
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uint32_t rb_mrt_control_rop;
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uint32_t rb_blend_cntl, sp_blend_cntl;
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uint32_t pipeline_color_write_enable, pipeline_blend_enable;
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uint32_t color_write_enable;
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bool logic_op_enabled;
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bool rop_reads_dst;
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enum pc_di_primtype primtype;
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