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freedreno/a6xx: VPC_SO_NCOMP is actually VPC_SO_BUFFER_STRIDE 

This answers the question in a comment in turnip, and fixes some GL46
tests and piglit tests.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17494>
This commit is contained in:
Connor Abbott 2022-07-12 16:55:03 +02:00 committed by Marge Bot
parent 7976d558d5
commit cf0cfd572e
5 changed files with 19 additions and 42 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/freedreno/ci/freedreno-a630-fails.txt
View File

@ -176,14 +176,6 @@ spec@arb_timer_query@timestamp-get,Fail
# Note: no FS, rasterizer discard enabled.
spec@arb_transform_feedback3@arb_transform_feedback3-ext_interleaved_two_bufs_vs,Fail
spec@arb_transform_feedback3@gl_skipcomponents1-1,Fail
spec@arb_transform_feedback3@gl_skipcomponents1234,Fail
spec@arb_transform_feedback3@gl_skipcomponents1-2,Fail
spec@arb_transform_feedback3@gl_skipcomponents1-3,Fail
spec@arb_transform_feedback3@gl_skipcomponents1-gl_nextbuffer,Fail
spec@arb_transform_feedback3@gl_skipcomponents2,Fail
spec@arb_transform_feedback3@gl_skipcomponents3,Fail
spec@arb_transform_feedback3@gl_skipcomponents4,Fail
spec@arb_vertex_type_2_10_10_10_rev@attrib-p-type-size-match,Fail
spec@egl 1.4@eglterminate then unbind context,Fail

2
src/freedreno/registers/adreno/a6xx.xml
View File

@ -2500,7 +2500,7 @@ to upconvert to 32b float internally?
<array offset="0x921a" name="VPC_SO" stride="7" length="4">
<reg64 offset="0" name="BUFFER_BASE" type="waddress" align="32"/>
<reg32 offset="2" name="BUFFER_SIZE" low="2" high="31" shr="2"/>
<reg32 offset="3" name="NCOMP" low="0" high="9"/> <!-- component count -->
<reg32 offset="3" name="BUFFER_STRIDE" low="0" high="9" shr="2"/>
<reg32 offset="4" name="BUFFER_OFFSET" low="2" high="31" shr="2"/>
<reg64 offset="5" name="FLUSH_BASE" type="waddress" align="32"/>
</array>

17
src/freedreno/vulkan/tu_pipeline.c
View File

@ -789,7 +789,6 @@ tu6_setup_streamout(struct tu_cs *cs,
#define A6XX_SO_PROG_DWORDS 64
uint32_t prog[A6XX_SO_PROG_DWORDS * IR3_MAX_SO_STREAMS] = {};
BITSET_DECLARE(valid_dwords, A6XX_SO_PROG_DWORDS * IR3_MAX_SO_STREAMS) = {0};
uint32_t ncomp[IR3_MAX_SO_BUFFERS] = {};
/* TODO: streamout state should be in a non-GMEM draw state */
@ -803,8 +802,6 @@ tu6_setup_streamout(struct tu_cs *cs,
return;
}
/* is there something to do with info->stride[i]? */
for (unsigned i = 0; i < info->num_outputs; i++) {
const struct ir3_stream_output *out = &info->output[i];
unsigned k = out->register_index;
@ -814,8 +811,6 @@ tu6_setup_streamout(struct tu_cs *cs,
if (k >= v->outputs_count || v->outputs[k].regid == INVALID_REG)
continue;
ncomp[out->output_buffer] += out->num_components;
/* linkage map sorted by order frag shader wants things, so
* a bit less ideal here..
*/
@ -855,17 +850,17 @@ tu6_setup_streamout(struct tu_cs *cs,
tu_cs_emit_pkt7(cs, CP_CONTEXT_REG_BUNCH, 10 + 2 * prog_count);
tu_cs_emit(cs, REG_A6XX_VPC_SO_STREAM_CNTL);
tu_cs_emit(cs, A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE(info->streams_written) |
COND(ncomp[0] > 0,
COND(info->stride[0] > 0,
A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM(1 + info->buffer_to_stream[0])) |
COND(ncomp[1] > 0,
COND(info->stride[1] > 0,
A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM(1 + info->buffer_to_stream[1])) |
COND(ncomp[2] > 0,
COND(info->stride[2] > 0,
A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM(1 + info->buffer_to_stream[2])) |
COND(ncomp[3] > 0,
COND(info->stride[3] > 0,
A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM(1 + info->buffer_to_stream[3])));
for (uint32_t i = 0; i < 4; i++) {
tu_cs_emit(cs, REG_A6XX_VPC_SO_NCOMP(i));
tu_cs_emit(cs, ncomp[i]);
tu_cs_emit(cs, REG_A6XX_VPC_SO_BUFFER_STRIDE(i));
tu_cs_emit(cs, info->stride[i]);
}
bool first = true;
BITSET_FOREACH_RANGE(start, end, valid_dwords,

28
src/gallium/drivers/freedreno/a6xx/fd6_program.c
View File

@ -197,9 +197,7 @@ setup_stream_out(struct fd_context *ctx, struct fd6_program_state *state,
#define A6XX_SO_PROG_DWORDS 64
uint32_t prog[A6XX_SO_PROG_DWORDS * IR3_MAX_SO_STREAMS] = {};
BITSET_DECLARE(valid_dwords, A6XX_SO_PROG_DWORDS * IR3_MAX_SO_STREAMS) = {0};
uint32_t ncomp[PIPE_MAX_SO_BUFFERS];
memset(ncomp, 0, sizeof(ncomp));
memset(prog, 0, sizeof(prog));
for (unsigned i = 0; i < strmout->num_outputs; i++) {
@ -207,8 +205,6 @@ setup_stream_out(struct fd_context *ctx, struct fd6_program_state *state,
unsigned k = out->register_index;
unsigned idx;
ncomp[out->output_buffer] += out->num_components;
/* linkage map sorted by order frag shader wants things, so
* a bit less ideal here..
*/
@ -255,18 +251,18 @@ setup_stream_out(struct fd_context *ctx, struct fd6_program_state *state,
OUT_RING(ring, REG_A6XX_VPC_SO_STREAM_CNTL);
OUT_RING(ring,
A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE(0x1) |
COND(ncomp[0] > 0, A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM(1)) |
COND(ncomp[1] > 0, A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM(1)) |
COND(ncomp[2] > 0, A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM(1)) |
COND(ncomp[3] > 0, A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM(1)));
OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(0));
OUT_RING(ring, ncomp[0]);
OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(1));
OUT_RING(ring, ncomp[1]);
OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(2));
OUT_RING(ring, ncomp[2]);
OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(3));
OUT_RING(ring, ncomp[3]);
COND(strmout->stride[0] > 0, A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM(1)) |
COND(strmout->stride[1] > 0, A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM(1)) |
COND(strmout->stride[2] > 0, A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM(1)) |
COND(strmout->stride[3] > 0, A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM(1)));
OUT_RING(ring, REG_A6XX_VPC_SO_BUFFER_STRIDE(0));
OUT_RING(ring, strmout->stride[0]);
OUT_RING(ring, REG_A6XX_VPC_SO_BUFFER_STRIDE(1));
OUT_RING(ring, strmout->stride[1]);
OUT_RING(ring, REG_A6XX_VPC_SO_BUFFER_STRIDE(2));
OUT_RING(ring, strmout->stride[2]);
OUT_RING(ring, REG_A6XX_VPC_SO_BUFFER_STRIDE(3));
OUT_RING(ring, strmout->stride[3]);
bool first = true;
BITSET_FOREACH_RANGE (start, end, valid_dwords,

6
src/gallium/drivers/zink/ci/zink-tu-a630-fails.txt
View File

@ -5,9 +5,6 @@ GTF-GL46.gtf21.GL3Tests.texture_lod_bias.texture_lod_bias_all,Fail
GTF-GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_blit_functionality_multisampled_to_singlesampled_blit,Fail
GTF-GL46.gtf30.GL3Tests.sgis_texture_lod.sgis_texture_lod_basic_lod_selection,Fail
GTF-GL46.gtf32.GL3Tests.draw_elements_base_vertex.draw_elements_base_vertex_invalid_mode,Fail
GTF-GL46.gtf40.GL3Tests.transform_feedback3.transform_feedback3_multiple_streams,Fail
GTF-GL46.gtf40.GL3Tests.transform_feedback3.transform_feedback3_skip_components,Fail
GTF-GL46.gtf40.GL3Tests.transform_feedback3.transform_feedback3_skip_multiple_buffers,Fail
KHR-GL46.buffer_storage.map_persistent_draw,Fail
KHR-GL46.copy_image.functional,Fail
KHR-GL46.direct_state_access.buffers_functional,Fail
@ -21,8 +18,5 @@ KHR-GL46.texture_view.view_classes,Fail
KHR-GL46.vertex_attrib_64bit.vao,Fail
KHR-Single-GL46.arrays_of_arrays_gl.AtomicUsage,Fail
KHR-Single-GL46.arrays_of_arrays_gl.SubroutineFunctionCalls2,Crash
KHR-Single-GL46.enhanced_layouts.xfb_capture_inactive_output_block_member,Fail
KHR-Single-GL46.enhanced_layouts.xfb_capture_struct,Fail
KHR-Single-GL46.enhanced_layouts.xfb_vertex_streams,Fail
dEQP-GLES31.functional.texture.border_clamp.range_clamp.linear_srgb_color,Fail
dEQP-GLES31.functional.texture.border_clamp.range_clamp.nearest_srgb_color,Fail