tu: Implement extendedDynamicState2LogicOp
Because this impacts most of the registers in the BLEND draw state, we make the entire draw state dynamic so that it all gets re-emitted when the logicOp changes. This also lays the groundwork for VK_EXT_color_write_enable. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16936>
This commit is contained in:
Connor Abbott
Marge Bot
parent
c23eb99357
commit
94be0dd0b8
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@ -2334,14 +2334,13 @@ tu_CmdBindPipeline(VkCommandBuffer commandBuffer,
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if (!(cmd->state.dirty & TU_CMD_DIRTY_DRAW_STATE)) {
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uint32_t mask = ~pipeline->dynamic_state_mask & BITFIELD_MASK(TU_DYNAMIC_STATE_COUNT);
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tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3 * (9 + util_bitcount(mask)));
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tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3 * (8 + util_bitcount(mask)));
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tu_cs_emit_draw_state(cs, TU_DRAW_STATE_PROGRAM_CONFIG, pipeline->program.config_state);
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tu_cs_emit_draw_state(cs, TU_DRAW_STATE_PROGRAM, pipeline->program.state);
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tu_cs_emit_draw_state(cs, TU_DRAW_STATE_PROGRAM_BINNING, pipeline->program.binning_state);
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tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VI, pipeline->vi.state);
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tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VI_BINNING, pipeline->vi.binning_state);
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tu_cs_emit_draw_state(cs, TU_DRAW_STATE_RAST, pipeline->rast_state);
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tu_cs_emit_draw_state(cs, TU_DRAW_STATE_BLEND, pipeline->blend_state);
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tu_cs_emit_draw_state(cs, TU_DRAW_STATE_PRIM_MODE_SYSMEM, pipeline->prim_order_state_sysmem);
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tu_cs_emit_draw_state(cs, TU_DRAW_STATE_PRIM_MODE_GMEM, pipeline->prim_order_state_gmem);
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@ -2430,8 +2429,48 @@ tu_CmdBindPipeline(VkCommandBuffer commandBuffer,
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UPDATE_REG(rb_stencil_cntl, RB_STENCIL_CNTL);
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UPDATE_REG(pc_raster_cntl, RASTERIZER_DISCARD);
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UPDATE_REG(vpc_unknown_9107, RASTERIZER_DISCARD);
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UPDATE_REG(sp_blend_cntl, BLEND);
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UPDATE_REG(rb_blend_cntl, BLEND);
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for (unsigned i = 0; i < pipeline->num_rts; i++) {
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if ((cmd->state.rb_mrt_control[i] & pipeline->rb_mrt_control_mask) !=
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pipeline->rb_mrt_control[i]) {
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cmd->state.rb_mrt_control[i] &= ~pipeline->rb_mrt_control_mask;
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cmd->state.rb_mrt_control[i] |= pipeline->rb_mrt_control[i];
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cmd->state.dirty |= TU_CMD_DIRTY_BLEND;
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}
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if (cmd->state.rb_mrt_blend_control[i] != pipeline->rb_mrt_blend_control[i]) {
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cmd->state.rb_mrt_blend_control[i] = pipeline->rb_mrt_blend_control[i];
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cmd->state.dirty |= TU_CMD_DIRTY_BLEND;
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}
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}
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#undef UPDATE_REG
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if (cmd->state.pipeline_color_write_enable != pipeline->color_write_enable) {
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cmd->state.pipeline_color_write_enable = pipeline->color_write_enable;
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cmd->state.dirty |= TU_CMD_DIRTY_BLEND;
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}
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if (cmd->state.pipeline_blend_enable != pipeline->blend_enable) {
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cmd->state.pipeline_blend_enable = pipeline->blend_enable;
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cmd->state.dirty |= TU_CMD_DIRTY_BLEND;
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}
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if (cmd->state.logic_op_enabled != pipeline->logic_op_enabled) {
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cmd->state.logic_op_enabled = pipeline->logic_op_enabled;
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cmd->state.dirty |= TU_CMD_DIRTY_BLEND;
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}
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if (!(pipeline->dynamic_state_mask & BIT(TU_DYNAMIC_STATE_LOGIC_OP)) &&
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cmd->state.rop_reads_dst != pipeline->rop_reads_dst) {
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cmd->state.rop_reads_dst = pipeline->rop_reads_dst;
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cmd->state.dirty |= TU_CMD_DIRTY_BLEND;
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}
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if (cmd->state.dynamic_state[TU_DYNAMIC_STATE_BLEND].size != pipeline->num_rts * 3 + 4) {
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cmd->state.dirty |= TU_CMD_DIRTY_BLEND;
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}
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if (!(pipeline->dynamic_state_mask & BIT(TU_DYNAMIC_STATE_BLEND))) {
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cmd->state.dirty &= ~TU_CMD_DIRTY_BLEND;
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}
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if (pipeline->rb_depth_cntl_disable)
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cmd->state.dirty |= TU_CMD_DIRTY_RB_DEPTH_CNTL;
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}
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@ -2793,7 +2832,12 @@ VKAPI_ATTR void VKAPI_CALL
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tu_CmdSetLogicOpEXT(VkCommandBuffer commandBuffer,
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VkLogicOp logicOp)
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{
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tu_stub();
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TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
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cmd->state.rb_mrt_control_rop =
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tu6_rb_mrt_control_rop(logicOp, &cmd->state.rop_reads_dst);
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cmd->state.dirty |= TU_CMD_DIRTY_BLEND;
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}
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VKAPI_ATTR void VKAPI_CALL
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@ -3770,6 +3814,11 @@ tu6_calculate_lrz_state(struct tu_cmd_buffer *cmd,
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gras_lrz_cntl.z_test_enable = z_read_enable;
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gras_lrz_cntl.z_bounds_enable = z_bounds_enable;
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/* See comment in tu_pipeline about disabling LRZ write for blending. */
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if ((cmd->state.pipeline->dynamic_state_mask & BIT(TU_DYNAMIC_STATE_LOGIC_OP)) &&
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cmd->state.logic_op_enabled && cmd->state.rop_reads_dst)
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gras_lrz_cntl.lrz_write = false;
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/* LRZ is disabled until it is cleared, which means that one "wrong"
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* depth test or shader could disable LRZ until depth buffer is cleared.
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*/
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@ -3998,6 +4047,41 @@ tu6_build_depth_plane_z_mode(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
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tu_cs_emit(cs, A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(zmode));
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}
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static void
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tu6_emit_blend(struct tu_cs *cs, struct tu_cmd_buffer *cmd)
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{
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struct tu_pipeline *pipeline = cmd->state.pipeline;
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uint32_t color_write_enable = cmd->state.pipeline_color_write_enable;
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for (unsigned i = 0; i < pipeline->num_rts; i++) {
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tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_CONTROL(i), 2);
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if (color_write_enable & BIT(i)) {
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tu_cs_emit(cs, cmd->state.rb_mrt_control[i] |
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((cmd->state.logic_op_enabled ?
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cmd->state.rb_mrt_control_rop : 0) &
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~pipeline->rb_mrt_control_mask));
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tu_cs_emit(cs, cmd->state.rb_mrt_blend_control[i]);
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} else {
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tu_cs_emit(cs, 0);
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tu_cs_emit(cs, 0);
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}
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}
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uint32_t blend_enable_mask =
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(cmd->state.logic_op_enabled && cmd->state.rop_reads_dst) ?
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color_write_enable : cmd->state.pipeline_blend_enable;
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tu_cs_emit_pkt4(cs, REG_A6XX_SP_BLEND_CNTL, 1);
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tu_cs_emit(cs, cmd->state.sp_blend_cntl |
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(A6XX_SP_BLEND_CNTL_ENABLE_BLEND(blend_enable_mask) &
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~pipeline->sp_blend_cntl_mask));
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tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLEND_CNTL, 1);
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tu_cs_emit(cs, cmd->state.rb_blend_cntl |
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(A6XX_RB_BLEND_CNTL_ENABLE_BLEND(blend_enable_mask) &
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~pipeline->rb_blend_cntl_mask));
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}
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static VkResult
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tu6_draw_common(struct tu_cmd_buffer *cmd,
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struct tu_cs *cs,
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@ -4043,7 +4127,9 @@ tu6_draw_common(struct tu_cmd_buffer *cmd,
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if (!(cmd->state.dirty & ~TU_CMD_DIRTY_COMPUTE_DESC_SETS_LOAD))
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return VK_SUCCESS;
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bool dirty_lrz = cmd->state.dirty & (TU_CMD_DIRTY_LRZ | TU_CMD_DIRTY_RB_DEPTH_CNTL | TU_CMD_DIRTY_RB_STENCIL_CNTL);
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bool dirty_lrz =
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cmd->state.dirty & (TU_CMD_DIRTY_LRZ | TU_CMD_DIRTY_RB_DEPTH_CNTL |
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TU_CMD_DIRTY_RB_STENCIL_CNTL | TU_CMD_DIRTY_BLEND);
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struct tu_descriptor_state *descriptors_state =
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&cmd->descriptors[VK_PIPELINE_BIND_POINT_GRAPHICS];
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@ -4103,6 +4189,12 @@ tu6_draw_common(struct tu_cmd_buffer *cmd,
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pipeline->z_negative_one_to_one);
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}
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if (cmd->state.dirty & TU_CMD_DIRTY_BLEND) {
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struct tu_cs cs = tu_cmd_dynamic_state(cmd, TU_DYNAMIC_STATE_BLEND,
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4 + 3 * cmd->state.pipeline->num_rts);
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tu6_emit_blend(&cs, cmd);
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}
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/* for the first draw in a renderpass, re-emit all the draw states
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*
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* and if a draw-state disabling path (CmdClearAttachments 3D fallback) was
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@ -4122,7 +4214,6 @@ tu6_draw_common(struct tu_cmd_buffer *cmd,
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tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VI, pipeline->vi.state);
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tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VI_BINNING, pipeline->vi.binning_state);
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tu_cs_emit_draw_state(cs, TU_DRAW_STATE_RAST, pipeline->rast_state);
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tu_cs_emit_draw_state(cs, TU_DRAW_STATE_BLEND, pipeline->blend_state);
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tu_cs_emit_draw_state(cs, TU_DRAW_STATE_PRIM_MODE_SYSMEM, pipeline->prim_order_state_sysmem);
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tu_cs_emit_draw_state(cs, TU_DRAW_STATE_PRIM_MODE_GMEM, pipeline->prim_order_state_gmem);
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tu_cs_emit_draw_state(cs, TU_DRAW_STATE_SHADER_GEOM_CONST, cmd->state.shader_const[0]);
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@ -4143,7 +4234,7 @@ tu6_draw_common(struct tu_cmd_buffer *cmd,
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/* emit draw states that were just updated
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* note we eventually don't want to have to emit anything here
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*/
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bool emit_binding_stride = false;
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bool emit_binding_stride = false, emit_blend = false;
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uint32_t draw_state_count =
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((cmd->state.dirty & TU_CMD_DIRTY_SHADER_CONSTS) ? 2 : 0) +
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((cmd->state.dirty & TU_CMD_DIRTY_DESC_SETS_LOAD) ? 1 : 0) +
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@ -4157,6 +4248,12 @@ tu6_draw_common(struct tu_cmd_buffer *cmd,
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draw_state_count += 1;
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}
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if ((cmd->state.dirty & TU_CMD_DIRTY_BLEND) &&
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(pipeline->dynamic_state_mask & BIT(TU_DYNAMIC_STATE_BLEND))) {
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emit_blend = true;
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draw_state_count += 1;
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}
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if (draw_state_count > 0)
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tu_cs_emit_pkt7(cs, CP_SET_DRAW_STATE, 3 * draw_state_count);
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@ -4172,6 +4269,10 @@ tu6_draw_common(struct tu_cmd_buffer *cmd,
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tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DYNAMIC + TU_DYNAMIC_STATE_VB_STRIDE,
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cmd->state.dynamic_state[TU_DYNAMIC_STATE_VB_STRIDE]);
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}
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if (emit_blend) {
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tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DYNAMIC + TU_DYNAMIC_STATE_BLEND,
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cmd->state.dynamic_state[TU_DYNAMIC_STATE_BLEND]);
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}
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if (cmd->state.dirty & TU_CMD_DIRTY_VS_PARAMS)
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tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VS_PARAMS, cmd->state.vs_params);
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@ -772,7 +772,7 @@ tu_GetPhysicalDeviceFeatures2(VkPhysicalDevice physicalDevice,
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VkPhysicalDeviceExtendedDynamicState2FeaturesEXT *features =
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(VkPhysicalDeviceExtendedDynamicState2FeaturesEXT *)ext;
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features->extendedDynamicState2 = true;
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features->extendedDynamicState2LogicOp = false;
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features->extendedDynamicState2LogicOp = true;
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features->extendedDynamicState2PatchControlPoints = false;
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break;
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}
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@ -2140,26 +2140,33 @@ tu6_rb_mrt_control(const VkPipelineColorBlendAttachmentState *att,
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return rb_mrt_control;
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}
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uint32_t
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tu6_rb_mrt_control_rop(VkLogicOp op, bool *rop_reads_dst)
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{
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*rop_reads_dst = tu_logic_op_reads_dst(op);
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return A6XX_RB_MRT_CONTROL_ROP_ENABLE |
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A6XX_RB_MRT_CONTROL_ROP_CODE(tu6_rop(op));
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}
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static void
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tu6_emit_rb_mrt_controls(struct tu_cs *cs,
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tu6_emit_rb_mrt_controls(struct tu_pipeline *pipeline,
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const VkPipelineColorBlendStateCreateInfo *blend_info,
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const VkFormat attachment_formats[MAX_RTS],
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uint32_t *blend_enable_mask,
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bool *rop_reads_dst,
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uint32_t *color_bandwidth_per_sample)
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{
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*blend_enable_mask = 0;
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*rop_reads_dst = false;
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*color_bandwidth_per_sample = 0;
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bool rop_reads_dst = false;
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uint32_t rb_mrt_control_rop = 0;
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if (blend_info->logicOpEnable) {
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rop_reads_dst = tu_logic_op_reads_dst(blend_info->logicOp);
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rb_mrt_control_rop =
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A6XX_RB_MRT_CONTROL_ROP_ENABLE |
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A6XX_RB_MRT_CONTROL_ROP_CODE(tu6_rop(blend_info->logicOp));
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pipeline->logic_op_enabled = true;
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rb_mrt_control_rop = tu6_rb_mrt_control_rop(blend_info->logicOp,
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rop_reads_dst);
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}
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uint32_t total_bpp = 0;
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pipeline->num_rts = blend_info->attachmentCount;
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for (uint32_t i = 0; i < blend_info->attachmentCount; i++) {
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const VkPipelineColorBlendAttachmentState *att =
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&blend_info->pAttachments[i];
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@ -2189,22 +2196,24 @@ tu6_emit_rb_mrt_controls(struct tu_cs *cs,
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}
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total_bpp += write_bpp;
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pipeline->color_write_enable |= BIT(i);
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if (att->blendEnable)
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pipeline->blend_enable |= BIT(i);
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if (att->blendEnable || rop_reads_dst) {
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*blend_enable_mask |= 1 << i;
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total_bpp += write_bpp;
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}
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}
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tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_CONTROL(i), 2);
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tu_cs_emit(cs, rb_mrt_control);
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tu_cs_emit(cs, rb_mrt_blend_control);
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pipeline->rb_mrt_control[i] = rb_mrt_control & pipeline->rb_mrt_control_mask;
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pipeline->rb_mrt_blend_control[i] = rb_mrt_blend_control;
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}
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*color_bandwidth_per_sample = total_bpp / 8;
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}
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static void
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tu6_emit_blend_control(struct tu_cs *cs,
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tu6_emit_blend_control(struct tu_pipeline *pipeline,
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uint32_t blend_enable_mask,
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bool dual_src_blend,
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const VkPipelineMultisampleStateCreateInfo *msaa_info)
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@ -2213,20 +2222,36 @@ tu6_emit_blend_control(struct tu_cs *cs,
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msaa_info->pSampleMask ? (*msaa_info->pSampleMask & 0xffff)
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: ((1 << msaa_info->rasterizationSamples) - 1);
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tu_cs_emit_regs(cs,
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A6XX_SP_BLEND_CNTL(.enable_blend = blend_enable_mask,
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.dual_color_in_enable = dual_src_blend,
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.alpha_to_coverage = msaa_info->alphaToCoverageEnable,
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.unk8 = true));
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pipeline->sp_blend_cntl =
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A6XX_SP_BLEND_CNTL(.enable_blend = blend_enable_mask,
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.dual_color_in_enable = dual_src_blend,
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.alpha_to_coverage = msaa_info->alphaToCoverageEnable,
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.unk8 = true).value & pipeline->sp_blend_cntl_mask;
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/* set A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND only when enabled? */
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tu_cs_emit_regs(cs,
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A6XX_RB_BLEND_CNTL(.enable_blend = blend_enable_mask,
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.independent_blend = true,
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.sample_mask = sample_mask,
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.dual_color_in_enable = dual_src_blend,
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.alpha_to_coverage = msaa_info->alphaToCoverageEnable,
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.alpha_to_one = msaa_info->alphaToOneEnable));
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pipeline->rb_blend_cntl =
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A6XX_RB_BLEND_CNTL(.enable_blend = blend_enable_mask,
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.independent_blend = true,
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.sample_mask = sample_mask,
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.dual_color_in_enable = dual_src_blend,
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.alpha_to_coverage = msaa_info->alphaToCoverageEnable,
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.alpha_to_one = msaa_info->alphaToOneEnable).value &
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pipeline->rb_blend_cntl_mask;
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}
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static void
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tu6_emit_blend(struct tu_cs *cs,
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struct tu_pipeline *pipeline)
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{
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tu_cs_emit_regs(cs, A6XX_SP_BLEND_CNTL(.dword = pipeline->sp_blend_cntl));
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tu_cs_emit_regs(cs, A6XX_RB_BLEND_CNTL(.dword = pipeline->rb_blend_cntl));
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for (unsigned i = 0; i < pipeline->num_rts; i++) {
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tu_cs_emit_regs(cs,
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A6XX_RB_MRT_CONTROL(i, .dword = pipeline->rb_mrt_control[i]),
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A6XX_RB_MRT_BLEND_CONTROL(i, .dword = pipeline->rb_mrt_blend_control[i]));
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}
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}
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static uint32_t
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@ -3031,6 +3056,9 @@ tu_pipeline_builder_parse_dynamic(struct tu_pipeline_builder *builder,
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pipeline->rb_stencil_cntl_mask = ~0u;
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pipeline->pc_raster_cntl_mask = ~0u;
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pipeline->vpc_unknown_9107_mask = ~0u;
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pipeline->sp_blend_cntl_mask = ~0u;
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pipeline->rb_blend_cntl_mask = ~0u;
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pipeline->rb_mrt_control_mask = ~0u;
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if (!dynamic_info)
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return;
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@ -3114,6 +3142,13 @@ tu_pipeline_builder_parse_dynamic(struct tu_pipeline_builder *builder,
|
|||
pipeline->vpc_unknown_9107_mask &= ~A6XX_VPC_UNKNOWN_9107_RASTER_DISCARD;
|
||||
pipeline->dynamic_state_mask |= BIT(TU_DYNAMIC_STATE_RASTERIZER_DISCARD);
|
||||
break;
|
||||
case VK_DYNAMIC_STATE_LOGIC_OP_EXT:
|
||||
pipeline->sp_blend_cntl_mask &= ~A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK;
|
||||
pipeline->rb_blend_cntl_mask &= ~A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK;
|
||||
pipeline->rb_mrt_control_mask &= ~A6XX_RB_MRT_CONTROL_ROP_CODE__MASK;
|
||||
pipeline->dynamic_state_mask |= BIT(TU_DYNAMIC_STATE_BLEND);
|
||||
pipeline->dynamic_state_mask |= BIT(TU_DYNAMIC_STATE_LOGIC_OP);
|
||||
break;
|
||||
default:
|
||||
assert(!"unsupported dynamic state");
|
||||
break;
|
||||
|
|
@ -3543,19 +3578,21 @@ tu_pipeline_builder_parse_multisample_and_color_blend(
|
|||
: &dummy_blend_info;
|
||||
|
||||
struct tu_cs cs;
|
||||
pipeline->blend_state =
|
||||
tu_cs_draw_state(&pipeline->cs, &cs, blend_info->attachmentCount * 3 + 4);
|
||||
|
||||
uint32_t blend_enable_mask;
|
||||
tu6_emit_rb_mrt_controls(&cs, blend_info,
|
||||
tu6_emit_rb_mrt_controls(pipeline, blend_info,
|
||||
builder->color_attachment_formats,
|
||||
&blend_enable_mask,
|
||||
&pipeline->rop_reads_dst,
|
||||
&pipeline->color_bandwidth_per_sample);
|
||||
|
||||
tu6_emit_blend_control(&cs, blend_enable_mask,
|
||||
uint32_t blend_enable_mask =
|
||||
pipeline->rop_reads_dst ? pipeline->color_write_enable : pipeline->blend_enable;
|
||||
tu6_emit_blend_control(pipeline, blend_enable_mask,
|
||||
builder->use_dual_src_blend, msaa_info);
|
||||
|
||||
assert(cs.cur == cs.end); /* validate draw state size */
|
||||
if (tu_pipeline_static_state(pipeline, &cs, TU_DYNAMIC_STATE_BLEND,
|
||||
blend_info->attachmentCount * 3 + 4)) {
|
||||
tu6_emit_blend(&cs, pipeline);
|
||||
assert(cs.cur == cs.end); /* validate draw state size */
|
||||
}
|
||||
|
||||
/* Disable LRZ writes when blend or logic op that reads the destination is
|
||||
* enabled, since the resulting pixel value from the blend-draw depends on
|
||||
|
|
|
|||
|
|
@ -695,10 +695,12 @@ enum tu_dynamic_state
|
|||
TU_DYNAMIC_STATE_RB_STENCIL_CNTL,
|
||||
TU_DYNAMIC_STATE_VB_STRIDE,
|
||||
TU_DYNAMIC_STATE_RASTERIZER_DISCARD,
|
||||
TU_DYNAMIC_STATE_BLEND,
|
||||
TU_DYNAMIC_STATE_COUNT,
|
||||
/* no associated draw state: */
|
||||
TU_DYNAMIC_STATE_PRIMITIVE_TOPOLOGY = TU_DYNAMIC_STATE_COUNT,
|
||||
TU_DYNAMIC_STATE_PRIMITIVE_RESTART_ENABLE,
|
||||
TU_DYNAMIC_STATE_LOGIC_OP,
|
||||
/* re-use the line width enum as it uses GRAS_SU_CNTL: */
|
||||
TU_DYNAMIC_STATE_GRAS_SU_CNTL = VK_DYNAMIC_STATE_LINE_WIDTH,
|
||||
};
|
||||
|
|
@ -712,7 +714,6 @@ enum tu_draw_state_group_id
|
|||
TU_DRAW_STATE_VI,
|
||||
TU_DRAW_STATE_VI_BINNING,
|
||||
TU_DRAW_STATE_RAST,
|
||||
TU_DRAW_STATE_BLEND,
|
||||
TU_DRAW_STATE_SHADER_GEOM_CONST,
|
||||
TU_DRAW_STATE_FS_CONST,
|
||||
TU_DRAW_STATE_DESC_SETS,
|
||||
|
|
@ -925,8 +926,9 @@ enum tu_cmd_dirty_bits
|
|||
TU_CMD_DIRTY_VS_PARAMS = BIT(9),
|
||||
TU_CMD_DIRTY_RASTERIZER_DISCARD = BIT(10),
|
||||
TU_CMD_DIRTY_VIEWPORTS = BIT(11),
|
||||
TU_CMD_DIRTY_BLEND = BIT(12),
|
||||
/* all draw states were disabled and need to be re-enabled: */
|
||||
TU_CMD_DIRTY_DRAW_STATE = BIT(12)
|
||||
TU_CMD_DIRTY_DRAW_STATE = BIT(13)
|
||||
};
|
||||
|
||||
/* There are only three cache domains we have to care about: the CCU, or
|
||||
|
|
@ -1163,6 +1165,12 @@ struct tu_cmd_state
|
|||
|
||||
uint32_t gras_su_cntl, rb_depth_cntl, rb_stencil_cntl;
|
||||
uint32_t pc_raster_cntl, vpc_unknown_9107;
|
||||
uint32_t rb_mrt_control[MAX_RTS], rb_mrt_blend_control[MAX_RTS];
|
||||
uint32_t rb_mrt_control_rop;
|
||||
uint32_t rb_blend_cntl, sp_blend_cntl;
|
||||
uint32_t pipeline_color_write_enable, pipeline_blend_enable;
|
||||
bool logic_op_enabled;
|
||||
bool rop_reads_dst;
|
||||
enum pc_di_primtype primtype;
|
||||
bool primitive_restart_enable;
|
||||
|
||||
|
|
@ -1447,12 +1455,21 @@ struct tu_pipeline
|
|||
uint32_t vpc_unknown_9107, vpc_unknown_9107_mask;
|
||||
uint32_t stencil_wrmask;
|
||||
|
||||
unsigned num_rts;
|
||||
uint32_t rb_mrt_control[MAX_RTS], rb_mrt_control_mask;
|
||||
uint32_t rb_mrt_blend_control[MAX_RTS];
|
||||
uint32_t sp_blend_cntl, sp_blend_cntl_mask;
|
||||
uint32_t rb_blend_cntl, rb_blend_cntl_mask;
|
||||
uint32_t color_write_enable, blend_enable;
|
||||
bool logic_op_enabled, rop_reads_dst;
|
||||
bool rasterizer_discard;
|
||||
|
||||
bool rb_depth_cntl_disable;
|
||||
|
||||
enum a5xx_line_mode line_mode;
|
||||
|
||||
/* draw states for the pipeline */
|
||||
struct tu_draw_state load_state, rast_state, blend_state;
|
||||
struct tu_draw_state load_state, rast_state;
|
||||
struct tu_draw_state prim_order_state_sysmem, prim_order_state_gmem;
|
||||
|
||||
/* for vertex buffers state */
|
||||
|
|
@ -1539,6 +1556,8 @@ void tu6_emit_window_scissor(struct tu_cs *cs, uint32_t x1, uint32_t y1, uint32_
|
|||
|
||||
void tu6_emit_window_offset(struct tu_cs *cs, uint32_t x1, uint32_t y1);
|
||||
|
||||
uint32_t tu6_rb_mrt_control_rop(VkLogicOp op, bool *rop_reads_dst);
|
||||
|
||||
void tu_disable_draw_states(struct tu_cmd_buffer *cmd, struct tu_cs *cs);
|
||||
|
||||
void tu6_apply_depth_bounds_workaround(struct tu_device *device,
|
||||
|
|
|
|||
Loading…
Reference in New Issue