KonstantinSeurer
/
mesa
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

freedreno: Document rest of GRAS_LRZ_CNTL, clarify UNK_25 event 

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16251>
This commit is contained in:
Danylo Piliaiev 2022-05-13 17:10:36 +03:00 committed by Marge Bot
parent edc7f40a83
commit 5592c366cf
3 changed files with 30 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
src/freedreno/registers/adreno/a6xx.xml
View File

@ -1773,11 +1773,13 @@ to upconvert to 32b float internally?
<reg32 offset="0x80f1" name="GRAS_SC_WINDOW_SCISSOR_BR" type="a6xx_reg_xy"/>
<!-- 0x80f2-0x80ff invalid -->
<enum name="a6xx_lrz_dir_status">
<value value="0x1" name="LRZ_DIR_LE"/>
<value value="0x2" name="LRZ_DIR_GE"/>
<value value="0x3" name="LRZ_DIR_INVALID"/>
</enum>
<reg32 offset="0x8100" name="GRAS_LRZ_CNTL">
<!--
These bits seems to mostly fit.. but wouldn't hurt to have a 2nd
look when we get around to enabling lrz
-->
<bitfield name="ENABLE" pos="0" type="boolean"/>
<doc>LRZ write also disabled for blend/etc.</doc>
<bitfield name="LRZ_WRITE" pos="1" type="boolean"/>
@ -1787,7 +1789,17 @@ to upconvert to 32b float internally?
<!-- set when depth-test + depth-write enabled -->
<bitfield name="Z_TEST_ENABLE" pos="4" type="boolean"/>
<bitfield name="Z_BOUNDS_ENABLE" pos="5" type="boolean"/>
<bitfield name="UNK6" low="6" high="9"/>
<bitfield name="DIR" low="6" high="7" type="a6xx_lrz_dir_status"/>
<doc>
If DISABLE_ON_WRONG_DIR enabled - write new LRZ direction into
buffer, in case of mismatched direction writes 0 (disables LRZ).
</doc>
<bitfield name="DIR_WRITE" pos="8" type="boolean"/>
<doc>
Disable LRZ based on previous direction and the current one.
If DIR_WRITE is not enabled - there is no write to direction buffer.
</doc>
<bitfield name="DISABLE_ON_WRONG_DIR" pos="9" type="boolean"/>
</reg32>
<enum name="a6xx_fragcoord_sample_mode">

13
src/freedreno/registers/adreno/adreno_pm4.xml
View File

@ -43,7 +43,18 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
<value name="PC_CCU_FLUSH_DEPTH_TS" value="28" varset="chip" variants="A5XX-"/>
<value name="PC_CCU_FLUSH_COLOR_TS" value="29" varset="chip" variants="A5XX-"/>
<value name="BLIT" value="30" varset="chip" variants="A5XX-"/>
<value name="UNK_25" value="37" varset="chip" variants="A5XX"/>
<doc>
Clears based on GRAS_LRZ_CNTL configuration, could clear
fast-clear buffer or LRZ direction.
LRZ direction is stored at lrz_fc_offset + 0x200, has 1 byte which
could be expressed by enum:
CUR_DIR_DISABLED = 0x0
CUR_DIR_GE = 0x1
CUR_DIR_LE = 0x2
CUR_DIR_UNSET = 0x3
Clear of direction means setting the direction to CUR_DIR_UNSET.
</doc>
<value name="LRZ_CLEAR" value="37" varset="chip" variants="A5XX-"/>
<value name="LRZ_FLUSH" value="38" varset="chip" variants="A5XX-"/>
<value name="BLIT_OP_FILL_2D" value="39" varset="chip" variants="A5XX-"/>
<value name="BLIT_OP_COPY_2D" value="40" varset="chip" variants="A5XX-"/>

2
src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
View File

@ -200,7 +200,7 @@ emit_zs(struct fd_ringbuffer *ring, struct pipe_surface *zsbuf,
* plus this CP_EVENT_WRITE at the end in it's own IB..
*/
OUT_PKT7(ring, CP_EVENT_WRITE, 1);
OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(UNK_25));
OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(LRZ_CLEAR));
if (rsc->stencil) {
stride = fd_resource_pitch(rsc->stencil, zsbuf->u.tex.level);