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freedreno/ir3: Enable core NIR's 16-bit ALU optimizations. 

In addition to hopefully generating shorter code, this optimizes out a
comparison of a mediump-cast value in
dEQP-GLES2.functional.shaders.algorithm.rgb_to_hsl_fragment passed
through ANGLE, and allows the test to pass.  We believe it to be a
test bug, but emitting better code like apparently everyone else does
is also a fine result.

No change on GLES gfxbench shaders.

Fixes: #6585
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17546>
This commit is contained in:
Emma Anholt 2022-07-14 11:33:19 -07:00 committed by Marge Bot
parent fc26fbde3d
commit 3d62a41dcc
1 changed files with 6 additions and 0 deletions
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6
src/freedreno/ir3/ir3_compiler.c
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@ -292,6 +292,12 @@ ir3_compiler_create(struct fd_device *dev, const struct fd_dev_id *dev_id,
compiler->nir_options.force_indirect_unrolling = nir_var_all;
}
/* 16-bit ALU op generation is mostly controlled by frontend compiler options, but
* this core NIR option enables some optimizations of 16-bit operations.
*/
if (compiler->gen >= 5 && !(ir3_shader_debug & IR3_DBG_NOFP16))
compiler->nir_options.support_16bit_alu = true;
if (!options->disable_cache)
ir3_disk_cache_init(compiler);