2017-09-01 10:41:18 +01:00
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/*
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* Copyright © 2016 Red Hat.
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* Copyright © 2016 Bas Nieuwenhuizen
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*
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* based in part on anv driver which is:
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* Copyright © 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "util/mesa-sha1.h"
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#include "util/u_atomic.h"
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#include "radv_debug.h"
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#include "radv_private.h"
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#include "radv_shader.h"
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2018-06-27 02:34:25 +01:00
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#include "radv_shader_helper.h"
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2017-09-01 10:41:18 +01:00
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#include "nir/nir.h"
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#include "nir/nir_builder.h"
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#include "spirv/nir_spirv.h"
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#include <llvm-c/Core.h>
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#include <llvm-c/TargetMachine.h>
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2018-06-08 10:38:01 +01:00
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#include <llvm-c/Support.h>
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2017-09-01 10:41:18 +01:00
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#include "sid.h"
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#include "ac_binary.h"
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#include "ac_llvm_util.h"
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#include "ac_nir_to_llvm.h"
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2019-07-01 00:29:24 +01:00
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#include "ac_rtld.h"
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2017-09-01 10:41:18 +01:00
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#include "vk_format.h"
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#include "util/debug.h"
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#include "ac_exp_param.h"
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2019-09-17 13:35:22 +01:00
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#include "aco_interface.h"
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2017-10-27 14:25:05 +01:00
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#include "util/string_buffer.h"
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2019-09-17 13:35:22 +01:00
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static const struct nir_shader_compiler_options nir_options_llvm = {
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2017-09-01 10:41:18 +01:00
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.vertex_id_zero_based = true,
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.lower_scmp = true,
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2018-12-06 14:01:15 +00:00
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.lower_flrp16 = true,
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2017-09-01 10:41:18 +01:00
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.lower_flrp32 = true,
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2018-01-12 00:12:09 +00:00
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.lower_flrp64 = true,
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2018-01-21 16:13:26 +00:00
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.lower_device_index_to_zero = true,
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2017-09-01 10:41:18 +01:00
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.lower_fsat = true,
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.lower_fdiv = true,
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2019-01-25 15:08:38 +00:00
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.lower_bitfield_insert_to_bitfield_select = true,
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2019-01-25 15:24:55 +00:00
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.lower_bitfield_extract = true,
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2017-09-01 10:41:18 +01:00
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.lower_sub = true,
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.lower_pack_snorm_2x16 = true,
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.lower_pack_snorm_4x8 = true,
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.lower_pack_unorm_2x16 = true,
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.lower_pack_unorm_4x8 = true,
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.lower_unpack_snorm_2x16 = true,
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.lower_unpack_snorm_4x8 = true,
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.lower_unpack_unorm_2x16 = true,
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.lower_unpack_unorm_4x8 = true,
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.lower_extract_byte = true,
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.lower_extract_word = true,
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2017-10-03 21:33:02 +01:00
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.lower_ffma = true,
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2018-02-02 18:04:57 +00:00
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.lower_fpow = true,
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2019-03-06 21:35:31 +00:00
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.lower_mul_2x32_64 = true,
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2019-06-04 01:11:57 +01:00
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.lower_rotate = true,
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2019-05-10 09:44:20 +01:00
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.max_unroll_iterations = 32,
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.use_interpolated_input_intrinsics = true,
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2017-09-01 10:41:18 +01:00
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};
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2019-09-17 13:35:22 +01:00
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static const struct nir_shader_compiler_options nir_options_aco = {
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.vertex_id_zero_based = true,
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.lower_scmp = true,
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.lower_flrp16 = true,
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.lower_flrp32 = true,
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.lower_flrp64 = true,
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.lower_device_index_to_zero = true,
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.lower_fdiv = true,
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.lower_bitfield_insert_to_bitfield_select = true,
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.lower_bitfield_extract = true,
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.lower_pack_snorm_2x16 = true,
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.lower_pack_snorm_4x8 = true,
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.lower_pack_unorm_2x16 = true,
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.lower_pack_unorm_4x8 = true,
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.lower_unpack_snorm_2x16 = true,
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.lower_unpack_snorm_4x8 = true,
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.lower_unpack_unorm_2x16 = true,
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.lower_unpack_unorm_4x8 = true,
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.lower_unpack_half_2x16 = true,
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.lower_extract_byte = true,
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.lower_extract_word = true,
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.lower_ffma = true,
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.lower_fpow = true,
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.lower_mul_2x32_64 = true,
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.lower_rotate = true,
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.max_unroll_iterations = 32,
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.use_interpolated_input_intrinsics = true,
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};
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2019-07-29 16:51:01 +01:00
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bool
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radv_can_dump_shader(struct radv_device *device,
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struct radv_shader_module *module,
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bool is_gs_copy_shader)
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{
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if (!(device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS))
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return false;
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2019-09-18 13:39:10 +01:00
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if (module)
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return !module->nir ||
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(device->instance->debug_flags & RADV_DEBUG_DUMP_META_SHADERS);
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2019-07-29 16:51:01 +01:00
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2019-09-18 13:39:10 +01:00
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return is_gs_copy_shader;
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2019-07-29 16:51:01 +01:00
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}
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bool
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radv_can_dump_shader_stats(struct radv_device *device,
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struct radv_shader_module *module)
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{
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/* Only dump non-meta shader stats. */
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return device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS &&
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module && !module->nir;
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}
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unsigned shader_io_get_unique_index(gl_varying_slot slot)
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{
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/* handle patch indices separate */
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if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
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return 0;
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if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
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return 1;
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if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
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return 2 + (slot - VARYING_SLOT_PATCH0);
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if (slot == VARYING_SLOT_POS)
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return 0;
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if (slot == VARYING_SLOT_PSIZ)
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return 1;
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if (slot == VARYING_SLOT_CLIP_DIST0)
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return 2;
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if (slot == VARYING_SLOT_CLIP_DIST1)
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return 3;
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/* 3 is reserved for clip dist as well */
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if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
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return 4 + (slot - VARYING_SLOT_VAR0);
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unreachable("illegal slot in get unique index\n");
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}
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2017-09-01 10:41:18 +01:00
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VkResult radv_CreateShaderModule(
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VkDevice _device,
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const VkShaderModuleCreateInfo* pCreateInfo,
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const VkAllocationCallbacks* pAllocator,
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VkShaderModule* pShaderModule)
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{
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RADV_FROM_HANDLE(radv_device, device, _device);
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struct radv_shader_module *module;
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assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
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assert(pCreateInfo->flags == 0);
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module = vk_alloc2(&device->alloc, pAllocator,
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sizeof(*module) + pCreateInfo->codeSize, 8,
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VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
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if (module == NULL)
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2018-05-31 00:06:41 +01:00
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return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
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2017-09-01 10:41:18 +01:00
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module->nir = NULL;
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module->size = pCreateInfo->codeSize;
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memcpy(module->data, pCreateInfo->pCode, module->size);
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_mesa_sha1_compute(module->data, module->size, module->sha1);
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*pShaderModule = radv_shader_module_to_handle(module);
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return VK_SUCCESS;
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}
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void radv_DestroyShaderModule(
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VkDevice _device,
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VkShaderModule _module,
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const VkAllocationCallbacks* pAllocator)
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{
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RADV_FROM_HANDLE(radv_device, device, _device);
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RADV_FROM_HANDLE(radv_shader_module, module, _module);
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if (!module)
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return;
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vk_free2(&device->alloc, pAllocator, module);
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}
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2017-02-08 23:12:10 +00:00
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void
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2018-10-17 23:42:17 +01:00
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radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
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bool allow_copies)
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2017-09-01 10:41:18 +01:00
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{
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bool progress;
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2018-08-19 00:42:04 +01:00
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unsigned lower_flrp =
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(shader->options->lower_flrp16 ? 16 : 0) |
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(shader->options->lower_flrp32 ? 32 : 0) |
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(shader->options->lower_flrp64 ? 64 : 0);
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2017-09-01 10:41:18 +01:00
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do {
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progress = false;
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2019-01-15 23:05:04 +00:00
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NIR_PASS(progress, shader, nir_split_array_vars, nir_var_function_temp);
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NIR_PASS(progress, shader, nir_shrink_vec_array_vars, nir_var_function_temp);
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2018-10-18 00:19:16 +01:00
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2017-09-01 10:41:18 +01:00
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NIR_PASS_V(shader, nir_lower_vars_to_ssa);
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2018-04-27 08:28:48 +01:00
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NIR_PASS_V(shader, nir_lower_pack);
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2018-10-17 22:55:46 +01:00
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2018-10-17 23:42:17 +01:00
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if (allow_copies) {
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/* Only run this pass in the first call to
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* radv_optimize_nir. Later calls assume that we've
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* lowered away any copy_deref instructions and we
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* don't want to introduce any more.
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*/
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NIR_PASS(progress, shader, nir_opt_find_array_copies);
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}
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2018-10-17 22:55:46 +01:00
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NIR_PASS(progress, shader, nir_opt_copy_prop_vars);
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NIR_PASS(progress, shader, nir_opt_dead_write_vars);
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2019-06-26 13:03:31 +01:00
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NIR_PASS(progress, shader, nir_remove_dead_variables,
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nir_var_function_temp);
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2018-10-17 22:55:46 +01:00
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2019-08-30 05:14:54 +01:00
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NIR_PASS_V(shader, nir_lower_alu_to_scalar, NULL, NULL);
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2017-09-01 10:41:18 +01:00
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NIR_PASS_V(shader, nir_lower_phis_to_scalar);
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NIR_PASS(progress, shader, nir_copy_prop);
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NIR_PASS(progress, shader, nir_opt_remove_phis);
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NIR_PASS(progress, shader, nir_opt_dce);
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if (nir_opt_trivial_continues(shader)) {
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progress = true;
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NIR_PASS(progress, shader, nir_copy_prop);
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2017-09-13 03:49:31 +01:00
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NIR_PASS(progress, shader, nir_opt_remove_phis);
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2017-09-01 10:41:18 +01:00
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NIR_PASS(progress, shader, nir_opt_dce);
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}
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2019-04-08 11:13:49 +01:00
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NIR_PASS(progress, shader, nir_opt_if, true);
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2017-09-01 10:41:18 +01:00
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NIR_PASS(progress, shader, nir_opt_dead_cf);
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NIR_PASS(progress, shader, nir_opt_cse);
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2018-06-19 00:11:55 +01:00
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NIR_PASS(progress, shader, nir_opt_peephole_select, 8, true, true);
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2017-09-01 10:41:18 +01:00
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NIR_PASS(progress, shader, nir_opt_constant_folding);
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2019-05-02 04:38:52 +01:00
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NIR_PASS(progress, shader, nir_opt_algebraic);
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2018-08-19 00:42:04 +01:00
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if (lower_flrp != 0) {
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2019-05-08 15:32:43 +01:00
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bool lower_flrp_progress = false;
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2018-08-19 00:42:04 +01:00
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NIR_PASS(lower_flrp_progress,
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shader,
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nir_lower_flrp,
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lower_flrp,
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false /* always_precise */,
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shader->options->lower_ffma);
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if (lower_flrp_progress) {
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NIR_PASS(progress, shader,
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nir_opt_constant_folding);
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progress = true;
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}
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/* Nothing should rematerialize any flrps, so we only
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* need to do this lowering once.
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*/
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lower_flrp = 0;
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}
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2017-09-01 10:41:18 +01:00
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NIR_PASS(progress, shader, nir_opt_undef);
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if (shader->options->max_unroll_iterations) {
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NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
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}
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2018-05-08 05:57:55 +01:00
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} while (progress && !optimize_conservatively);
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2018-01-29 16:19:18 +00:00
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2019-07-20 18:21:14 +01:00
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NIR_PASS(progress, shader, nir_opt_conditional_discard);
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2018-01-29 16:19:18 +00:00
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NIR_PASS(progress, shader, nir_opt_shrink_load);
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2019-07-24 19:23:21 +01:00
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NIR_PASS(progress, shader, nir_opt_move, nir_move_load_ubo);
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2017-09-01 10:41:18 +01:00
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}
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nir_shader *
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radv_shader_compile_to_nir(struct radv_device *device,
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struct radv_shader_module *module,
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const char *entrypoint_name,
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gl_shader_stage stage,
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2018-05-08 05:57:55 +01:00
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const VkSpecializationInfo *spec_info,
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2019-03-30 13:28:06 +00:00
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const VkPipelineCreateFlags flags,
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2019-09-17 13:35:22 +01:00
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const struct radv_pipeline_layout *layout,
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bool use_aco)
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2017-09-01 10:41:18 +01:00
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{
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nir_shader *nir;
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2019-09-17 13:35:22 +01:00
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|
|
const nir_shader_compiler_options *nir_options = use_aco ? &nir_options_aco :
|
|
|
|
&nir_options_llvm;
|
2017-09-01 10:41:18 +01:00
|
|
|
if (module->nir) {
|
|
|
|
/* Some things such as our meta clear/blit code will give us a NIR
|
|
|
|
* shader directly. In that case, we just ignore the SPIR-V entirely
|
|
|
|
* and just use the NIR shader */
|
|
|
|
nir = module->nir;
|
2019-09-17 13:35:22 +01:00
|
|
|
nir->options = nir_options;
|
2018-10-18 21:18:30 +01:00
|
|
|
nir_validate_shader(nir, "in internal shader");
|
2017-09-01 10:41:18 +01:00
|
|
|
|
|
|
|
assert(exec_list_length(&nir->functions) == 1);
|
|
|
|
} else {
|
|
|
|
uint32_t *spirv = (uint32_t *) module->data;
|
|
|
|
assert(module->size % 4 == 0);
|
|
|
|
|
2017-10-11 01:59:20 +01:00
|
|
|
if (device->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV)
|
2017-09-22 15:56:40 +01:00
|
|
|
radv_print_spirv(spirv, module->size, stderr);
|
2017-09-01 10:41:18 +01:00
|
|
|
|
|
|
|
uint32_t num_spec_entries = 0;
|
|
|
|
struct nir_spirv_specialization *spec_entries = NULL;
|
|
|
|
if (spec_info && spec_info->mapEntryCount > 0) {
|
|
|
|
num_spec_entries = spec_info->mapEntryCount;
|
|
|
|
spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
|
|
|
|
for (uint32_t i = 0; i < num_spec_entries; i++) {
|
|
|
|
VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
|
|
|
|
const void *data = spec_info->pData + entry.offset;
|
|
|
|
assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
|
|
|
|
|
|
|
|
spec_entries[i].id = spec_info->pMapEntries[i].constantID;
|
|
|
|
if (spec_info->dataSize == 8)
|
|
|
|
spec_entries[i].data64 = *(const uint64_t *)data;
|
|
|
|
else
|
|
|
|
spec_entries[i].data32 = *(const uint32_t *)data;
|
|
|
|
}
|
|
|
|
}
|
2017-10-19 01:28:19 +01:00
|
|
|
const struct spirv_to_nir_options spirv_options = {
|
2018-12-15 00:36:01 +00:00
|
|
|
.lower_ubo_ssbo_access_to_offsets = true,
|
2017-10-19 01:28:19 +01:00
|
|
|
.caps = {
|
2018-05-09 19:41:23 +01:00
|
|
|
.amd_gcn_shader = true,
|
2019-08-21 07:38:24 +01:00
|
|
|
.amd_shader_ballot = device->physical_device->use_shader_ballot,
|
2018-05-09 19:41:23 +01:00
|
|
|
.amd_trinary_minmax = true,
|
2019-09-17 16:09:52 +01:00
|
|
|
.demote_to_helper_invocation = device->physical_device->use_aco,
|
2019-04-19 11:40:37 +01:00
|
|
|
.derivative_group = true,
|
2019-01-07 16:28:23 +00:00
|
|
|
.descriptor_array_dynamic_indexing = true,
|
2019-04-29 16:05:13 +01:00
|
|
|
.descriptor_array_non_uniform_indexing = true,
|
|
|
|
.descriptor_indexing = true,
|
2018-01-21 16:13:26 +00:00
|
|
|
.device_group = true,
|
2017-10-19 01:28:19 +01:00
|
|
|
.draw_parameters = true,
|
2019-09-17 13:35:22 +01:00
|
|
|
.float16 = !device->physical_device->use_aco,
|
2017-10-19 01:28:19 +01:00
|
|
|
.float64 = true,
|
2019-01-07 16:28:23 +00:00
|
|
|
.geometry_streams = true,
|
2017-10-19 01:28:19 +01:00
|
|
|
.image_read_without_format = true,
|
|
|
|
.image_write_without_format = true,
|
2019-09-17 13:35:22 +01:00
|
|
|
.int8 = !device->physical_device->use_aco,
|
|
|
|
.int16 = !device->physical_device->use_aco,
|
2019-01-07 16:28:23 +00:00
|
|
|
.int64 = true,
|
2019-04-16 09:38:24 +01:00
|
|
|
.int64_atomics = true,
|
2017-10-19 01:28:19 +01:00
|
|
|
.multiview = true,
|
2019-01-24 01:06:27 +00:00
|
|
|
.physical_storage_buffer_address = true,
|
2019-07-16 16:11:50 +01:00
|
|
|
.post_depth_coverage = true,
|
2019-01-07 16:28:23 +00:00
|
|
|
.runtime_descriptor_array = true,
|
|
|
|
.shader_viewport_index_layer = true,
|
|
|
|
.stencil_export = true,
|
2019-09-17 13:35:22 +01:00
|
|
|
.storage_8bit = !device->physical_device->use_aco,
|
|
|
|
.storage_16bit = !device->physical_device->use_aco,
|
2019-01-07 16:28:23 +00:00
|
|
|
.storage_image_ms = true,
|
2018-09-18 14:27:52 +01:00
|
|
|
.subgroup_arithmetic = true,
|
2018-03-06 14:05:13 +00:00
|
|
|
.subgroup_ballot = true,
|
2018-01-21 14:06:10 +00:00
|
|
|
.subgroup_basic = true,
|
2018-03-06 14:05:13 +00:00
|
|
|
.subgroup_quad = true,
|
|
|
|
.subgroup_shuffle = true,
|
|
|
|
.subgroup_vote = true,
|
2019-01-07 16:28:23 +00:00
|
|
|
.tessellation = true,
|
2018-10-05 17:04:56 +01:00
|
|
|
.transform_feedback = true,
|
2019-01-07 16:28:23 +00:00
|
|
|
.variable_pointers = true,
|
2018-02-23 12:55:01 +00:00
|
|
|
},
|
2019-05-01 22:15:32 +01:00
|
|
|
.ubo_addr_format = nir_address_format_32bit_index_offset,
|
|
|
|
.ssbo_addr_format = nir_address_format_32bit_index_offset,
|
|
|
|
.phys_ssbo_addr_format = nir_address_format_64bit_global,
|
|
|
|
.push_const_addr_format = nir_address_format_logical,
|
|
|
|
.shared_addr_format = nir_address_format_32bit_offset,
|
2019-05-13 14:39:54 +01:00
|
|
|
.frag_coord_is_sysval = true,
|
2017-09-01 10:41:18 +01:00
|
|
|
};
|
2019-05-19 08:22:17 +01:00
|
|
|
nir = spirv_to_nir(spirv, module->size / 4,
|
|
|
|
spec_entries, num_spec_entries,
|
|
|
|
stage, entrypoint_name,
|
2019-09-17 13:35:22 +01:00
|
|
|
&spirv_options, nir_options);
|
2017-09-15 03:52:38 +01:00
|
|
|
assert(nir->info.stage == stage);
|
2018-10-18 21:18:30 +01:00
|
|
|
nir_validate_shader(nir, "after spirv_to_nir");
|
2017-09-01 10:41:18 +01:00
|
|
|
|
|
|
|
free(spec_entries);
|
|
|
|
|
|
|
|
/* We have to lower away local constant initializers right before we
|
|
|
|
* inline functions. That way they get properly initialized at the top
|
|
|
|
* of the function and not at the top of its caller.
|
|
|
|
*/
|
2019-01-15 23:05:04 +00:00
|
|
|
NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_function_temp);
|
2017-09-01 10:41:18 +01:00
|
|
|
NIR_PASS_V(nir, nir_lower_returns);
|
|
|
|
NIR_PASS_V(nir, nir_inline_functions);
|
2018-12-13 17:08:13 +00:00
|
|
|
NIR_PASS_V(nir, nir_opt_deref);
|
2017-09-01 10:41:18 +01:00
|
|
|
|
|
|
|
/* Pick off the single entrypoint that we want */
|
|
|
|
foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
|
2019-05-19 08:11:37 +01:00
|
|
|
if (func->is_entrypoint)
|
|
|
|
func->name = ralloc_strdup(func, "main");
|
|
|
|
else
|
2017-09-01 10:41:18 +01:00
|
|
|
exec_node_remove(&func->node);
|
|
|
|
}
|
|
|
|
assert(exec_list_length(&nir->functions) == 1);
|
|
|
|
|
2018-03-19 04:27:49 +00:00
|
|
|
/* Make sure we lower constant initializers on output variables so that
|
|
|
|
* nir_remove_dead_variables below sees the corresponding stores
|
|
|
|
*/
|
|
|
|
NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_shader_out);
|
|
|
|
|
2017-09-01 10:41:18 +01:00
|
|
|
/* Now that we've deleted all but the main function, we can go ahead and
|
|
|
|
* lower the rest of the constant initializers.
|
|
|
|
*/
|
|
|
|
NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
|
2018-03-22 00:30:22 +00:00
|
|
|
|
|
|
|
/* Split member structs. We do this before lower_io_to_temporaries so that
|
|
|
|
* it doesn't lower system values to temporaries by accident.
|
|
|
|
*/
|
|
|
|
NIR_PASS_V(nir, nir_split_var_copies);
|
|
|
|
NIR_PASS_V(nir, nir_split_per_member_structs);
|
|
|
|
|
2019-09-17 13:35:22 +01:00
|
|
|
if (nir->info.stage == MESA_SHADER_FRAGMENT && use_aco)
|
|
|
|
NIR_PASS_V(nir, nir_lower_io_to_vector, nir_var_shader_out);
|
2019-04-05 10:01:39 +01:00
|
|
|
if (nir->info.stage == MESA_SHADER_FRAGMENT)
|
2019-05-13 14:39:54 +01:00
|
|
|
NIR_PASS_V(nir, nir_lower_input_attachments, true);
|
2019-04-05 10:01:39 +01:00
|
|
|
|
2018-08-22 11:34:13 +01:00
|
|
|
NIR_PASS_V(nir, nir_remove_dead_variables,
|
2019-09-17 17:24:06 +01:00
|
|
|
nir_var_shader_in | nir_var_shader_out | nir_var_system_value | nir_var_mem_shared);
|
2018-08-22 11:34:13 +01:00
|
|
|
|
2019-09-05 12:57:11 +01:00
|
|
|
NIR_PASS_V(nir, nir_propagate_invariant);
|
|
|
|
|
2017-09-01 10:41:18 +01:00
|
|
|
NIR_PASS_V(nir, nir_lower_system_values);
|
|
|
|
NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
|
2019-03-30 13:28:06 +00:00
|
|
|
NIR_PASS_V(nir, radv_nir_lower_ycbcr_textures, layout);
|
2017-09-01 10:41:18 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Vulkan uses the separate-shader linking model */
|
|
|
|
nir->info.separate_shader = true;
|
|
|
|
|
2019-05-19 08:11:37 +01:00
|
|
|
nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
|
2017-09-01 10:41:18 +01:00
|
|
|
|
|
|
|
static const nir_lower_tex_options tex_options = {
|
|
|
|
.lower_txp = ~0,
|
2019-03-19 18:55:21 +00:00
|
|
|
.lower_tg4_offsets = true,
|
2017-09-01 10:41:18 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
nir_lower_tex(nir, &tex_options);
|
|
|
|
|
|
|
|
nir_lower_vars_to_ssa(nir);
|
2018-05-23 13:31:55 +01:00
|
|
|
|
2018-05-23 13:31:56 +01:00
|
|
|
if (nir->info.stage == MESA_SHADER_VERTEX ||
|
2019-05-10 09:44:20 +01:00
|
|
|
nir->info.stage == MESA_SHADER_GEOMETRY ||
|
|
|
|
nir->info.stage == MESA_SHADER_FRAGMENT) {
|
2018-05-23 13:31:56 +01:00
|
|
|
NIR_PASS_V(nir, nir_lower_io_to_temporaries,
|
|
|
|
nir_shader_get_entrypoint(nir), true, true);
|
2019-05-10 09:44:20 +01:00
|
|
|
} else if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
|
2018-05-23 13:31:56 +01:00
|
|
|
NIR_PASS_V(nir, nir_lower_io_to_temporaries,
|
|
|
|
nir_shader_get_entrypoint(nir), true, false);
|
|
|
|
}
|
|
|
|
|
2018-05-23 13:31:55 +01:00
|
|
|
nir_split_var_copies(nir);
|
|
|
|
|
2017-09-01 10:41:18 +01:00
|
|
|
nir_lower_global_vars_to_local(nir);
|
2019-01-15 23:05:04 +00:00
|
|
|
nir_remove_dead_variables(nir, nir_var_function_temp);
|
2018-01-21 14:06:10 +00:00
|
|
|
nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) {
|
|
|
|
.subgroup_size = 64,
|
|
|
|
.ballot_bit_size = 64,
|
|
|
|
.lower_to_scalar = 1,
|
|
|
|
.lower_subgroup_masks = 1,
|
|
|
|
.lower_shuffle = 1,
|
2018-03-06 14:05:13 +00:00
|
|
|
.lower_shuffle_to_32bit = 1,
|
|
|
|
.lower_vote_eq_to_ballot = 1,
|
2018-01-21 14:06:10 +00:00
|
|
|
});
|
|
|
|
|
2018-09-24 09:18:48 +01:00
|
|
|
nir_lower_load_const_to_scalar(nir);
|
|
|
|
|
2018-05-08 05:57:55 +01:00
|
|
|
if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
|
2018-10-17 23:42:17 +01:00
|
|
|
radv_optimize_nir(nir, false, true);
|
|
|
|
|
|
|
|
/* We call nir_lower_var_copies() after the first radv_optimize_nir()
|
|
|
|
* to remove any copies introduced by nir_opt_find_array_copies().
|
|
|
|
*/
|
|
|
|
nir_lower_var_copies(nir);
|
2017-09-01 10:41:18 +01:00
|
|
|
|
2019-08-30 15:08:47 +01:00
|
|
|
/* Lower large variables that are always constant with load_constant
|
|
|
|
* intrinsics, which get turned into PC-relative loads from a data
|
|
|
|
* section next to the shader.
|
|
|
|
*/
|
|
|
|
NIR_PASS_V(nir, nir_opt_large_constants,
|
|
|
|
glsl_get_natural_size_align_bytes, 16);
|
|
|
|
|
2018-03-08 05:20:48 +00:00
|
|
|
/* Indirect lowering must be called after the radv_optimize_nir() loop
|
|
|
|
* has been called at least once. Otherwise indirect lowering can
|
|
|
|
* bloat the instruction count of the loop and cause it to be
|
|
|
|
* considered too large for unrolling.
|
|
|
|
*/
|
|
|
|
ac_lower_indirect_derefs(nir, device->physical_device->rad_info.chip_class);
|
2018-10-17 23:42:17 +01:00
|
|
|
radv_optimize_nir(nir, flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT, false);
|
2018-03-08 05:20:48 +00:00
|
|
|
|
2017-09-01 10:41:18 +01:00
|
|
|
return nir;
|
|
|
|
}
|
|
|
|
|
2019-05-10 09:44:20 +01:00
|
|
|
static int
|
|
|
|
type_size_vec4(const struct glsl_type *type, bool bindless)
|
|
|
|
{
|
|
|
|
return glsl_count_attribute_slots(type, false);
|
|
|
|
}
|
|
|
|
|
|
|
|
static nir_variable *
|
|
|
|
find_layer_in_var(nir_shader *nir)
|
|
|
|
{
|
|
|
|
nir_foreach_variable(var, &nir->inputs) {
|
|
|
|
if (var->data.location == VARYING_SLOT_LAYER) {
|
|
|
|
return var;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
nir_variable *var =
|
|
|
|
nir_variable_create(nir, nir_var_shader_in, glsl_int_type(), "layer id");
|
|
|
|
var->data.location = VARYING_SLOT_LAYER;
|
|
|
|
var->data.interpolation = INTERP_MODE_FLAT;
|
|
|
|
return var;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* We use layered rendering to implement multiview, which means we need to map
|
|
|
|
* view_index to gl_Layer. The attachment lowering also uses needs to know the
|
|
|
|
* layer so that it can sample from the correct layer. The code generates a
|
|
|
|
* load from the layer_id sysval, but since we don't have a way to get at this
|
|
|
|
* information from the fragment shader, we also need to lower this to the
|
|
|
|
* gl_Layer varying. This pass lowers both to a varying load from the LAYER
|
|
|
|
* slot, before lowering io, so that nir_assign_var_locations() will give the
|
|
|
|
* LAYER varying the correct driver_location.
|
|
|
|
*/
|
|
|
|
|
|
|
|
static bool
|
|
|
|
lower_view_index(nir_shader *nir)
|
|
|
|
{
|
|
|
|
bool progress = false;
|
|
|
|
nir_function_impl *entry = nir_shader_get_entrypoint(nir);
|
|
|
|
nir_builder b;
|
|
|
|
nir_builder_init(&b, entry);
|
|
|
|
|
|
|
|
nir_variable *layer = NULL;
|
|
|
|
nir_foreach_block(block, entry) {
|
|
|
|
nir_foreach_instr_safe(instr, block) {
|
|
|
|
if (instr->type != nir_instr_type_intrinsic)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
nir_intrinsic_instr *load = nir_instr_as_intrinsic(instr);
|
|
|
|
if (load->intrinsic != nir_intrinsic_load_view_index &&
|
|
|
|
load->intrinsic != nir_intrinsic_load_layer_id)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (!layer)
|
|
|
|
layer = find_layer_in_var(nir);
|
|
|
|
|
|
|
|
b.cursor = nir_before_instr(instr);
|
|
|
|
nir_ssa_def *def = nir_load_var(&b, layer);
|
|
|
|
nir_ssa_def_rewrite_uses(&load->dest.ssa,
|
|
|
|
nir_src_for_ssa(def));
|
|
|
|
|
|
|
|
nir_instr_remove(instr);
|
|
|
|
progress = true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return progress;
|
|
|
|
}
|
|
|
|
|
2019-08-29 10:16:44 +01:00
|
|
|
void
|
|
|
|
radv_lower_fs_io(nir_shader *nir)
|
2019-05-10 09:44:20 +01:00
|
|
|
{
|
|
|
|
NIR_PASS_V(nir, lower_view_index);
|
|
|
|
nir_assign_io_var_locations(&nir->inputs, &nir->num_inputs,
|
|
|
|
MESA_SHADER_FRAGMENT);
|
|
|
|
|
|
|
|
NIR_PASS_V(nir, nir_lower_io, nir_var_shader_in, type_size_vec4, 0);
|
|
|
|
|
|
|
|
/* This pass needs actual constants */
|
|
|
|
nir_opt_constant_folding(nir);
|
|
|
|
|
|
|
|
NIR_PASS_V(nir, nir_io_add_const_offset_to_base, nir_var_shader_in);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2017-09-01 10:41:18 +01:00
|
|
|
void *
|
|
|
|
radv_alloc_shader_memory(struct radv_device *device,
|
|
|
|
struct radv_shader_variant *shader)
|
|
|
|
{
|
|
|
|
mtx_lock(&device->shader_slab_mutex);
|
|
|
|
list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
|
|
|
|
uint64_t offset = 0;
|
|
|
|
list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) {
|
|
|
|
if (s->bo_offset - offset >= shader->code_size) {
|
|
|
|
shader->bo = slab->bo;
|
|
|
|
shader->bo_offset = offset;
|
|
|
|
list_addtail(&shader->slab_list, &s->slab_list);
|
|
|
|
mtx_unlock(&device->shader_slab_mutex);
|
|
|
|
return slab->ptr + offset;
|
|
|
|
}
|
|
|
|
offset = align_u64(s->bo_offset + s->code_size, 256);
|
|
|
|
}
|
|
|
|
if (slab->size - offset >= shader->code_size) {
|
|
|
|
shader->bo = slab->bo;
|
|
|
|
shader->bo_offset = offset;
|
|
|
|
list_addtail(&shader->slab_list, &slab->shaders);
|
|
|
|
mtx_unlock(&device->shader_slab_mutex);
|
|
|
|
return slab->ptr + offset;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
mtx_unlock(&device->shader_slab_mutex);
|
|
|
|
struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab));
|
|
|
|
|
|
|
|
slab->size = 256 * 1024;
|
|
|
|
slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
|
2018-01-04 14:19:47 +00:00
|
|
|
RADEON_DOMAIN_VRAM,
|
|
|
|
RADEON_FLAG_NO_INTERPROCESS_SHARING |
|
2019-08-20 16:20:42 +01:00
|
|
|
(device->physical_device->rad_info.cpdma_prefetch_writes_memory ?
|
2019-01-27 23:28:05 +00:00
|
|
|
0 : RADEON_FLAG_READ_ONLY),
|
|
|
|
RADV_BO_PRIORITY_SHADER);
|
2017-09-01 10:41:18 +01:00
|
|
|
slab->ptr = (char*)device->ws->buffer_map(slab->bo);
|
|
|
|
list_inithead(&slab->shaders);
|
|
|
|
|
|
|
|
mtx_lock(&device->shader_slab_mutex);
|
|
|
|
list_add(&slab->slabs, &device->shader_slabs);
|
|
|
|
|
|
|
|
shader->bo = slab->bo;
|
|
|
|
shader->bo_offset = 0;
|
|
|
|
list_add(&shader->slab_list, &slab->shaders);
|
|
|
|
mtx_unlock(&device->shader_slab_mutex);
|
|
|
|
return slab->ptr;
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
radv_destroy_shader_slabs(struct radv_device *device)
|
|
|
|
{
|
|
|
|
list_for_each_entry_safe(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
|
|
|
|
device->ws->buffer_destroy(slab->bo);
|
|
|
|
free(slab);
|
|
|
|
}
|
|
|
|
mtx_destroy(&device->shader_slab_mutex);
|
|
|
|
}
|
|
|
|
|
2018-06-27 09:39:51 +01:00
|
|
|
/* For the UMR disassembler. */
|
|
|
|
#define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
|
|
|
|
#define DEBUGGER_NUM_MARKERS 5
|
|
|
|
|
|
|
|
static unsigned
|
2019-07-01 00:29:24 +01:00
|
|
|
radv_get_shader_binary_size(size_t code_size)
|
2018-06-27 09:39:51 +01:00
|
|
|
{
|
2019-07-01 00:29:24 +01:00
|
|
|
return code_size + DEBUGGER_NUM_MARKERS * 4;
|
2018-06-27 09:39:51 +01:00
|
|
|
}
|
|
|
|
|
2019-07-01 00:29:24 +01:00
|
|
|
static void radv_postprocess_config(const struct radv_physical_device *pdevice,
|
|
|
|
const struct ac_shader_config *config_in,
|
2019-09-03 16:39:23 +01:00
|
|
|
const struct radv_shader_info *info,
|
2019-07-01 00:29:24 +01:00
|
|
|
gl_shader_stage stage,
|
|
|
|
struct ac_shader_config *config_out)
|
2017-09-01 10:41:18 +01:00
|
|
|
{
|
2019-07-01 00:29:24 +01:00
|
|
|
bool scratch_enabled = config_in->scratch_bytes_per_wave > 0;
|
2017-09-01 10:41:18 +01:00
|
|
|
unsigned vgpr_comp_cnt = 0;
|
2019-07-01 01:19:13 +01:00
|
|
|
unsigned num_input_vgprs = info->num_input_vgprs;
|
|
|
|
|
|
|
|
if (stage == MESA_SHADER_FRAGMENT) {
|
2019-09-25 15:40:07 +01:00
|
|
|
num_input_vgprs = ac_get_fs_input_vgpr_cnt(config_in, NULL, NULL);
|
2019-07-01 01:19:13 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
unsigned num_vgprs = MAX2(config_in->num_vgprs, num_input_vgprs);
|
|
|
|
/* +3 for scratch wave offset and VCC */
|
|
|
|
unsigned num_sgprs = MAX2(config_in->num_sgprs, info->num_input_sgprs + 3);
|
2019-09-13 14:53:09 +01:00
|
|
|
unsigned num_shared_vgprs = config_in->num_shared_vgprs;
|
|
|
|
/* shared VGPRs are introduced in Navi and are allocated in blocks of 8 (RDNA ref 3.6.5) */
|
|
|
|
assert((pdevice->rad_info.chip_class >= GFX10 && num_shared_vgprs % 8 == 0)
|
|
|
|
|| (pdevice->rad_info.chip_class < GFX10 && num_shared_vgprs == 0));
|
|
|
|
unsigned num_shared_vgpr_blocks = num_shared_vgprs / 8;
|
2017-09-01 10:41:18 +01:00
|
|
|
|
2019-07-01 00:29:24 +01:00
|
|
|
*config_out = *config_in;
|
2019-07-01 01:19:13 +01:00
|
|
|
config_out->num_vgprs = num_vgprs;
|
|
|
|
config_out->num_sgprs = num_sgprs;
|
2019-09-13 14:53:09 +01:00
|
|
|
config_out->num_shared_vgprs = num_shared_vgprs;
|
2019-07-01 01:19:13 +01:00
|
|
|
|
|
|
|
/* Enable 64-bit and 16-bit denormals, because there is no performance
|
|
|
|
* cost.
|
|
|
|
*
|
|
|
|
* If denormals are enabled, all floating-point output modifiers are
|
|
|
|
* ignored.
|
|
|
|
*
|
|
|
|
* Don't enable denormals for 32-bit floats, because:
|
|
|
|
* - Floating-point output modifiers would be ignored by the hw.
|
|
|
|
* - Some opcodes don't support denormals, such as v_mad_f32. We would
|
|
|
|
* have to stop using those.
|
|
|
|
* - GFX6 & GFX7 would be very slow.
|
|
|
|
*/
|
|
|
|
config_out->float_mode |= V_00B028_FP_64_DENORMS;
|
2019-07-01 00:29:24 +01:00
|
|
|
|
|
|
|
config_out->rsrc2 = S_00B12C_USER_SGPR(info->num_user_sgprs) |
|
2019-09-09 09:23:30 +01:00
|
|
|
S_00B12C_SCRATCH_EN(scratch_enabled);
|
|
|
|
|
|
|
|
if (!pdevice->use_ngg_streamout) {
|
|
|
|
config_out->rsrc2 |= S_00B12C_SO_BASE0_EN(!!info->so.strides[0]) |
|
|
|
|
S_00B12C_SO_BASE1_EN(!!info->so.strides[1]) |
|
|
|
|
S_00B12C_SO_BASE2_EN(!!info->so.strides[2]) |
|
|
|
|
S_00B12C_SO_BASE3_EN(!!info->so.strides[3]) |
|
|
|
|
S_00B12C_SO_EN(!!info->so.num_outputs);
|
|
|
|
}
|
2019-07-01 00:29:24 +01:00
|
|
|
|
2019-07-30 17:32:42 +01:00
|
|
|
config_out->rsrc1 = S_00B848_VGPRS((num_vgprs - 1) /
|
2019-09-03 16:39:23 +01:00
|
|
|
(info->wave_size == 32 ? 8 : 4)) |
|
2019-07-01 00:29:24 +01:00
|
|
|
S_00B848_DX10_CLAMP(1) |
|
2019-07-01 01:19:13 +01:00
|
|
|
S_00B848_FLOAT_MODE(config_out->float_mode);
|
2017-10-17 23:59:16 +01:00
|
|
|
|
2019-06-25 12:33:03 +01:00
|
|
|
if (pdevice->rad_info.chip_class >= GFX10) {
|
|
|
|
config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(info->num_user_sgprs >> 5);
|
|
|
|
} else {
|
|
|
|
config_out->rsrc1 |= S_00B228_SGPRS((num_sgprs - 1) / 8);
|
2019-07-23 13:55:16 +01:00
|
|
|
config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(info->num_user_sgprs >> 5);
|
2019-06-25 12:33:03 +01:00
|
|
|
}
|
|
|
|
|
2017-09-01 10:41:18 +01:00
|
|
|
switch (stage) {
|
|
|
|
case MESA_SHADER_TESS_EVAL:
|
2019-07-08 22:44:32 +01:00
|
|
|
if (info->is_ngg) {
|
|
|
|
config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
|
|
|
|
config_out->rsrc2 |= S_00B22C_OC_LDS_EN(1);
|
|
|
|
} else if (info->tes.as_es) {
|
2019-07-01 00:29:24 +01:00
|
|
|
assert(pdevice->rad_info.chip_class <= GFX8);
|
2019-09-03 16:39:23 +01:00
|
|
|
vgpr_comp_cnt = info->uses_prim_id ? 3 : 2;
|
2019-07-08 22:44:32 +01:00
|
|
|
|
|
|
|
config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
|
2019-06-26 14:11:00 +01:00
|
|
|
} else {
|
2019-09-03 16:39:23 +01:00
|
|
|
bool enable_prim_id = info->tes.export_prim_id || info->uses_prim_id;
|
2019-06-26 14:11:00 +01:00
|
|
|
vgpr_comp_cnt = enable_prim_id ? 3 : 2;
|
2019-07-06 11:31:25 +01:00
|
|
|
|
|
|
|
config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
|
2019-07-08 22:44:32 +01:00
|
|
|
config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
|
2019-06-26 14:11:00 +01:00
|
|
|
}
|
2019-09-13 14:53:09 +01:00
|
|
|
config_out->rsrc2 |= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
|
2017-10-17 23:59:16 +01:00
|
|
|
break;
|
2017-09-01 10:41:18 +01:00
|
|
|
case MESA_SHADER_TESS_CTRL:
|
2019-07-01 00:29:24 +01:00
|
|
|
if (pdevice->rad_info.chip_class >= GFX9) {
|
2019-06-26 14:11:03 +01:00
|
|
|
/* We need at least 2 components for LS.
|
|
|
|
* VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
|
|
|
|
* StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
|
|
|
|
*/
|
2019-07-08 22:44:32 +01:00
|
|
|
if (pdevice->rad_info.chip_class >= GFX10) {
|
2019-09-03 16:39:23 +01:00
|
|
|
vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 1;
|
2019-07-08 22:44:32 +01:00
|
|
|
} else {
|
2019-09-03 16:39:23 +01:00
|
|
|
vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1;
|
2019-07-08 22:44:32 +01:00
|
|
|
}
|
2018-05-11 08:46:46 +01:00
|
|
|
} else {
|
2019-07-01 00:29:24 +01:00
|
|
|
config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
|
2018-05-11 08:46:46 +01:00
|
|
|
}
|
2019-07-12 11:17:16 +01:00
|
|
|
config_out->rsrc1 |= S_00B428_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
|
|
|
|
S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
|
2019-09-13 14:53:09 +01:00
|
|
|
config_out->rsrc2 |= S_00B42C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
|
2017-09-01 10:41:18 +01:00
|
|
|
break;
|
|
|
|
case MESA_SHADER_VERTEX:
|
2019-07-05 07:33:06 +01:00
|
|
|
if (info->is_ngg) {
|
|
|
|
config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
|
|
|
|
} else if (info->vs.as_ls) {
|
2019-07-01 00:29:24 +01:00
|
|
|
assert(pdevice->rad_info.chip_class <= GFX8);
|
2019-06-26 14:11:03 +01:00
|
|
|
/* We need at least 2 components for LS.
|
|
|
|
* VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
|
|
|
|
* StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
|
|
|
|
*/
|
2019-09-03 16:39:23 +01:00
|
|
|
vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1;
|
2019-07-01 00:29:24 +01:00
|
|
|
} else if (info->vs.as_es) {
|
|
|
|
assert(pdevice->rad_info.chip_class <= GFX8);
|
2019-06-26 14:11:03 +01:00
|
|
|
/* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
|
2019-09-03 16:39:23 +01:00
|
|
|
vgpr_comp_cnt = info->vs.needs_instance_id ? 1 : 0;
|
2019-06-26 14:11:03 +01:00
|
|
|
} else {
|
|
|
|
/* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
|
|
|
|
* If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
|
|
|
|
* StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
|
|
|
|
*/
|
2019-09-03 16:39:23 +01:00
|
|
|
if (info->vs.needs_instance_id && pdevice->rad_info.chip_class >= GFX10) {
|
2019-08-21 00:50:53 +01:00
|
|
|
vgpr_comp_cnt = 3;
|
|
|
|
} else if (info->vs.export_prim_id) {
|
2019-06-26 14:11:03 +01:00
|
|
|
vgpr_comp_cnt = 2;
|
2019-09-03 16:39:23 +01:00
|
|
|
} else if (info->vs.needs_instance_id) {
|
2019-08-21 00:50:53 +01:00
|
|
|
vgpr_comp_cnt = 1;
|
2019-06-26 14:11:03 +01:00
|
|
|
} else {
|
|
|
|
vgpr_comp_cnt = 0;
|
|
|
|
}
|
2019-07-06 11:31:25 +01:00
|
|
|
|
|
|
|
config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
|
2019-09-13 14:53:09 +01:00
|
|
|
config_out->rsrc2 |= S_00B12C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
|
2019-06-26 14:11:03 +01:00
|
|
|
}
|
2017-09-01 10:41:18 +01:00
|
|
|
break;
|
|
|
|
case MESA_SHADER_FRAGMENT:
|
2019-07-06 11:31:25 +01:00
|
|
|
config_out->rsrc1 |= S_00B028_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
|
2019-09-13 14:53:09 +01:00
|
|
|
config_out->rsrc2 |= S_00B02C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
|
2019-07-06 11:31:25 +01:00
|
|
|
break;
|
2019-06-26 14:11:01 +01:00
|
|
|
case MESA_SHADER_GEOMETRY:
|
2019-07-12 11:17:16 +01:00
|
|
|
config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
|
|
|
|
S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
|
2019-09-13 14:53:09 +01:00
|
|
|
config_out->rsrc2 |= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
|
2017-09-01 10:41:18 +01:00
|
|
|
break;
|
2018-05-11 08:46:46 +01:00
|
|
|
case MESA_SHADER_COMPUTE:
|
2019-07-12 11:17:16 +01:00
|
|
|
config_out->rsrc1 |= S_00B848_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
|
|
|
|
S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
|
2019-07-01 00:29:24 +01:00
|
|
|
config_out->rsrc2 |=
|
2019-09-03 16:39:23 +01:00
|
|
|
S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) |
|
|
|
|
S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) |
|
|
|
|
S_00B84C_TGID_Z_EN(info->cs.uses_block_id[2]) |
|
|
|
|
S_00B84C_TIDIG_COMP_CNT(info->cs.uses_thread_id[2] ? 2 :
|
|
|
|
info->cs.uses_thread_id[1] ? 1 : 0) |
|
|
|
|
S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx) |
|
2019-07-01 00:29:24 +01:00
|
|
|
S_00B84C_LDS_SIZE(config_in->lds_size);
|
2019-09-13 14:53:09 +01:00
|
|
|
config_out->rsrc3 |= S_00B8A0_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
|
|
|
|
|
2017-09-01 10:41:18 +01:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
unreachable("unsupported shader type");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2019-07-16 15:39:16 +01:00
|
|
|
if (pdevice->rad_info.chip_class >= GFX10 && info->is_ngg &&
|
2019-07-09 07:44:01 +01:00
|
|
|
(stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_TESS_EVAL || stage == MESA_SHADER_GEOMETRY)) {
|
2019-07-05 07:33:06 +01:00
|
|
|
unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
|
2019-07-11 07:44:15 +01:00
|
|
|
gl_shader_stage es_stage = stage;
|
|
|
|
if (stage == MESA_SHADER_GEOMETRY)
|
|
|
|
es_stage = info->gs.es_type;
|
2019-07-05 07:33:06 +01:00
|
|
|
|
|
|
|
/* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
|
2019-07-11 07:44:15 +01:00
|
|
|
if (es_stage == MESA_SHADER_VERTEX) {
|
2019-09-03 16:39:23 +01:00
|
|
|
es_vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 0;
|
2019-07-11 07:44:15 +01:00
|
|
|
} else if (es_stage == MESA_SHADER_TESS_EVAL) {
|
2019-09-03 16:39:23 +01:00
|
|
|
bool enable_prim_id = info->tes.export_prim_id || info->uses_prim_id;
|
2019-07-09 07:27:30 +01:00
|
|
|
es_vgpr_comp_cnt = enable_prim_id ? 3 : 2;
|
2019-07-18 23:00:03 +01:00
|
|
|
} else
|
|
|
|
unreachable("Unexpected ES shader stage");
|
2019-07-08 22:44:32 +01:00
|
|
|
|
|
|
|
bool tes_triangles = stage == MESA_SHADER_TESS_EVAL &&
|
|
|
|
info->tes.primitive_mode >= 4; /* GL_TRIANGLES */
|
2019-09-03 16:39:23 +01:00
|
|
|
if (info->uses_invocation_id || stage == MESA_SHADER_VERTEX) {
|
2019-07-08 22:44:32 +01:00
|
|
|
gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
|
2019-09-03 16:39:23 +01:00
|
|
|
} else if (info->uses_prim_id) {
|
2019-07-08 22:44:32 +01:00
|
|
|
gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
|
|
|
|
} else if (info->gs.vertices_in >= 3 || tes_triangles) {
|
|
|
|
gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
|
|
|
|
} else {
|
|
|
|
gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
|
|
|
|
}
|
2019-07-05 07:33:06 +01:00
|
|
|
|
2019-07-12 11:17:16 +01:00
|
|
|
config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt) |
|
|
|
|
S_00B228_WGP_MODE(1);
|
2019-07-05 07:33:06 +01:00
|
|
|
config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
|
2019-07-15 17:46:48 +01:00
|
|
|
S_00B22C_LDS_SIZE(config_in->lds_size) |
|
|
|
|
S_00B22C_OC_LDS_EN(es_stage == MESA_SHADER_TESS_EVAL);
|
2019-07-05 07:33:06 +01:00
|
|
|
} else if (pdevice->rad_info.chip_class >= GFX9 &&
|
|
|
|
stage == MESA_SHADER_GEOMETRY) {
|
2019-07-01 00:29:24 +01:00
|
|
|
unsigned es_type = info->gs.es_type;
|
2018-01-09 15:01:10 +00:00
|
|
|
unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
|
|
|
|
|
|
|
|
if (es_type == MESA_SHADER_VERTEX) {
|
2019-06-26 14:11:03 +01:00
|
|
|
/* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
|
2019-09-03 16:39:23 +01:00
|
|
|
if (info->vs.needs_instance_id) {
|
2019-07-23 10:52:36 +01:00
|
|
|
es_vgpr_comp_cnt = pdevice->rad_info.chip_class >= GFX10 ? 3 : 1;
|
|
|
|
} else {
|
|
|
|
es_vgpr_comp_cnt = 0;
|
|
|
|
}
|
2018-01-09 15:01:10 +00:00
|
|
|
} else if (es_type == MESA_SHADER_TESS_EVAL) {
|
2019-09-03 16:39:23 +01:00
|
|
|
es_vgpr_comp_cnt = info->uses_prim_id ? 3 : 2;
|
2018-01-09 15:01:10 +00:00
|
|
|
} else {
|
2018-01-17 22:23:02 +00:00
|
|
|
unreachable("invalid shader ES type");
|
2018-01-09 15:01:10 +00:00
|
|
|
}
|
2017-12-20 19:56:57 +00:00
|
|
|
|
|
|
|
/* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
|
|
|
|
* VGPR[0:4] are always loaded.
|
|
|
|
*/
|
2019-09-03 16:39:23 +01:00
|
|
|
if (info->uses_invocation_id) {
|
2017-12-20 19:56:57 +00:00
|
|
|
gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
|
2019-09-03 16:39:23 +01:00
|
|
|
} else if (info->uses_prim_id) {
|
2017-12-20 19:56:57 +00:00
|
|
|
gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
|
2019-07-01 00:29:24 +01:00
|
|
|
} else if (info->gs.vertices_in >= 3) {
|
2018-01-05 16:18:52 +00:00
|
|
|
gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
|
2018-05-11 08:46:46 +01:00
|
|
|
} else {
|
2018-01-05 16:18:52 +00:00
|
|
|
gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
|
2018-05-11 08:46:46 +01:00
|
|
|
}
|
2017-12-20 19:56:57 +00:00
|
|
|
|
2019-07-01 00:29:24 +01:00
|
|
|
config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
|
|
|
|
config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
|
2019-06-30 00:47:30 +01:00
|
|
|
S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL);
|
2019-07-01 00:29:24 +01:00
|
|
|
} else if (pdevice->rad_info.chip_class >= GFX9 &&
|
2018-05-11 08:46:46 +01:00
|
|
|
stage == MESA_SHADER_TESS_CTRL) {
|
2019-07-01 00:29:24 +01:00
|
|
|
config_out->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
|
2018-05-11 08:46:46 +01:00
|
|
|
} else {
|
2019-07-01 00:29:24 +01:00
|
|
|
config_out->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt);
|
2018-05-11 08:46:46 +01:00
|
|
|
}
|
2017-09-01 10:41:18 +01:00
|
|
|
}
|
|
|
|
|
2019-07-01 00:29:24 +01:00
|
|
|
struct radv_shader_variant *
|
|
|
|
radv_shader_variant_create(struct radv_device *device,
|
2019-05-31 00:06:27 +01:00
|
|
|
const struct radv_shader_binary *binary,
|
|
|
|
bool keep_shader_info)
|
2019-07-01 00:29:24 +01:00
|
|
|
{
|
|
|
|
struct ac_shader_config config = {0};
|
|
|
|
struct ac_rtld_binary rtld_binary = {0};
|
|
|
|
struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
|
|
|
|
if (!variant)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
variant->ref_count = 1;
|
|
|
|
|
|
|
|
if (binary->type == RADV_BINARY_TYPE_RTLD) {
|
2019-09-03 12:01:54 +01:00
|
|
|
struct ac_rtld_symbol lds_symbols[2];
|
2019-07-01 00:29:24 +01:00
|
|
|
unsigned num_lds_symbols = 0;
|
|
|
|
const char *elf_data = (const char *)((struct radv_shader_binary_rtld *)binary)->data;
|
|
|
|
size_t elf_size = ((struct radv_shader_binary_rtld *)binary)->elf_size;
|
|
|
|
|
|
|
|
if (device->physical_device->rad_info.chip_class >= GFX9 &&
|
2019-09-03 12:01:54 +01:00
|
|
|
(binary->stage == MESA_SHADER_GEOMETRY || binary->info.is_ngg) &&
|
|
|
|
!binary->is_gs_copy_shader) {
|
2019-07-01 00:29:24 +01:00
|
|
|
/* We add this symbol even on LLVM <= 8 to ensure that
|
|
|
|
* shader->config.lds_size is set correctly below.
|
|
|
|
*/
|
|
|
|
struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
|
|
|
|
sym->name = "esgs_ring";
|
2019-09-18 08:58:54 +01:00
|
|
|
sym->size = binary->info.ngg_info.esgs_ring_size;
|
2019-07-01 00:29:24 +01:00
|
|
|
sym->align = 64 * 1024;
|
2019-09-03 12:01:54 +01:00
|
|
|
}
|
2019-07-11 07:44:16 +01:00
|
|
|
|
2019-09-03 12:01:54 +01:00
|
|
|
if (binary->info.is_ngg &&
|
|
|
|
binary->stage == MESA_SHADER_GEOMETRY) {
|
|
|
|
struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
|
|
|
|
sym->name = "ngg_emit";
|
|
|
|
sym->size = binary->info.ngg_info.ngg_emit_size * 4;
|
|
|
|
sym->align = 4;
|
2019-07-01 00:29:24 +01:00
|
|
|
}
|
2019-07-30 17:32:42 +01:00
|
|
|
|
2019-07-01 00:29:24 +01:00
|
|
|
struct ac_rtld_open_info open_info = {
|
|
|
|
.info = &device->physical_device->rad_info,
|
|
|
|
.shader_type = binary->stage,
|
2019-09-03 16:39:23 +01:00
|
|
|
.wave_size = binary->info.wave_size,
|
2019-07-01 00:29:24 +01:00
|
|
|
.num_parts = 1,
|
|
|
|
.elf_ptrs = &elf_data,
|
|
|
|
.elf_sizes = &elf_size,
|
|
|
|
.num_shared_lds_symbols = num_lds_symbols,
|
|
|
|
.shared_lds_symbols = lds_symbols,
|
|
|
|
};
|
|
|
|
|
|
|
|
if (!ac_rtld_open(&rtld_binary, open_info)) {
|
|
|
|
free(variant);
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!ac_rtld_read_config(&rtld_binary, &config)) {
|
|
|
|
ac_rtld_close(&rtld_binary);
|
|
|
|
free(variant);
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (rtld_binary.lds_size > 0) {
|
|
|
|
unsigned alloc_granularity = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
|
|
|
|
config.lds_size = align(rtld_binary.lds_size, alloc_granularity) / alloc_granularity;
|
|
|
|
}
|
|
|
|
|
|
|
|
variant->code_size = rtld_binary.rx_size;
|
2019-08-29 16:15:46 +01:00
|
|
|
variant->exec_size = rtld_binary.exec_size;
|
2019-07-01 00:29:24 +01:00
|
|
|
} else {
|
|
|
|
assert(binary->type == RADV_BINARY_TYPE_LEGACY);
|
|
|
|
config = ((struct radv_shader_binary_legacy *)binary)->config;
|
2019-08-29 16:15:46 +01:00
|
|
|
variant->code_size = radv_get_shader_binary_size(((struct radv_shader_binary_legacy *)binary)->code_size);
|
2019-09-17 13:35:22 +01:00
|
|
|
variant->exec_size = ((struct radv_shader_binary_legacy *)binary)->exec_size;
|
2019-07-01 00:29:24 +01:00
|
|
|
}
|
|
|
|
|
2019-09-03 16:39:23 +01:00
|
|
|
variant->info = binary->info;
|
|
|
|
radv_postprocess_config(device->physical_device, &config, &binary->info,
|
2019-07-01 00:29:24 +01:00
|
|
|
binary->stage, &variant->config);
|
|
|
|
|
|
|
|
void *dest_ptr = radv_alloc_shader_memory(device, variant);
|
|
|
|
|
|
|
|
if (binary->type == RADV_BINARY_TYPE_RTLD) {
|
|
|
|
struct radv_shader_binary_rtld* bin = (struct radv_shader_binary_rtld *)binary;
|
|
|
|
struct ac_rtld_upload_info info = {
|
|
|
|
.binary = &rtld_binary,
|
|
|
|
.rx_va = radv_buffer_get_va(variant->bo) + variant->bo_offset,
|
|
|
|
.rx_ptr = dest_ptr,
|
|
|
|
};
|
|
|
|
|
|
|
|
if (!ac_rtld_upload(&info)) {
|
|
|
|
radv_shader_variant_destroy(device, variant);
|
|
|
|
ac_rtld_close(&rtld_binary);
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2019-05-31 00:06:27 +01:00
|
|
|
if (keep_shader_info ||
|
2019-07-23 08:55:24 +01:00
|
|
|
(device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS)) {
|
2019-07-17 05:20:55 +01:00
|
|
|
const char *disasm_data;
|
|
|
|
size_t disasm_size;
|
|
|
|
if (!ac_rtld_get_section_by_name(&rtld_binary, ".AMDGPU.disasm", &disasm_data, &disasm_size)) {
|
|
|
|
radv_shader_variant_destroy(device, variant);
|
|
|
|
ac_rtld_close(&rtld_binary);
|
|
|
|
return NULL;
|
|
|
|
}
|
2019-07-01 00:29:24 +01:00
|
|
|
|
2019-09-25 11:48:04 +01:00
|
|
|
variant->ir_string = bin->llvm_ir_size ? strdup((const char*)(bin->data + bin->elf_size)) : NULL;
|
2019-07-17 05:20:55 +01:00
|
|
|
variant->disasm_string = malloc(disasm_size + 1);
|
|
|
|
memcpy(variant->disasm_string, disasm_data, disasm_size);
|
|
|
|
variant->disasm_string[disasm_size] = 0;
|
|
|
|
}
|
2019-07-01 00:29:24 +01:00
|
|
|
|
|
|
|
ac_rtld_close(&rtld_binary);
|
|
|
|
} else {
|
|
|
|
struct radv_shader_binary_legacy* bin = (struct radv_shader_binary_legacy *)binary;
|
|
|
|
memcpy(dest_ptr, bin->data, bin->code_size);
|
|
|
|
|
|
|
|
/* Add end-of-code markers for the UMR disassembler. */
|
|
|
|
uint32_t *ptr32 = (uint32_t *)dest_ptr + bin->code_size / 4;
|
|
|
|
for (unsigned i = 0; i < DEBUGGER_NUM_MARKERS; i++)
|
|
|
|
ptr32[i] = DEBUGGER_END_OF_CODE_MARKER;
|
|
|
|
|
2019-09-25 11:48:04 +01:00
|
|
|
variant->ir_string = bin->ir_size ? strdup((const char*)(bin->data + bin->code_size)) : NULL;
|
|
|
|
variant->disasm_string = bin->disasm_size ? strdup((const char*)(bin->data + bin->code_size + bin->ir_size)) : NULL;
|
2019-07-01 00:29:24 +01:00
|
|
|
}
|
|
|
|
return variant;
|
|
|
|
}
|
|
|
|
|
2019-06-01 19:54:35 +01:00
|
|
|
static char *
|
|
|
|
radv_dump_nir_shaders(struct nir_shader * const *shaders,
|
|
|
|
int shader_count)
|
|
|
|
{
|
|
|
|
char *data = NULL;
|
|
|
|
char *ret = NULL;
|
|
|
|
size_t size = 0;
|
|
|
|
FILE *f = open_memstream(&data, &size);
|
|
|
|
if (f) {
|
|
|
|
for (int i = 0; i < shader_count; ++i)
|
|
|
|
nir_print_shader(shaders[i], f);
|
|
|
|
fclose(f);
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = malloc(size + 1);
|
|
|
|
if (ret) {
|
|
|
|
memcpy(ret, data, size);
|
|
|
|
ret[size] = 0;
|
|
|
|
}
|
|
|
|
free(data);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2017-09-01 15:51:12 +01:00
|
|
|
static struct radv_shader_variant *
|
2019-07-01 00:29:24 +01:00
|
|
|
shader_variant_compile(struct radv_device *device,
|
|
|
|
struct radv_shader_module *module,
|
|
|
|
struct nir_shader * const *shaders,
|
|
|
|
int shader_count,
|
|
|
|
gl_shader_stage stage,
|
2019-09-03 09:29:19 +01:00
|
|
|
struct radv_shader_info *info,
|
2019-07-01 00:29:24 +01:00
|
|
|
struct radv_nir_compiler_options *options,
|
|
|
|
bool gs_copy_shader,
|
2019-05-31 00:06:27 +01:00
|
|
|
bool keep_shader_info,
|
2019-09-17 13:35:22 +01:00
|
|
|
bool use_aco,
|
2019-07-01 00:29:24 +01:00
|
|
|
struct radv_shader_binary **binary_out)
|
2017-09-01 10:41:18 +01:00
|
|
|
{
|
|
|
|
enum radeon_family chip_family = device->physical_device->rad_info.family;
|
2019-07-01 00:29:24 +01:00
|
|
|
struct radv_shader_binary *binary = NULL;
|
2017-09-01 10:41:18 +01:00
|
|
|
|
2017-09-01 15:51:12 +01:00
|
|
|
options->family = chip_family;
|
|
|
|
options->chip_class = device->physical_device->rad_info.chip_class;
|
2018-05-11 15:36:02 +01:00
|
|
|
options->dump_shader = radv_can_dump_shader(device, module, gs_copy_shader);
|
2018-03-14 09:28:49 +00:00
|
|
|
options->dump_preoptir = options->dump_shader &&
|
2018-01-19 11:12:02 +00:00
|
|
|
device->instance->debug_flags & RADV_DEBUG_PREOPTIR;
|
2019-09-25 11:48:04 +01:00
|
|
|
options->record_ir = keep_shader_info;
|
2018-06-14 13:28:58 +01:00
|
|
|
options->check_ir = device->instance->debug_flags & RADV_DEBUG_CHECKIR;
|
2018-02-19 07:14:04 +00:00
|
|
|
options->tess_offchip_block_dw_size = device->tess_offchip_block_dw_size;
|
2018-05-16 15:02:04 +01:00
|
|
|
options->address32_hi = device->physical_device->rad_info.address32_hi;
|
2019-08-23 07:55:53 +01:00
|
|
|
options->has_ls_vgpr_init_bug = device->physical_device->rad_info.has_ls_vgpr_init_bug;
|
2019-09-09 09:23:30 +01:00
|
|
|
options->use_ngg_streamout = device->physical_device->use_ngg_streamout;
|
2019-08-03 23:48:05 +01:00
|
|
|
|
2019-08-04 00:29:53 +01:00
|
|
|
if ((stage == MESA_SHADER_GEOMETRY && !options->key.vs_common_out.as_ngg) ||
|
|
|
|
gs_copy_shader)
|
|
|
|
options->wave_size = 64;
|
|
|
|
else if (stage == MESA_SHADER_COMPUTE)
|
2019-08-03 23:48:05 +01:00
|
|
|
options->wave_size = device->physical_device->cs_wave_size;
|
|
|
|
else if (stage == MESA_SHADER_FRAGMENT)
|
|
|
|
options->wave_size = device->physical_device->ps_wave_size;
|
|
|
|
else
|
|
|
|
options->wave_size = device->physical_device->ge_wave_size;
|
2017-09-01 10:41:18 +01:00
|
|
|
|
2019-09-25 11:48:04 +01:00
|
|
|
if (!use_aco || options->dump_shader || options->record_ir)
|
2019-09-17 13:35:22 +01:00
|
|
|
ac_init_llvm_once();
|
|
|
|
|
|
|
|
if (use_aco) {
|
|
|
|
aco_compile_shader(shader_count, shaders, &binary, info, options);
|
|
|
|
binary->info = *info;
|
2017-09-01 15:51:12 +01:00
|
|
|
} else {
|
2019-09-17 13:35:22 +01:00
|
|
|
enum ac_target_machine_options tm_options = 0;
|
|
|
|
struct ac_llvm_compiler ac_llvm;
|
|
|
|
bool thread_compiler;
|
|
|
|
|
|
|
|
if (options->supports_spill)
|
|
|
|
tm_options |= AC_TM_SUPPORTS_SPILL;
|
|
|
|
if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
|
|
|
|
tm_options |= AC_TM_SISCHED;
|
|
|
|
if (options->check_ir)
|
|
|
|
tm_options |= AC_TM_CHECK_IR;
|
|
|
|
if (device->instance->debug_flags & RADV_DEBUG_NO_LOAD_STORE_OPT)
|
|
|
|
tm_options |= AC_TM_NO_LOAD_STORE_OPT;
|
|
|
|
|
|
|
|
thread_compiler = !(device->instance->debug_flags & RADV_DEBUG_NOTHREADLLVM);
|
|
|
|
radv_init_llvm_compiler(&ac_llvm,
|
|
|
|
thread_compiler,
|
|
|
|
chip_family, tm_options,
|
|
|
|
options->wave_size);
|
|
|
|
|
|
|
|
if (gs_copy_shader) {
|
|
|
|
assert(shader_count == 1);
|
|
|
|
radv_compile_gs_copy_shader(&ac_llvm, *shaders, &binary,
|
|
|
|
info, options);
|
|
|
|
} else {
|
|
|
|
radv_compile_nir_shader(&ac_llvm, &binary, info,
|
|
|
|
shaders, shader_count, options);
|
|
|
|
}
|
2017-09-01 15:51:12 +01:00
|
|
|
|
2019-09-17 13:35:22 +01:00
|
|
|
binary->info = *info;
|
|
|
|
radv_destroy_llvm_compiler(&ac_llvm, thread_compiler);
|
|
|
|
}
|
2017-09-01 10:41:18 +01:00
|
|
|
|
2019-05-31 00:06:27 +01:00
|
|
|
struct radv_shader_variant *variant = radv_shader_variant_create(device, binary,
|
|
|
|
keep_shader_info);
|
2019-07-01 00:29:24 +01:00
|
|
|
if (!variant) {
|
|
|
|
free(binary);
|
|
|
|
return NULL;
|
|
|
|
}
|
2019-09-24 15:25:07 +01:00
|
|
|
variant->aco_used = use_aco;
|
2017-09-01 12:45:33 +01:00
|
|
|
|
2019-07-01 01:19:13 +01:00
|
|
|
if (options->dump_shader) {
|
|
|
|
fprintf(stderr, "disasm:\n%s\n", variant->disasm_string);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2019-05-31 00:06:27 +01:00
|
|
|
if (keep_shader_info) {
|
2019-06-01 19:54:35 +01:00
|
|
|
variant->nir_string = radv_dump_nir_shaders(shaders, shader_count);
|
2017-09-22 15:44:08 +01:00
|
|
|
if (!gs_copy_shader && !module->nir) {
|
2017-09-22 15:56:40 +01:00
|
|
|
variant->spirv = (uint32_t *)module->data;
|
|
|
|
variant->spirv_size = module->size;
|
2017-09-22 15:44:08 +01:00
|
|
|
}
|
2017-09-01 12:45:33 +01:00
|
|
|
}
|
|
|
|
|
2019-07-01 00:29:24 +01:00
|
|
|
if (binary_out)
|
|
|
|
*binary_out = binary;
|
|
|
|
else
|
|
|
|
free(binary);
|
|
|
|
|
2017-09-01 10:41:18 +01:00
|
|
|
return variant;
|
|
|
|
}
|
|
|
|
|
|
|
|
struct radv_shader_variant *
|
2019-07-01 00:29:24 +01:00
|
|
|
radv_shader_variant_compile(struct radv_device *device,
|
2017-09-22 15:44:08 +01:00
|
|
|
struct radv_shader_module *module,
|
2017-10-16 12:18:02 +01:00
|
|
|
struct nir_shader *const *shaders,
|
|
|
|
int shader_count,
|
2017-09-01 15:51:12 +01:00
|
|
|
struct radv_pipeline_layout *layout,
|
2018-03-13 13:54:04 +00:00
|
|
|
const struct radv_shader_variant_key *key,
|
2019-09-03 09:29:19 +01:00
|
|
|
struct radv_shader_info *info,
|
2019-05-31 00:06:27 +01:00
|
|
|
bool keep_shader_info,
|
2019-09-17 13:35:22 +01:00
|
|
|
bool use_aco,
|
2019-07-01 00:29:24 +01:00
|
|
|
struct radv_shader_binary **binary_out)
|
2017-09-01 10:41:18 +01:00
|
|
|
{
|
2018-03-13 13:54:04 +00:00
|
|
|
struct radv_nir_compiler_options options = {0};
|
2017-09-01 10:41:18 +01:00
|
|
|
|
2017-09-01 15:51:12 +01:00
|
|
|
options.layout = layout;
|
|
|
|
if (key)
|
|
|
|
options.key = *key;
|
|
|
|
|
2017-10-11 01:59:20 +01:00
|
|
|
options.unsafe_math = !!(device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH);
|
2018-05-17 08:56:47 +01:00
|
|
|
options.supports_spill = true;
|
2019-08-02 11:40:17 +01:00
|
|
|
options.robust_buffer_access = device->robust_buffer_access;
|
2017-09-01 15:51:12 +01:00
|
|
|
|
2019-09-03 09:29:19 +01:00
|
|
|
return shader_variant_compile(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage, info,
|
2019-09-17 13:35:22 +01:00
|
|
|
&options, false, keep_shader_info, use_aco, binary_out);
|
2017-09-01 15:51:12 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
struct radv_shader_variant *
|
|
|
|
radv_create_gs_copy_shader(struct radv_device *device,
|
|
|
|
struct nir_shader *shader,
|
2019-09-03 09:29:19 +01:00
|
|
|
struct radv_shader_info *info,
|
2019-07-01 00:29:24 +01:00
|
|
|
struct radv_shader_binary **binary_out,
|
2019-05-31 00:06:27 +01:00
|
|
|
bool keep_shader_info,
|
2017-09-01 15:51:12 +01:00
|
|
|
bool multiview)
|
|
|
|
{
|
2018-03-13 13:54:04 +00:00
|
|
|
struct radv_nir_compiler_options options = {0};
|
2017-09-01 10:41:18 +01:00
|
|
|
|
2017-09-01 15:51:12 +01:00
|
|
|
options.key.has_multiview_view_index = multiview;
|
2017-09-01 10:41:18 +01:00
|
|
|
|
2019-07-01 00:29:24 +01:00
|
|
|
return shader_variant_compile(device, NULL, &shader, 1, MESA_SHADER_VERTEX,
|
2019-09-17 13:35:22 +01:00
|
|
|
info, &options, true, keep_shader_info, false, binary_out);
|
2017-09-01 10:41:18 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
radv_shader_variant_destroy(struct radv_device *device,
|
|
|
|
struct radv_shader_variant *variant)
|
|
|
|
{
|
|
|
|
if (!p_atomic_dec_zero(&variant->ref_count))
|
|
|
|
return;
|
|
|
|
|
|
|
|
mtx_lock(&device->shader_slab_mutex);
|
|
|
|
list_del(&variant->slab_list);
|
|
|
|
mtx_unlock(&device->shader_slab_mutex);
|
|
|
|
|
2019-06-01 19:54:35 +01:00
|
|
|
free(variant->nir_string);
|
2017-09-01 12:45:33 +01:00
|
|
|
free(variant->disasm_string);
|
2019-09-25 11:48:04 +01:00
|
|
|
free(variant->ir_string);
|
2017-09-01 10:41:18 +01:00
|
|
|
free(variant);
|
|
|
|
}
|
|
|
|
|
|
|
|
const char *
|
2019-09-03 16:39:23 +01:00
|
|
|
radv_get_shader_name(struct radv_shader_info *info,
|
2019-07-11 17:03:55 +01:00
|
|
|
gl_shader_stage stage)
|
2017-09-01 10:41:18 +01:00
|
|
|
{
|
|
|
|
switch (stage) {
|
2019-07-11 17:03:55 +01:00
|
|
|
case MESA_SHADER_VERTEX:
|
|
|
|
if (info->vs.as_ls)
|
|
|
|
return "Vertex Shader as LS";
|
|
|
|
else if (info->vs.as_es)
|
|
|
|
return "Vertex Shader as ES";
|
|
|
|
else if (info->is_ngg)
|
|
|
|
return "Vertex Shader as ESGS";
|
|
|
|
else
|
|
|
|
return "Vertex Shader as VS";
|
|
|
|
case MESA_SHADER_TESS_CTRL:
|
|
|
|
return "Tessellation Control Shader";
|
|
|
|
case MESA_SHADER_TESS_EVAL:
|
|
|
|
if (info->tes.as_es)
|
|
|
|
return "Tessellation Evaluation Shader as ES";
|
|
|
|
else if (info->is_ngg)
|
|
|
|
return "Tessellation Evaluation Shader as ESGS";
|
|
|
|
else
|
|
|
|
return "Tessellation Evaluation Shader as VS";
|
|
|
|
case MESA_SHADER_GEOMETRY:
|
|
|
|
return "Geometry Shader";
|
|
|
|
case MESA_SHADER_FRAGMENT:
|
|
|
|
return "Pixel Shader";
|
|
|
|
case MESA_SHADER_COMPUTE:
|
|
|
|
return "Compute Shader";
|
2017-09-01 10:41:18 +01:00
|
|
|
default:
|
|
|
|
return "Unknown shader";
|
|
|
|
};
|
|
|
|
}
|
|
|
|
|
2019-06-01 19:25:47 +01:00
|
|
|
unsigned
|
|
|
|
radv_get_max_workgroup_size(enum chip_class chip_class,
|
|
|
|
gl_shader_stage stage,
|
|
|
|
const unsigned *sizes)
|
|
|
|
{
|
|
|
|
switch (stage) {
|
|
|
|
case MESA_SHADER_TESS_CTRL:
|
|
|
|
return chip_class >= GFX7 ? 128 : 64;
|
|
|
|
case MESA_SHADER_GEOMETRY:
|
|
|
|
return chip_class >= GFX9 ? 128 : 64;
|
|
|
|
case MESA_SHADER_COMPUTE:
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned max_workgroup_size = sizes[0] * sizes[1] * sizes[2];
|
|
|
|
return max_workgroup_size;
|
|
|
|
}
|
2019-06-01 17:46:21 +01:00
|
|
|
|
|
|
|
unsigned
|
|
|
|
radv_get_max_waves(struct radv_device *device,
|
|
|
|
struct radv_shader_variant *variant,
|
|
|
|
gl_shader_stage stage)
|
2017-09-05 14:34:07 +01:00
|
|
|
{
|
2019-02-01 11:04:39 +00:00
|
|
|
enum chip_class chip_class = device->physical_device->rad_info.chip_class;
|
2019-05-15 03:16:20 +01:00
|
|
|
unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
|
2019-09-03 16:39:23 +01:00
|
|
|
uint8_t wave_size = variant->info.wave_size;
|
2019-06-01 17:46:21 +01:00
|
|
|
struct ac_shader_config *conf = &variant->config;
|
2017-09-05 14:34:07 +01:00
|
|
|
unsigned max_simd_waves;
|
|
|
|
unsigned lds_per_wave = 0;
|
|
|
|
|
2019-09-13 00:39:02 +01:00
|
|
|
max_simd_waves = device->physical_device->rad_info.max_wave64_per_simd;
|
2017-09-05 14:34:07 +01:00
|
|
|
|
|
|
|
if (stage == MESA_SHADER_FRAGMENT) {
|
|
|
|
lds_per_wave = conf->lds_size * lds_increment +
|
2019-09-03 16:39:23 +01:00
|
|
|
align(variant->info.ps.num_interp * 48,
|
2017-09-05 14:34:07 +01:00
|
|
|
lds_increment);
|
2019-02-01 11:04:39 +00:00
|
|
|
} else if (stage == MESA_SHADER_COMPUTE) {
|
|
|
|
unsigned max_workgroup_size =
|
2019-06-01 19:25:47 +01:00
|
|
|
radv_get_max_workgroup_size(chip_class, stage, variant->info.cs.block_size);
|
2019-02-01 11:04:39 +00:00
|
|
|
lds_per_wave = (conf->lds_size * lds_increment) /
|
2019-07-30 17:32:42 +01:00
|
|
|
DIV_ROUND_UP(max_workgroup_size, wave_size);
|
2017-09-05 14:34:07 +01:00
|
|
|
}
|
|
|
|
|
2017-10-27 14:25:05 +01:00
|
|
|
if (conf->num_sgprs)
|
2018-04-06 13:06:24 +01:00
|
|
|
max_simd_waves =
|
|
|
|
MIN2(max_simd_waves,
|
2019-09-13 00:46:02 +01:00
|
|
|
device->physical_device->rad_info.num_physical_sgprs_per_simd /
|
2019-08-28 22:38:50 +01:00
|
|
|
conf->num_sgprs);
|
2017-09-05 14:34:07 +01:00
|
|
|
|
|
|
|
if (conf->num_vgprs)
|
2018-04-06 13:10:34 +01:00
|
|
|
max_simd_waves =
|
|
|
|
MIN2(max_simd_waves,
|
|
|
|
RADV_NUM_PHYSICAL_VGPRS / conf->num_vgprs);
|
2017-09-05 14:34:07 +01:00
|
|
|
|
|
|
|
/* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
|
|
|
|
* that PS can use.
|
|
|
|
*/
|
|
|
|
if (lds_per_wave)
|
|
|
|
max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
|
|
|
|
|
2019-06-01 17:46:21 +01:00
|
|
|
return max_simd_waves;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
generate_shader_stats(struct radv_device *device,
|
|
|
|
struct radv_shader_variant *variant,
|
|
|
|
gl_shader_stage stage,
|
|
|
|
struct _mesa_string_buffer *buf)
|
|
|
|
{
|
|
|
|
struct ac_shader_config *conf = &variant->config;
|
|
|
|
unsigned max_simd_waves = radv_get_max_waves(device, variant, stage);
|
|
|
|
|
2017-10-27 14:25:05 +01:00
|
|
|
if (stage == MESA_SHADER_FRAGMENT) {
|
|
|
|
_mesa_string_buffer_printf(buf, "*** SHADER CONFIG ***\n"
|
|
|
|
"SPI_PS_INPUT_ADDR = 0x%04x\n"
|
|
|
|
"SPI_PS_INPUT_ENA = 0x%04x\n",
|
|
|
|
conf->spi_ps_input_addr, conf->spi_ps_input_ena);
|
|
|
|
}
|
|
|
|
|
|
|
|
_mesa_string_buffer_printf(buf, "*** SHADER STATS ***\n"
|
|
|
|
"SGPRS: %d\n"
|
|
|
|
"VGPRS: %d\n"
|
|
|
|
"Spilled SGPRs: %d\n"
|
|
|
|
"Spilled VGPRs: %d\n"
|
2018-03-01 21:12:56 +00:00
|
|
|
"PrivMem VGPRS: %d\n"
|
2017-10-27 14:25:05 +01:00
|
|
|
"Code Size: %d bytes\n"
|
|
|
|
"LDS: %d blocks\n"
|
|
|
|
"Scratch: %d bytes per wave\n"
|
|
|
|
"Max Waves: %d\n"
|
|
|
|
"********************\n\n\n",
|
|
|
|
conf->num_sgprs, conf->num_vgprs,
|
2018-03-01 21:12:56 +00:00
|
|
|
conf->spilled_sgprs, conf->spilled_vgprs,
|
2019-08-29 16:15:46 +01:00
|
|
|
variant->info.private_mem_vgprs, variant->exec_size,
|
2017-10-27 14:25:05 +01:00
|
|
|
conf->lds_size, conf->scratch_bytes_per_wave,
|
|
|
|
max_simd_waves);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
radv_shader_dump_stats(struct radv_device *device,
|
|
|
|
struct radv_shader_variant *variant,
|
|
|
|
gl_shader_stage stage,
|
|
|
|
FILE *file)
|
|
|
|
{
|
|
|
|
struct _mesa_string_buffer *buf = _mesa_string_buffer_create(NULL, 256);
|
|
|
|
|
|
|
|
generate_shader_stats(device, variant, stage, buf);
|
|
|
|
|
2019-07-11 17:03:55 +01:00
|
|
|
fprintf(file, "\n%s:\n", radv_get_shader_name(&variant->info, stage));
|
2017-10-30 08:38:14 +00:00
|
|
|
fprintf(file, "%s", buf->buf);
|
2017-09-05 14:34:07 +01:00
|
|
|
|
2017-10-27 14:25:05 +01:00
|
|
|
_mesa_string_buffer_destroy(buf);
|
|
|
|
}
|
|
|
|
|
|
|
|
VkResult
|
|
|
|
radv_GetShaderInfoAMD(VkDevice _device,
|
|
|
|
VkPipeline _pipeline,
|
|
|
|
VkShaderStageFlagBits shaderStage,
|
|
|
|
VkShaderInfoTypeAMD infoType,
|
|
|
|
size_t* pInfoSize,
|
|
|
|
void* pInfo)
|
|
|
|
{
|
|
|
|
RADV_FROM_HANDLE(radv_device, device, _device);
|
|
|
|
RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
|
|
|
|
gl_shader_stage stage = vk_to_mesa_shader_stage(shaderStage);
|
|
|
|
struct radv_shader_variant *variant = pipeline->shaders[stage];
|
|
|
|
struct _mesa_string_buffer *buf;
|
|
|
|
VkResult result = VK_SUCCESS;
|
|
|
|
|
|
|
|
/* Spec doesn't indicate what to do if the stage is invalid, so just
|
|
|
|
* return no info for this. */
|
|
|
|
if (!variant)
|
2018-05-31 00:06:41 +01:00
|
|
|
return vk_error(device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
|
2017-10-27 14:25:05 +01:00
|
|
|
|
|
|
|
switch (infoType) {
|
|
|
|
case VK_SHADER_INFO_TYPE_STATISTICS_AMD:
|
|
|
|
if (!pInfo) {
|
|
|
|
*pInfoSize = sizeof(VkShaderStatisticsInfoAMD);
|
|
|
|
} else {
|
2019-05-15 03:16:20 +01:00
|
|
|
unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
|
2017-10-27 14:25:05 +01:00
|
|
|
struct ac_shader_config *conf = &variant->config;
|
|
|
|
|
|
|
|
VkShaderStatisticsInfoAMD statistics = {};
|
|
|
|
statistics.shaderStageMask = shaderStage;
|
2018-04-06 13:10:34 +01:00
|
|
|
statistics.numPhysicalVgprs = RADV_NUM_PHYSICAL_VGPRS;
|
2019-09-13 00:46:02 +01:00
|
|
|
statistics.numPhysicalSgprs = device->physical_device->rad_info.num_physical_sgprs_per_simd;
|
2017-10-27 14:25:05 +01:00
|
|
|
statistics.numAvailableSgprs = statistics.numPhysicalSgprs;
|
|
|
|
|
|
|
|
if (stage == MESA_SHADER_COMPUTE) {
|
2019-06-01 19:25:47 +01:00
|
|
|
unsigned *local_size = variant->info.cs.block_size;
|
2017-10-27 14:25:05 +01:00
|
|
|
unsigned workgroup_size = local_size[0] * local_size[1] * local_size[2];
|
|
|
|
|
|
|
|
statistics.numAvailableVgprs = statistics.numPhysicalVgprs /
|
2018-06-15 17:49:08 +01:00
|
|
|
ceil((double)workgroup_size / statistics.numPhysicalVgprs);
|
2017-10-27 14:25:05 +01:00
|
|
|
|
|
|
|
statistics.computeWorkGroupSize[0] = local_size[0];
|
|
|
|
statistics.computeWorkGroupSize[1] = local_size[1];
|
|
|
|
statistics.computeWorkGroupSize[2] = local_size[2];
|
|
|
|
} else {
|
|
|
|
statistics.numAvailableVgprs = statistics.numPhysicalVgprs;
|
|
|
|
}
|
|
|
|
|
|
|
|
statistics.resourceUsage.numUsedVgprs = conf->num_vgprs;
|
|
|
|
statistics.resourceUsage.numUsedSgprs = conf->num_sgprs;
|
|
|
|
statistics.resourceUsage.ldsSizePerLocalWorkGroup = 32768;
|
|
|
|
statistics.resourceUsage.ldsUsageSizeInBytes = conf->lds_size * lds_multiplier;
|
|
|
|
statistics.resourceUsage.scratchMemUsageInBytes = conf->scratch_bytes_per_wave;
|
|
|
|
|
|
|
|
size_t size = *pInfoSize;
|
|
|
|
*pInfoSize = sizeof(statistics);
|
|
|
|
|
|
|
|
memcpy(pInfo, &statistics, MIN2(size, *pInfoSize));
|
|
|
|
|
|
|
|
if (size < *pInfoSize)
|
|
|
|
result = VK_INCOMPLETE;
|
|
|
|
}
|
|
|
|
|
|
|
|
break;
|
|
|
|
case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD:
|
|
|
|
buf = _mesa_string_buffer_create(NULL, 1024);
|
|
|
|
|
2019-07-11 17:03:55 +01:00
|
|
|
_mesa_string_buffer_printf(buf, "%s:\n", radv_get_shader_name(&variant->info, stage));
|
2019-09-25 11:48:04 +01:00
|
|
|
_mesa_string_buffer_printf(buf, "%s\n\n", variant->ir_string);
|
2017-10-27 14:25:05 +01:00
|
|
|
_mesa_string_buffer_printf(buf, "%s\n\n", variant->disasm_string);
|
|
|
|
generate_shader_stats(device, variant, stage, buf);
|
|
|
|
|
|
|
|
/* Need to include the null terminator. */
|
|
|
|
size_t length = buf->length + 1;
|
|
|
|
|
|
|
|
if (!pInfo) {
|
|
|
|
*pInfoSize = length;
|
|
|
|
} else {
|
|
|
|
size_t size = *pInfoSize;
|
|
|
|
*pInfoSize = length;
|
|
|
|
|
|
|
|
memcpy(pInfo, buf->buf, MIN2(size, length));
|
|
|
|
|
|
|
|
if (size < length)
|
|
|
|
result = VK_INCOMPLETE;
|
|
|
|
}
|
|
|
|
|
|
|
|
_mesa_string_buffer_destroy(buf);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
/* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
|
|
|
|
result = VK_ERROR_FEATURE_NOT_PRESENT;
|
|
|
|
break;
|
2017-09-05 14:34:07 +01:00
|
|
|
}
|
|
|
|
|
2017-10-27 14:25:05 +01:00
|
|
|
return result;
|
2017-09-05 14:34:07 +01:00
|
|
|
}
|