radv: drop tess offchip layout for tcs.
This removes the last TCS specific user sgpr. Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Dave Airlie
parent
ee31cff856
commit
010d055aae
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@ -106,6 +106,7 @@ struct radv_shader_context {
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uint64_t tcs_outputs_read;
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uint32_t tcs_vertices_per_patch;
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uint32_t tcs_num_inputs;
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uint32_t tcs_num_patches;
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};
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enum radeon_llvm_calling_convention {
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@ -136,6 +137,46 @@ static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
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}
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}
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static unsigned
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get_tcs_num_patches(struct radv_shader_context *ctx)
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{
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unsigned num_tcs_input_cp = ctx->options->key.tcs.input_vertices;
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unsigned num_tcs_output_cp = ctx->tcs_vertices_per_patch;
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uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
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uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
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uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
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uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
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uint32_t output_vertex_size = num_tcs_outputs * 16;
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uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
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uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
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unsigned num_patches;
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unsigned hardware_lds_size;
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/* Ensure that we only need one wave per SIMD so we don't need to check
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* resource usage. Also ensures that the number of tcs in and out
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* vertices per threadgroup are at most 256.
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*/
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num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
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/* Make sure that the data fits in LDS. This assumes the shaders only
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* use LDS for the inputs and outputs.
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*/
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hardware_lds_size = ctx->options->chip_class >= CIK ? 65536 : 32768;
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num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
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/* Make sure the output data fits in the offchip buffer */
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num_patches = MIN2(num_patches, (ctx->options->tess_offchip_block_dw_size * 4) / output_patch_size);
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/* Not necessary for correctness, but improves performance. The
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* specific value is taken from the proprietary driver.
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*/
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num_patches = MIN2(num_patches, 40);
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/* SI bug workaround - limit LS-HS threadgroups to only one wave. */
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if (ctx->options->chip_class == SI) {
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unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
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num_patches = MIN2(num_patches, one_wave);
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}
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return num_patches;
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}
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/* Tessellation shaders pass outputs to the next shader using LDS.
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*
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* LS outputs = TCS inputs
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@ -195,17 +236,17 @@ get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
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uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
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uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
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uint32_t output_patch0_offset = input_patch_size;
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LLVMValueRef num_patches = ac_unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
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unsigned num_patches = ctx->tcs_num_patches;
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output_patch0_offset *= num_patches;
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output_patch0_offset /= 4;
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return LLVMBuildMul(ctx->ac.builder,
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num_patches,
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LLVMConstInt(ctx->ac.i32, output_patch0_offset, false), "");
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return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
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}
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static LLVMValueRef
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get_tcs_out_patch0_patch_data_offset(struct radv_shader_context *ctx)
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{
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assert (ctx->stage == MESA_SHADER_TESS_CTRL);
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uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
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uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
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uint32_t output_patch0_offset = input_patch_size;
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@ -213,15 +254,12 @@ get_tcs_out_patch0_patch_data_offset(struct radv_shader_context *ctx)
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uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
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uint32_t output_vertex_size = num_tcs_outputs * 16;
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uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
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LLVMValueRef num_patches = ac_unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
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unsigned num_patches = ctx->tcs_num_patches;
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output_patch0_offset *= num_patches;
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output_patch0_offset += pervertex_output_patch_size;
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output_patch0_offset /= 4;
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LLVMValueRef value = LLVMBuildMul(ctx->ac.builder,
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num_patches,
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LLVMConstInt(ctx->ac.i32, output_patch0_offset, false), "");
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return LLVMBuildAdd(ctx->ac.builder,
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value,
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LLVMConstInt(ctx->ac.i32, pervertex_output_patch_size / 4, false), "");
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return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
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}
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static LLVMValueRef
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@ -493,7 +531,6 @@ static void allocate_user_sgprs(struct radv_shader_context *ctx,
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if (previous_stage == MESA_SHADER_VERTEX)
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user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
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}
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user_sgpr_info->sgpr_count += 1;
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break;
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case MESA_SHADER_TESS_EVAL:
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user_sgpr_info->sgpr_count += 1;
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@ -789,8 +826,6 @@ static void create_function(struct radv_shader_context *ctx,
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has_previous_stage,
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previous_stage, &args);
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add_arg(&args, ARG_SGPR, ctx->ac.i32,
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&ctx->tcs_offchip_layout);
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if (needs_view_index)
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add_arg(&args, ARG_SGPR, ctx->ac.i32,
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&ctx->abi.view_index);
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@ -808,8 +843,6 @@ static void create_function(struct radv_shader_context *ctx,
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&user_sgpr_info, &args,
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&desc_sets);
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add_arg(&args, ARG_SGPR, ctx->ac.i32,
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&ctx->tcs_offchip_layout);
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if (needs_view_index)
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add_arg(&args, ARG_SGPR, ctx->ac.i32,
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&ctx->abi.view_index);
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@ -1018,7 +1051,6 @@ static void create_function(struct radv_shader_context *ctx,
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case MESA_SHADER_TESS_CTRL:
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set_vs_specific_input_locs(ctx, stage, has_previous_stage,
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previous_stage, &user_sgpr_idx);
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set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
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if (ctx->abi.view_index)
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set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
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break;
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@ -1115,30 +1147,58 @@ radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
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*
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* Note that every attribute has 4 components.
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*/
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static LLVMValueRef get_non_vertex_index_offset(struct radv_shader_context *ctx)
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{
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if (ctx->stage == MESA_SHADER_TESS_CTRL) {
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uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
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uint32_t output_vertex_size = num_tcs_outputs * 16;
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uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * output_vertex_size;
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uint32_t num_patches = ctx->tcs_num_patches;
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return LLVMConstInt(ctx->ac.i32, pervertex_output_patch_size * num_patches, false);
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} else
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return ac_unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
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}
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static LLVMValueRef calc_param_stride(struct radv_shader_context *ctx,
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LLVMValueRef vertex_index)
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{
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LLVMValueRef param_stride;
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if (ctx->stage == MESA_SHADER_TESS_CTRL) {
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if (vertex_index)
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param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch * ctx->tcs_num_patches, false);
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else
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param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_num_patches, false);
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} else {
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LLVMValueRef num_patches = ac_unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
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LLVMValueRef vertices_per_patch = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch, false);
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if (vertex_index)
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param_stride = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
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num_patches, "");
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else
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param_stride = num_patches;
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}
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return param_stride;
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}
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static LLVMValueRef get_tcs_tes_buffer_address(struct radv_shader_context *ctx,
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LLVMValueRef vertex_index,
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LLVMValueRef param_index)
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{
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LLVMValueRef base_addr, vertices_per_patch, num_patches;
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LLVMValueRef base_addr;
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LLVMValueRef param_stride, constant16;
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LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
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vertices_per_patch = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch, false);
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num_patches = ac_unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
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LLVMValueRef vertices_per_patch = LLVMConstInt(ctx->ac.i32, ctx->tcs_vertices_per_patch, false);
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constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
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param_stride = calc_param_stride(ctx, vertex_index);
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if (vertex_index) {
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base_addr = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
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vertices_per_patch, "");
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base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
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vertex_index, "");
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param_stride = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
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num_patches, "");
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} else {
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base_addr = rel_patch_id;
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param_stride = num_patches;
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}
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base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
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@ -1148,8 +1208,7 @@ static LLVMValueRef get_tcs_tes_buffer_address(struct radv_shader_context *ctx,
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base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
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if (!vertex_index) {
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LLVMValueRef patch_data_offset =
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ac_unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
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LLVMValueRef patch_data_offset = get_non_vertex_index_offset(ctx);
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base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
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patch_data_offset, "");
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@ -3043,6 +3102,7 @@ LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
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ctx.tcs_num_inputs = ctx.options->key.tcs.num_inputs;
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else
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ctx.tcs_num_inputs = util_last_bit64(shader_info->info.vs.ls_outputs_written);
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ctx.tcs_num_patches = get_tcs_num_patches(&ctx);
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} else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
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ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
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ctx.abi.load_tess_varyings = load_tes_input;
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@ -2604,15 +2604,6 @@ radv_pipeline_generate_tess_shaders(struct radeon_winsys_cs *cs,
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struct radv_userdata_info *loc;
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loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
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if (loc->sgpr_idx != -1) {
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uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_CTRL];
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assert(loc->num_sgprs == 1);
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assert(!loc->indirect);
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radeon_set_sh_reg_seq(cs, base_reg + loc->sgpr_idx * 4, 1);
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radeon_emit(cs, tess->offchip_layout);
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}
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loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
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if (loc->sgpr_idx != -1) {
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uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_EVAL];
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@ -463,6 +463,7 @@ shader_variant_create(struct radv_device *device,
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options->dump_preoptir = options->dump_shader &&
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device->instance->debug_flags & RADV_DEBUG_PREOPTIR;
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options->record_llvm_ir = device->keep_shader_info;
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options->tess_offchip_block_dw_size = device->tess_offchip_block_dw_size;
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if (options->supports_spill)
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tm_options |= AC_TM_SUPPORTS_SPILL;
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@ -103,6 +103,7 @@ struct radv_nir_compiler_options {
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bool record_llvm_ir;
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enum radeon_family family;
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enum chip_class chip_class;
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uint32_t tess_offchip_block_dw_size;
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};
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enum radv_ud_index {
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@ -120,7 +121,6 @@ enum radv_ud_index {
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AC_UD_CS_MAX_UD,
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AC_UD_GS_VS_RING_STRIDE_ENTRIES = AC_UD_VS_MAX_UD,
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AC_UD_GS_MAX_UD,
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AC_UD_TCS_OFFCHIP_LAYOUT = AC_UD_VS_MAX_UD,
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AC_UD_TCS_MAX_UD,
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AC_UD_TES_OFFCHIP_LAYOUT = AC_UD_SHADER_START,
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AC_UD_TES_MAX_UD,
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