2017-09-01 10:41:18 +01:00
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/*
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* Copyright © 2016 Red Hat.
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* Copyright © 2016 Bas Nieuwenhuizen
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*
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* based in part on anv driver which is:
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* Copyright © 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "util/mesa-sha1.h"
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#include "util/u_atomic.h"
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#include "radv_debug.h"
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#include "radv_private.h"
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#include "radv_shader.h"
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#include "nir/nir.h"
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#include "nir/nir_builder.h"
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#include "spirv/nir_spirv.h"
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#include <llvm-c/Core.h>
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#include <llvm-c/TargetMachine.h>
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2018-06-08 10:38:01 +01:00
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#include <llvm-c/Support.h>
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2017-09-01 10:41:18 +01:00
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#include "sid.h"
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#include "gfx9d.h"
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#include "ac_binary.h"
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#include "ac_llvm_util.h"
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#include "ac_nir_to_llvm.h"
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#include "vk_format.h"
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#include "util/debug.h"
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#include "ac_exp_param.h"
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2017-10-27 14:25:05 +01:00
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#include "util/string_buffer.h"
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2017-09-01 10:41:18 +01:00
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static const struct nir_shader_compiler_options nir_options = {
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.vertex_id_zero_based = true,
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.lower_scmp = true,
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.lower_flrp32 = true,
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2018-01-12 00:12:09 +00:00
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.lower_flrp64 = true,
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2018-01-21 16:13:26 +00:00
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.lower_device_index_to_zero = true,
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2017-09-01 10:41:18 +01:00
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.lower_fsat = true,
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.lower_fdiv = true,
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.lower_sub = true,
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.lower_pack_snorm_2x16 = true,
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.lower_pack_snorm_4x8 = true,
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.lower_pack_unorm_2x16 = true,
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.lower_pack_unorm_4x8 = true,
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.lower_unpack_snorm_2x16 = true,
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.lower_unpack_snorm_4x8 = true,
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.lower_unpack_unorm_2x16 = true,
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.lower_unpack_unorm_4x8 = true,
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.lower_extract_byte = true,
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.lower_extract_word = true,
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2017-10-03 21:33:02 +01:00
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.lower_ffma = true,
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2018-02-02 18:04:57 +00:00
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.lower_fpow = true,
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2018-01-07 23:37:27 +00:00
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.vs_inputs_dual_locations = true,
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2017-09-01 10:41:18 +01:00
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.max_unroll_iterations = 32
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};
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VkResult radv_CreateShaderModule(
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VkDevice _device,
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const VkShaderModuleCreateInfo* pCreateInfo,
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const VkAllocationCallbacks* pAllocator,
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VkShaderModule* pShaderModule)
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{
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RADV_FROM_HANDLE(radv_device, device, _device);
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struct radv_shader_module *module;
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assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
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assert(pCreateInfo->flags == 0);
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module = vk_alloc2(&device->alloc, pAllocator,
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sizeof(*module) + pCreateInfo->codeSize, 8,
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VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
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if (module == NULL)
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2018-05-31 00:06:41 +01:00
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return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
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2017-09-01 10:41:18 +01:00
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module->nir = NULL;
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module->size = pCreateInfo->codeSize;
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memcpy(module->data, pCreateInfo->pCode, module->size);
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_mesa_sha1_compute(module->data, module->size, module->sha1);
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*pShaderModule = radv_shader_module_to_handle(module);
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return VK_SUCCESS;
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}
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void radv_DestroyShaderModule(
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VkDevice _device,
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VkShaderModule _module,
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const VkAllocationCallbacks* pAllocator)
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{
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RADV_FROM_HANDLE(radv_device, device, _device);
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RADV_FROM_HANDLE(radv_shader_module, module, _module);
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if (!module)
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return;
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vk_free2(&device->alloc, pAllocator, module);
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}
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2017-02-08 23:12:10 +00:00
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void
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2018-05-08 05:57:55 +01:00
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radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively)
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2017-09-01 10:41:18 +01:00
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{
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bool progress;
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do {
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progress = false;
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NIR_PASS_V(shader, nir_lower_vars_to_ssa);
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2018-04-27 08:28:48 +01:00
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NIR_PASS_V(shader, nir_lower_pack);
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2017-09-01 10:41:18 +01:00
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NIR_PASS_V(shader, nir_lower_alu_to_scalar);
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NIR_PASS_V(shader, nir_lower_phis_to_scalar);
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NIR_PASS(progress, shader, nir_copy_prop);
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NIR_PASS(progress, shader, nir_opt_remove_phis);
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NIR_PASS(progress, shader, nir_opt_dce);
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if (nir_opt_trivial_continues(shader)) {
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progress = true;
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NIR_PASS(progress, shader, nir_copy_prop);
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2017-09-13 03:49:31 +01:00
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NIR_PASS(progress, shader, nir_opt_remove_phis);
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2017-09-01 10:41:18 +01:00
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NIR_PASS(progress, shader, nir_opt_dce);
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}
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NIR_PASS(progress, shader, nir_opt_if);
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NIR_PASS(progress, shader, nir_opt_dead_cf);
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NIR_PASS(progress, shader, nir_opt_cse);
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NIR_PASS(progress, shader, nir_opt_peephole_select, 8);
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NIR_PASS(progress, shader, nir_opt_algebraic);
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NIR_PASS(progress, shader, nir_opt_constant_folding);
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NIR_PASS(progress, shader, nir_opt_undef);
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NIR_PASS(progress, shader, nir_opt_conditional_discard);
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if (shader->options->max_unroll_iterations) {
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NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
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}
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2018-05-08 05:57:55 +01:00
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} while (progress && !optimize_conservatively);
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2018-01-29 16:19:18 +00:00
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NIR_PASS(progress, shader, nir_opt_shrink_load);
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2018-03-08 14:31:14 +00:00
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NIR_PASS(progress, shader, nir_opt_move_load_ubo);
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2017-09-01 10:41:18 +01:00
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}
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nir_shader *
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radv_shader_compile_to_nir(struct radv_device *device,
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struct radv_shader_module *module,
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const char *entrypoint_name,
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gl_shader_stage stage,
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2018-05-08 05:57:55 +01:00
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const VkSpecializationInfo *spec_info,
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const VkPipelineCreateFlags flags)
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2017-09-01 10:41:18 +01:00
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{
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nir_shader *nir;
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nir_function *entry_point;
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if (module->nir) {
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/* Some things such as our meta clear/blit code will give us a NIR
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* shader directly. In that case, we just ignore the SPIR-V entirely
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* and just use the NIR shader */
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nir = module->nir;
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nir->options = &nir_options;
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nir_validate_shader(nir);
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assert(exec_list_length(&nir->functions) == 1);
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struct exec_node *node = exec_list_get_head(&nir->functions);
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entry_point = exec_node_data(nir_function, node, node);
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} else {
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uint32_t *spirv = (uint32_t *) module->data;
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assert(module->size % 4 == 0);
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2017-10-11 01:59:20 +01:00
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if (device->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV)
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2017-09-22 15:56:40 +01:00
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radv_print_spirv(spirv, module->size, stderr);
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2017-09-01 10:41:18 +01:00
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uint32_t num_spec_entries = 0;
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struct nir_spirv_specialization *spec_entries = NULL;
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if (spec_info && spec_info->mapEntryCount > 0) {
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num_spec_entries = spec_info->mapEntryCount;
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spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
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for (uint32_t i = 0; i < num_spec_entries; i++) {
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VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
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const void *data = spec_info->pData + entry.offset;
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assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
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spec_entries[i].id = spec_info->pMapEntries[i].constantID;
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if (spec_info->dataSize == 8)
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spec_entries[i].data64 = *(const uint64_t *)data;
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else
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spec_entries[i].data32 = *(const uint32_t *)data;
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}
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}
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2017-10-19 01:28:19 +01:00
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const struct spirv_to_nir_options spirv_options = {
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.caps = {
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2018-01-21 16:13:26 +00:00
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.device_group = true,
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2017-10-19 01:28:19 +01:00
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.draw_parameters = true,
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.float64 = true,
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.image_read_without_format = true,
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.image_write_without_format = true,
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.tessellation = true,
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.int64 = true,
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.multiview = true,
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2018-03-06 14:05:13 +00:00
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.subgroup_ballot = true,
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2018-01-21 14:06:10 +00:00
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.subgroup_basic = true,
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2018-03-06 14:05:13 +00:00
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.subgroup_quad = true,
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.subgroup_shuffle = true,
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.subgroup_vote = true,
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2017-10-19 01:28:19 +01:00
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.variable_pointers = true,
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2018-03-08 11:43:00 +00:00
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.gcn_shader = true,
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2018-03-08 22:13:43 +00:00
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.trinary_minmax = true,
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2018-04-02 17:17:55 +01:00
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.shader_viewport_index_layer = true,
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2018-04-11 18:08:30 +01:00
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.descriptor_array_dynamic_indexing = true,
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.runtime_descriptor_array = true,
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2018-02-23 12:55:01 +00:00
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},
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2017-09-01 10:41:18 +01:00
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};
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entry_point = spirv_to_nir(spirv, module->size / 4,
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spec_entries, num_spec_entries,
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2017-10-19 01:28:19 +01:00
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stage, entrypoint_name,
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&spirv_options, &nir_options);
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2017-09-01 10:41:18 +01:00
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nir = entry_point->shader;
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2017-09-15 03:52:38 +01:00
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assert(nir->info.stage == stage);
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2017-09-01 10:41:18 +01:00
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nir_validate_shader(nir);
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free(spec_entries);
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/* We have to lower away local constant initializers right before we
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* inline functions. That way they get properly initialized at the top
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* of the function and not at the top of its caller.
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*/
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NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local);
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NIR_PASS_V(nir, nir_lower_returns);
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NIR_PASS_V(nir, nir_inline_functions);
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/* Pick off the single entrypoint that we want */
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foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
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if (func != entry_point)
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exec_node_remove(&func->node);
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}
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assert(exec_list_length(&nir->functions) == 1);
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entry_point->name = ralloc_strdup(entry_point, "main");
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2018-03-19 04:27:49 +00:00
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/* Make sure we lower constant initializers on output variables so that
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* nir_remove_dead_variables below sees the corresponding stores
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*/
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NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_shader_out);
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2017-09-01 10:41:18 +01:00
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NIR_PASS_V(nir, nir_remove_dead_variables,
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nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
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/* Now that we've deleted all but the main function, we can go ahead and
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* lower the rest of the constant initializers.
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*/
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NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
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NIR_PASS_V(nir, nir_lower_system_values);
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NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
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}
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/* Vulkan uses the separate-shader linking model */
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nir->info.separate_shader = true;
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nir_shader_gather_info(nir, entry_point->impl);
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static const nir_lower_tex_options tex_options = {
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.lower_txp = ~0,
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};
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nir_lower_tex(nir, &tex_options);
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nir_lower_vars_to_ssa(nir);
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2018-05-23 13:31:55 +01:00
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2018-05-23 13:31:56 +01:00
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if (nir->info.stage == MESA_SHADER_VERTEX ||
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nir->info.stage == MESA_SHADER_GEOMETRY) {
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NIR_PASS_V(nir, nir_lower_io_to_temporaries,
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nir_shader_get_entrypoint(nir), true, true);
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} else if (nir->info.stage == MESA_SHADER_TESS_EVAL||
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nir->info.stage == MESA_SHADER_FRAGMENT) {
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NIR_PASS_V(nir, nir_lower_io_to_temporaries,
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nir_shader_get_entrypoint(nir), true, false);
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}
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2018-05-23 13:31:55 +01:00
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nir_split_var_copies(nir);
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2017-09-01 10:41:18 +01:00
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nir_lower_var_copies(nir);
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2018-05-23 13:31:55 +01:00
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2017-09-01 10:41:18 +01:00
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nir_lower_global_vars_to_local(nir);
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nir_remove_dead_variables(nir, nir_var_local);
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2018-01-21 14:06:10 +00:00
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nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) {
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.subgroup_size = 64,
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.ballot_bit_size = 64,
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.lower_to_scalar = 1,
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|
|
.lower_subgroup_masks = 1,
|
|
|
|
.lower_shuffle = 1,
|
2018-03-06 14:05:13 +00:00
|
|
|
.lower_shuffle_to_32bit = 1,
|
|
|
|
.lower_vote_eq_to_ballot = 1,
|
2018-01-21 14:06:10 +00:00
|
|
|
});
|
|
|
|
|
2018-05-08 05:57:55 +01:00
|
|
|
if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
|
|
|
|
radv_optimize_nir(nir, false);
|
2017-09-01 10:41:18 +01:00
|
|
|
|
2018-03-08 05:20:48 +00:00
|
|
|
/* Indirect lowering must be called after the radv_optimize_nir() loop
|
|
|
|
* has been called at least once. Otherwise indirect lowering can
|
|
|
|
* bloat the instruction count of the loop and cause it to be
|
|
|
|
* considered too large for unrolling.
|
|
|
|
*/
|
|
|
|
ac_lower_indirect_derefs(nir, device->physical_device->rad_info.chip_class);
|
2018-05-08 05:57:55 +01:00
|
|
|
radv_optimize_nir(nir, flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT);
|
2018-03-08 05:20:48 +00:00
|
|
|
|
2017-09-01 10:41:18 +01:00
|
|
|
return nir;
|
|
|
|
}
|
|
|
|
|
|
|
|
void *
|
|
|
|
radv_alloc_shader_memory(struct radv_device *device,
|
|
|
|
struct radv_shader_variant *shader)
|
|
|
|
{
|
|
|
|
mtx_lock(&device->shader_slab_mutex);
|
|
|
|
list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
|
|
|
|
uint64_t offset = 0;
|
|
|
|
list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) {
|
|
|
|
if (s->bo_offset - offset >= shader->code_size) {
|
|
|
|
shader->bo = slab->bo;
|
|
|
|
shader->bo_offset = offset;
|
|
|
|
list_addtail(&shader->slab_list, &s->slab_list);
|
|
|
|
mtx_unlock(&device->shader_slab_mutex);
|
|
|
|
return slab->ptr + offset;
|
|
|
|
}
|
|
|
|
offset = align_u64(s->bo_offset + s->code_size, 256);
|
|
|
|
}
|
|
|
|
if (slab->size - offset >= shader->code_size) {
|
|
|
|
shader->bo = slab->bo;
|
|
|
|
shader->bo_offset = offset;
|
|
|
|
list_addtail(&shader->slab_list, &slab->shaders);
|
|
|
|
mtx_unlock(&device->shader_slab_mutex);
|
|
|
|
return slab->ptr + offset;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
mtx_unlock(&device->shader_slab_mutex);
|
|
|
|
struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab));
|
|
|
|
|
|
|
|
slab->size = 256 * 1024;
|
|
|
|
slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
|
2018-01-04 14:19:47 +00:00
|
|
|
RADEON_DOMAIN_VRAM,
|
|
|
|
RADEON_FLAG_NO_INTERPROCESS_SHARING |
|
|
|
|
device->physical_device->cpdma_prefetch_writes_memory ?
|
|
|
|
0 : RADEON_FLAG_READ_ONLY);
|
2017-09-01 10:41:18 +01:00
|
|
|
slab->ptr = (char*)device->ws->buffer_map(slab->bo);
|
|
|
|
list_inithead(&slab->shaders);
|
|
|
|
|
|
|
|
mtx_lock(&device->shader_slab_mutex);
|
|
|
|
list_add(&slab->slabs, &device->shader_slabs);
|
|
|
|
|
|
|
|
shader->bo = slab->bo;
|
|
|
|
shader->bo_offset = 0;
|
|
|
|
list_add(&shader->slab_list, &slab->shaders);
|
|
|
|
mtx_unlock(&device->shader_slab_mutex);
|
|
|
|
return slab->ptr;
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
radv_destroy_shader_slabs(struct radv_device *device)
|
|
|
|
{
|
|
|
|
list_for_each_entry_safe(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
|
|
|
|
device->ws->buffer_destroy(slab->bo);
|
|
|
|
free(slab);
|
|
|
|
}
|
|
|
|
mtx_destroy(&device->shader_slab_mutex);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
radv_fill_shader_variant(struct radv_device *device,
|
|
|
|
struct radv_shader_variant *variant,
|
|
|
|
struct ac_shader_binary *binary,
|
|
|
|
gl_shader_stage stage)
|
|
|
|
{
|
|
|
|
bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
|
2018-05-11 08:46:46 +01:00
|
|
|
struct radv_shader_info *info = &variant->info.info;
|
2017-09-01 10:41:18 +01:00
|
|
|
unsigned vgpr_comp_cnt = 0;
|
|
|
|
|
|
|
|
variant->code_size = binary->code_size;
|
|
|
|
variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
|
2018-05-11 08:46:46 +01:00
|
|
|
S_00B12C_SCRATCH_EN(scratch_enabled);
|
2017-09-01 10:41:18 +01:00
|
|
|
|
2018-05-11 08:46:46 +01:00
|
|
|
variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
|
2017-10-17 23:59:16 +01:00
|
|
|
S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
|
|
|
|
S_00B848_DX10_CLAMP(1) |
|
|
|
|
S_00B848_FLOAT_MODE(variant->config.float_mode);
|
|
|
|
|
2017-09-01 10:41:18 +01:00
|
|
|
switch (stage) {
|
|
|
|
case MESA_SHADER_TESS_EVAL:
|
|
|
|
vgpr_comp_cnt = 3;
|
2017-10-17 23:59:16 +01:00
|
|
|
variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
|
|
|
|
break;
|
2017-09-01 10:41:18 +01:00
|
|
|
case MESA_SHADER_TESS_CTRL:
|
2018-05-11 08:46:46 +01:00
|
|
|
if (device->physical_device->rad_info.chip_class >= GFX9) {
|
2017-10-17 23:59:16 +01:00
|
|
|
vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
|
2018-05-11 08:46:46 +01:00
|
|
|
} else {
|
2017-10-17 23:59:16 +01:00
|
|
|
variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
|
2018-05-11 08:46:46 +01:00
|
|
|
}
|
2017-09-01 10:41:18 +01:00
|
|
|
break;
|
|
|
|
case MESA_SHADER_VERTEX:
|
|
|
|
case MESA_SHADER_GEOMETRY:
|
|
|
|
vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
|
|
|
|
break;
|
|
|
|
case MESA_SHADER_FRAGMENT:
|
|
|
|
break;
|
2018-05-11 08:46:46 +01:00
|
|
|
case MESA_SHADER_COMPUTE:
|
2017-09-01 10:41:18 +01:00
|
|
|
variant->rsrc2 |=
|
2017-12-18 21:06:38 +00:00
|
|
|
S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) |
|
|
|
|
S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) |
|
|
|
|
S_00B84C_TGID_Z_EN(info->cs.uses_block_id[2]) |
|
|
|
|
S_00B84C_TIDIG_COMP_CNT(info->cs.uses_thread_id[2] ? 2 :
|
|
|
|
info->cs.uses_thread_id[1] ? 1 : 0) |
|
2017-12-14 16:32:41 +00:00
|
|
|
S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx) |
|
2017-09-01 10:41:18 +01:00
|
|
|
S_00B84C_LDS_SIZE(variant->config.lds_size);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
unreachable("unsupported shader type");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2017-10-17 23:59:16 +01:00
|
|
|
if (device->physical_device->rad_info.chip_class >= GFX9 &&
|
2017-10-20 01:24:24 +01:00
|
|
|
stage == MESA_SHADER_GEOMETRY) {
|
2018-01-09 15:01:09 +00:00
|
|
|
unsigned es_type = variant->info.gs.es_type;
|
2018-01-09 15:01:10 +00:00
|
|
|
unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
|
|
|
|
|
|
|
|
if (es_type == MESA_SHADER_VERTEX) {
|
|
|
|
es_vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
|
|
|
|
} else if (es_type == MESA_SHADER_TESS_EVAL) {
|
|
|
|
es_vgpr_comp_cnt = 3;
|
|
|
|
} else {
|
2018-01-17 22:23:02 +00:00
|
|
|
unreachable("invalid shader ES type");
|
2018-01-09 15:01:10 +00:00
|
|
|
}
|
2017-12-20 19:56:57 +00:00
|
|
|
|
|
|
|
/* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
|
|
|
|
* VGPR[0:4] are always loaded.
|
|
|
|
*/
|
2018-05-11 08:46:46 +01:00
|
|
|
if (info->uses_invocation_id) {
|
2017-12-20 19:56:57 +00:00
|
|
|
gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
|
2018-05-11 08:46:46 +01:00
|
|
|
} else if (info->uses_prim_id) {
|
2017-12-20 19:56:57 +00:00
|
|
|
gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
|
2018-05-11 08:46:46 +01:00
|
|
|
} else if (variant->info.gs.vertices_in >= 3) {
|
2018-01-05 16:18:52 +00:00
|
|
|
gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
|
2018-05-11 08:46:46 +01:00
|
|
|
} else {
|
2018-01-05 16:18:52 +00:00
|
|
|
gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
|
2018-05-11 08:46:46 +01:00
|
|
|
}
|
2017-12-20 19:56:57 +00:00
|
|
|
|
|
|
|
variant->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
|
2018-01-09 15:01:10 +00:00
|
|
|
variant->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
|
2018-01-09 15:01:09 +00:00
|
|
|
S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL);
|
2017-10-20 01:24:24 +01:00
|
|
|
} else if (device->physical_device->rad_info.chip_class >= GFX9 &&
|
2018-05-11 08:46:46 +01:00
|
|
|
stage == MESA_SHADER_TESS_CTRL) {
|
2017-10-17 23:59:16 +01:00
|
|
|
variant->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
|
2018-05-11 08:46:46 +01:00
|
|
|
} else {
|
2017-10-17 23:59:16 +01:00
|
|
|
variant->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt);
|
2018-05-11 08:46:46 +01:00
|
|
|
}
|
2017-09-01 10:41:18 +01:00
|
|
|
|
|
|
|
void *ptr = radv_alloc_shader_memory(device, variant);
|
|
|
|
memcpy(ptr, binary->code, binary->code_size);
|
|
|
|
}
|
|
|
|
|
2018-06-08 10:38:01 +01:00
|
|
|
static void radv_init_llvm_target()
|
|
|
|
{
|
|
|
|
LLVMInitializeAMDGPUTargetInfo();
|
|
|
|
LLVMInitializeAMDGPUTarget();
|
|
|
|
LLVMInitializeAMDGPUTargetMC();
|
|
|
|
LLVMInitializeAMDGPUAsmPrinter();
|
|
|
|
|
|
|
|
/* For inline assembly. */
|
|
|
|
LLVMInitializeAMDGPUAsmParser();
|
|
|
|
|
|
|
|
/* Workaround for bug in llvm 4.0 that causes image intrinsics
|
|
|
|
* to disappear.
|
|
|
|
* https://reviews.llvm.org/D26348
|
|
|
|
*
|
|
|
|
* Workaround for bug in llvm that causes the GPU to hang in presence
|
|
|
|
* of nested loops because there is an exec mask issue. The proper
|
|
|
|
* solution is to fix LLVM but this might require a bunch of work.
|
|
|
|
* https://bugs.llvm.org/show_bug.cgi?id=37744
|
|
|
|
*
|
|
|
|
* "mesa" is the prefix for error messages.
|
|
|
|
*/
|
|
|
|
const char *argv[3] = { "mesa", "-simplifycfg-sink-common=false",
|
|
|
|
"-amdgpu-skip-threshold=1" };
|
|
|
|
LLVMParseCommandLineOptions(3, argv, NULL);
|
|
|
|
}
|
|
|
|
|
|
|
|
static once_flag radv_init_llvm_target_once_flag = ONCE_FLAG_INIT;
|
|
|
|
|
|
|
|
static LLVMTargetRef radv_get_llvm_target(const char *triple)
|
|
|
|
{
|
|
|
|
LLVMTargetRef target = NULL;
|
|
|
|
char *err_message = NULL;
|
|
|
|
|
|
|
|
call_once(&radv_init_llvm_target_once_flag, radv_init_llvm_target);
|
|
|
|
|
|
|
|
if (LLVMGetTargetFromTriple(triple, &target, &err_message)) {
|
|
|
|
fprintf(stderr, "Cannot find target for triple %s ", triple);
|
|
|
|
if (err_message) {
|
|
|
|
fprintf(stderr, "%s\n", err_message);
|
|
|
|
}
|
|
|
|
LLVMDisposeMessage(err_message);
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
return target;
|
|
|
|
}
|
|
|
|
|
|
|
|
static LLVMTargetMachineRef radv_create_target_machine(enum radeon_family family,
|
|
|
|
enum ac_target_machine_options tm_options,
|
|
|
|
const char **out_triple)
|
|
|
|
{
|
|
|
|
assert(family >= CHIP_TAHITI);
|
|
|
|
char features[256];
|
|
|
|
const char *triple = (tm_options & AC_TM_SUPPORTS_SPILL) ? "amdgcn-mesa-mesa3d" : "amdgcn--";
|
|
|
|
LLVMTargetRef target = radv_get_llvm_target(triple);
|
|
|
|
|
|
|
|
snprintf(features, sizeof(features),
|
|
|
|
"+DumpCode,+vgpr-spilling,-fp32-denormals,+fp64-denormals%s%s%s%s",
|
|
|
|
tm_options & AC_TM_SISCHED ? ",+si-scheduler" : "",
|
|
|
|
tm_options & AC_TM_FORCE_ENABLE_XNACK ? ",+xnack" : "",
|
|
|
|
tm_options & AC_TM_FORCE_DISABLE_XNACK ? ",-xnack" : "",
|
|
|
|
tm_options & AC_TM_PROMOTE_ALLOCA_TO_SCRATCH ? ",-promote-alloca" : "");
|
|
|
|
|
|
|
|
LLVMTargetMachineRef tm = LLVMCreateTargetMachine(
|
|
|
|
target,
|
|
|
|
triple,
|
|
|
|
ac_get_llvm_processor_name(family),
|
|
|
|
features,
|
|
|
|
LLVMCodeGenLevelDefault,
|
|
|
|
LLVMRelocDefault,
|
|
|
|
LLVMCodeModelDefault);
|
|
|
|
|
|
|
|
if (out_triple)
|
|
|
|
*out_triple = triple;
|
|
|
|
return tm;
|
|
|
|
}
|
|
|
|
|
2017-09-01 15:51:12 +01:00
|
|
|
static struct radv_shader_variant *
|
|
|
|
shader_variant_create(struct radv_device *device,
|
2017-09-22 15:44:08 +01:00
|
|
|
struct radv_shader_module *module,
|
2017-10-16 12:18:02 +01:00
|
|
|
struct nir_shader * const *shaders,
|
|
|
|
int shader_count,
|
2017-09-01 15:51:12 +01:00
|
|
|
gl_shader_stage stage,
|
2018-03-13 13:54:04 +00:00
|
|
|
struct radv_nir_compiler_options *options,
|
2017-09-01 15:51:12 +01:00
|
|
|
bool gs_copy_shader,
|
|
|
|
void **code_out,
|
|
|
|
unsigned *code_size_out)
|
2017-09-01 10:41:18 +01:00
|
|
|
{
|
|
|
|
enum radeon_family chip_family = device->physical_device->rad_info.family;
|
2017-09-01 15:51:12 +01:00
|
|
|
enum ac_target_machine_options tm_options = 0;
|
|
|
|
struct radv_shader_variant *variant;
|
|
|
|
struct ac_shader_binary binary;
|
2017-09-01 10:41:18 +01:00
|
|
|
LLVMTargetMachineRef tm;
|
2017-09-01 15:51:12 +01:00
|
|
|
|
|
|
|
variant = calloc(1, sizeof(struct radv_shader_variant));
|
2017-09-01 10:41:18 +01:00
|
|
|
if (!variant)
|
|
|
|
return NULL;
|
|
|
|
|
2017-09-01 15:51:12 +01:00
|
|
|
options->family = chip_family;
|
|
|
|
options->chip_class = device->physical_device->rad_info.chip_class;
|
2018-05-11 15:36:02 +01:00
|
|
|
options->dump_shader = radv_can_dump_shader(device, module, gs_copy_shader);
|
2018-03-14 09:28:49 +00:00
|
|
|
options->dump_preoptir = options->dump_shader &&
|
2018-01-19 11:12:02 +00:00
|
|
|
device->instance->debug_flags & RADV_DEBUG_PREOPTIR;
|
2018-03-14 09:34:13 +00:00
|
|
|
options->record_llvm_ir = device->keep_shader_info;
|
2018-02-19 07:14:04 +00:00
|
|
|
options->tess_offchip_block_dw_size = device->tess_offchip_block_dw_size;
|
2018-05-16 15:02:04 +01:00
|
|
|
options->address32_hi = device->physical_device->rad_info.address32_hi;
|
2017-09-01 10:41:18 +01:00
|
|
|
|
2017-09-01 15:51:12 +01:00
|
|
|
if (options->supports_spill)
|
2017-09-01 10:41:18 +01:00
|
|
|
tm_options |= AC_TM_SUPPORTS_SPILL;
|
|
|
|
if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
|
|
|
|
tm_options |= AC_TM_SISCHED;
|
2018-06-08 10:38:01 +01:00
|
|
|
tm = radv_create_target_machine(chip_family, tm_options, NULL);
|
2017-09-01 15:51:12 +01:00
|
|
|
|
|
|
|
if (gs_copy_shader) {
|
2017-10-16 12:18:02 +01:00
|
|
|
assert(shader_count == 1);
|
2018-03-09 15:58:10 +00:00
|
|
|
radv_compile_gs_copy_shader(tm, *shaders, &binary,
|
|
|
|
&variant->config, &variant->info,
|
2018-03-14 09:28:49 +00:00
|
|
|
options);
|
2017-09-01 15:51:12 +01:00
|
|
|
} else {
|
2018-03-09 15:58:10 +00:00
|
|
|
radv_compile_nir_shader(tm, &binary, &variant->config,
|
|
|
|
&variant->info, shaders, shader_count,
|
2018-03-14 09:28:49 +00:00
|
|
|
options);
|
2017-09-01 15:51:12 +01:00
|
|
|
}
|
|
|
|
|
2017-09-01 10:41:18 +01:00
|
|
|
LLVMDisposeTargetMachine(tm);
|
|
|
|
|
2017-09-01 15:51:12 +01:00
|
|
|
radv_fill_shader_variant(device, variant, &binary, stage);
|
2017-09-01 10:41:18 +01:00
|
|
|
|
|
|
|
if (code_out) {
|
|
|
|
*code_out = binary.code;
|
|
|
|
*code_size_out = binary.code_size;
|
|
|
|
} else
|
|
|
|
free(binary.code);
|
|
|
|
free(binary.config);
|
|
|
|
free(binary.rodata);
|
|
|
|
free(binary.global_symbol_offsets);
|
|
|
|
free(binary.relocs);
|
|
|
|
variant->ref_count = 1;
|
2017-09-01 12:45:33 +01:00
|
|
|
|
2017-10-27 14:25:05 +01:00
|
|
|
if (device->keep_shader_info) {
|
2017-09-01 12:45:33 +01:00
|
|
|
variant->disasm_string = binary.disasm_string;
|
2018-03-14 09:34:13 +00:00
|
|
|
variant->llvm_ir_string = binary.llvm_ir_string;
|
2017-09-22 15:44:08 +01:00
|
|
|
if (!gs_copy_shader && !module->nir) {
|
2017-10-16 12:18:02 +01:00
|
|
|
variant->nir = *shaders;
|
2017-09-22 15:56:40 +01:00
|
|
|
variant->spirv = (uint32_t *)module->data;
|
|
|
|
variant->spirv_size = module->size;
|
2017-09-22 15:44:08 +01:00
|
|
|
}
|
2017-09-01 12:45:33 +01:00
|
|
|
} else {
|
|
|
|
free(binary.disasm_string);
|
|
|
|
}
|
|
|
|
|
2017-09-01 10:41:18 +01:00
|
|
|
return variant;
|
|
|
|
}
|
|
|
|
|
|
|
|
struct radv_shader_variant *
|
2017-09-01 15:51:12 +01:00
|
|
|
radv_shader_variant_create(struct radv_device *device,
|
2017-09-22 15:44:08 +01:00
|
|
|
struct radv_shader_module *module,
|
2017-10-16 12:18:02 +01:00
|
|
|
struct nir_shader *const *shaders,
|
|
|
|
int shader_count,
|
2017-09-01 15:51:12 +01:00
|
|
|
struct radv_pipeline_layout *layout,
|
2018-03-13 13:54:04 +00:00
|
|
|
const struct radv_shader_variant_key *key,
|
2017-09-01 15:51:12 +01:00
|
|
|
void **code_out,
|
|
|
|
unsigned *code_size_out)
|
2017-09-01 10:41:18 +01:00
|
|
|
{
|
2018-03-13 13:54:04 +00:00
|
|
|
struct radv_nir_compiler_options options = {0};
|
2017-09-01 10:41:18 +01:00
|
|
|
|
2017-09-01 15:51:12 +01:00
|
|
|
options.layout = layout;
|
|
|
|
if (key)
|
|
|
|
options.key = *key;
|
|
|
|
|
2017-10-11 01:59:20 +01:00
|
|
|
options.unsafe_math = !!(device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH);
|
2018-05-17 08:56:47 +01:00
|
|
|
options.supports_spill = true;
|
2017-09-01 15:51:12 +01:00
|
|
|
|
2017-09-15 03:52:38 +01:00
|
|
|
return shader_variant_create(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage,
|
2017-09-01 15:51:12 +01:00
|
|
|
&options, false, code_out, code_size_out);
|
|
|
|
}
|
|
|
|
|
|
|
|
struct radv_shader_variant *
|
|
|
|
radv_create_gs_copy_shader(struct radv_device *device,
|
|
|
|
struct nir_shader *shader,
|
|
|
|
void **code_out,
|
|
|
|
unsigned *code_size_out,
|
|
|
|
bool multiview)
|
|
|
|
{
|
2018-03-13 13:54:04 +00:00
|
|
|
struct radv_nir_compiler_options options = {0};
|
2017-09-01 10:41:18 +01:00
|
|
|
|
2017-09-01 15:51:12 +01:00
|
|
|
options.key.has_multiview_view_index = multiview;
|
2017-09-01 10:41:18 +01:00
|
|
|
|
2017-10-16 12:18:02 +01:00
|
|
|
return shader_variant_create(device, NULL, &shader, 1, MESA_SHADER_VERTEX,
|
2017-09-01 15:51:12 +01:00
|
|
|
&options, true, code_out, code_size_out);
|
2017-09-01 10:41:18 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
radv_shader_variant_destroy(struct radv_device *device,
|
|
|
|
struct radv_shader_variant *variant)
|
|
|
|
{
|
|
|
|
if (!p_atomic_dec_zero(&variant->ref_count))
|
|
|
|
return;
|
|
|
|
|
|
|
|
mtx_lock(&device->shader_slab_mutex);
|
|
|
|
list_del(&variant->slab_list);
|
|
|
|
mtx_unlock(&device->shader_slab_mutex);
|
|
|
|
|
2017-09-22 15:44:08 +01:00
|
|
|
ralloc_free(variant->nir);
|
2017-09-01 12:45:33 +01:00
|
|
|
free(variant->disasm_string);
|
2018-03-14 09:34:13 +00:00
|
|
|
free(variant->llvm_ir_string);
|
2017-09-01 10:41:18 +01:00
|
|
|
free(variant);
|
|
|
|
}
|
|
|
|
|
|
|
|
const char *
|
|
|
|
radv_get_shader_name(struct radv_shader_variant *var, gl_shader_stage stage)
|
|
|
|
{
|
|
|
|
switch (stage) {
|
|
|
|
case MESA_SHADER_VERTEX: return var->info.vs.as_ls ? "Vertex Shader as LS" : var->info.vs.as_es ? "Vertex Shader as ES" : "Vertex Shader as VS";
|
|
|
|
case MESA_SHADER_GEOMETRY: return "Geometry Shader";
|
|
|
|
case MESA_SHADER_FRAGMENT: return "Pixel Shader";
|
|
|
|
case MESA_SHADER_COMPUTE: return "Compute Shader";
|
|
|
|
case MESA_SHADER_TESS_CTRL: return "Tessellation Control Shader";
|
|
|
|
case MESA_SHADER_TESS_EVAL: return var->info.tes.as_es ? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
|
|
|
|
default:
|
|
|
|
return "Unknown shader";
|
|
|
|
};
|
|
|
|
}
|
|
|
|
|
2017-10-27 14:25:05 +01:00
|
|
|
static void
|
|
|
|
generate_shader_stats(struct radv_device *device,
|
|
|
|
struct radv_shader_variant *variant,
|
|
|
|
gl_shader_stage stage,
|
|
|
|
struct _mesa_string_buffer *buf)
|
2017-09-05 14:34:07 +01:00
|
|
|
{
|
|
|
|
unsigned lds_increment = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
|
|
|
|
struct ac_shader_config *conf;
|
|
|
|
unsigned max_simd_waves;
|
|
|
|
unsigned lds_per_wave = 0;
|
|
|
|
|
2018-04-23 01:16:07 +01:00
|
|
|
max_simd_waves = ac_get_max_simd_waves(device->physical_device->rad_info.family);
|
2017-09-05 14:34:07 +01:00
|
|
|
|
|
|
|
conf = &variant->config;
|
|
|
|
|
|
|
|
if (stage == MESA_SHADER_FRAGMENT) {
|
|
|
|
lds_per_wave = conf->lds_size * lds_increment +
|
|
|
|
align(variant->info.fs.num_interp * 48,
|
|
|
|
lds_increment);
|
|
|
|
}
|
|
|
|
|
2017-10-27 14:25:05 +01:00
|
|
|
if (conf->num_sgprs)
|
2018-04-06 13:06:24 +01:00
|
|
|
max_simd_waves =
|
|
|
|
MIN2(max_simd_waves,
|
|
|
|
radv_get_num_physical_sgprs(device->physical_device) / conf->num_sgprs);
|
2017-09-05 14:34:07 +01:00
|
|
|
|
|
|
|
if (conf->num_vgprs)
|
2018-04-06 13:10:34 +01:00
|
|
|
max_simd_waves =
|
|
|
|
MIN2(max_simd_waves,
|
|
|
|
RADV_NUM_PHYSICAL_VGPRS / conf->num_vgprs);
|
2017-09-05 14:34:07 +01:00
|
|
|
|
|
|
|
/* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
|
|
|
|
* that PS can use.
|
|
|
|
*/
|
|
|
|
if (lds_per_wave)
|
|
|
|
max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
|
|
|
|
|
2017-10-27 14:25:05 +01:00
|
|
|
if (stage == MESA_SHADER_FRAGMENT) {
|
|
|
|
_mesa_string_buffer_printf(buf, "*** SHADER CONFIG ***\n"
|
|
|
|
"SPI_PS_INPUT_ADDR = 0x%04x\n"
|
|
|
|
"SPI_PS_INPUT_ENA = 0x%04x\n",
|
|
|
|
conf->spi_ps_input_addr, conf->spi_ps_input_ena);
|
|
|
|
}
|
|
|
|
|
|
|
|
_mesa_string_buffer_printf(buf, "*** SHADER STATS ***\n"
|
|
|
|
"SGPRS: %d\n"
|
|
|
|
"VGPRS: %d\n"
|
|
|
|
"Spilled SGPRs: %d\n"
|
|
|
|
"Spilled VGPRs: %d\n"
|
2018-03-01 21:12:56 +00:00
|
|
|
"PrivMem VGPRS: %d\n"
|
2017-10-27 14:25:05 +01:00
|
|
|
"Code Size: %d bytes\n"
|
|
|
|
"LDS: %d blocks\n"
|
|
|
|
"Scratch: %d bytes per wave\n"
|
|
|
|
"Max Waves: %d\n"
|
|
|
|
"********************\n\n\n",
|
|
|
|
conf->num_sgprs, conf->num_vgprs,
|
2018-03-01 21:12:56 +00:00
|
|
|
conf->spilled_sgprs, conf->spilled_vgprs,
|
|
|
|
variant->info.private_mem_vgprs, variant->code_size,
|
2017-10-27 14:25:05 +01:00
|
|
|
conf->lds_size, conf->scratch_bytes_per_wave,
|
|
|
|
max_simd_waves);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
radv_shader_dump_stats(struct radv_device *device,
|
|
|
|
struct radv_shader_variant *variant,
|
|
|
|
gl_shader_stage stage,
|
|
|
|
FILE *file)
|
|
|
|
{
|
|
|
|
struct _mesa_string_buffer *buf = _mesa_string_buffer_create(NULL, 256);
|
|
|
|
|
|
|
|
generate_shader_stats(device, variant, stage, buf);
|
|
|
|
|
2017-09-05 14:34:07 +01:00
|
|
|
fprintf(file, "\n%s:\n", radv_get_shader_name(variant, stage));
|
2017-10-30 08:38:14 +00:00
|
|
|
fprintf(file, "%s", buf->buf);
|
2017-09-05 14:34:07 +01:00
|
|
|
|
2017-10-27 14:25:05 +01:00
|
|
|
_mesa_string_buffer_destroy(buf);
|
|
|
|
}
|
|
|
|
|
|
|
|
VkResult
|
|
|
|
radv_GetShaderInfoAMD(VkDevice _device,
|
|
|
|
VkPipeline _pipeline,
|
|
|
|
VkShaderStageFlagBits shaderStage,
|
|
|
|
VkShaderInfoTypeAMD infoType,
|
|
|
|
size_t* pInfoSize,
|
|
|
|
void* pInfo)
|
|
|
|
{
|
|
|
|
RADV_FROM_HANDLE(radv_device, device, _device);
|
|
|
|
RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
|
|
|
|
gl_shader_stage stage = vk_to_mesa_shader_stage(shaderStage);
|
|
|
|
struct radv_shader_variant *variant = pipeline->shaders[stage];
|
|
|
|
struct _mesa_string_buffer *buf;
|
|
|
|
VkResult result = VK_SUCCESS;
|
|
|
|
|
|
|
|
/* Spec doesn't indicate what to do if the stage is invalid, so just
|
|
|
|
* return no info for this. */
|
|
|
|
if (!variant)
|
2018-05-31 00:06:41 +01:00
|
|
|
return vk_error(device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
|
2017-10-27 14:25:05 +01:00
|
|
|
|
|
|
|
switch (infoType) {
|
|
|
|
case VK_SHADER_INFO_TYPE_STATISTICS_AMD:
|
|
|
|
if (!pInfo) {
|
|
|
|
*pInfoSize = sizeof(VkShaderStatisticsInfoAMD);
|
|
|
|
} else {
|
|
|
|
unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
|
|
|
|
struct ac_shader_config *conf = &variant->config;
|
|
|
|
|
|
|
|
VkShaderStatisticsInfoAMD statistics = {};
|
|
|
|
statistics.shaderStageMask = shaderStage;
|
2018-04-06 13:10:34 +01:00
|
|
|
statistics.numPhysicalVgprs = RADV_NUM_PHYSICAL_VGPRS;
|
2018-04-06 13:06:24 +01:00
|
|
|
statistics.numPhysicalSgprs = radv_get_num_physical_sgprs(device->physical_device);
|
2017-10-27 14:25:05 +01:00
|
|
|
statistics.numAvailableSgprs = statistics.numPhysicalSgprs;
|
|
|
|
|
|
|
|
if (stage == MESA_SHADER_COMPUTE) {
|
|
|
|
unsigned *local_size = variant->nir->info.cs.local_size;
|
|
|
|
unsigned workgroup_size = local_size[0] * local_size[1] * local_size[2];
|
|
|
|
|
|
|
|
statistics.numAvailableVgprs = statistics.numPhysicalVgprs /
|
|
|
|
ceil(workgroup_size / statistics.numPhysicalVgprs);
|
|
|
|
|
|
|
|
statistics.computeWorkGroupSize[0] = local_size[0];
|
|
|
|
statistics.computeWorkGroupSize[1] = local_size[1];
|
|
|
|
statistics.computeWorkGroupSize[2] = local_size[2];
|
|
|
|
} else {
|
|
|
|
statistics.numAvailableVgprs = statistics.numPhysicalVgprs;
|
|
|
|
}
|
|
|
|
|
|
|
|
statistics.resourceUsage.numUsedVgprs = conf->num_vgprs;
|
|
|
|
statistics.resourceUsage.numUsedSgprs = conf->num_sgprs;
|
|
|
|
statistics.resourceUsage.ldsSizePerLocalWorkGroup = 32768;
|
|
|
|
statistics.resourceUsage.ldsUsageSizeInBytes = conf->lds_size * lds_multiplier;
|
|
|
|
statistics.resourceUsage.scratchMemUsageInBytes = conf->scratch_bytes_per_wave;
|
|
|
|
|
|
|
|
size_t size = *pInfoSize;
|
|
|
|
*pInfoSize = sizeof(statistics);
|
|
|
|
|
|
|
|
memcpy(pInfo, &statistics, MIN2(size, *pInfoSize));
|
|
|
|
|
|
|
|
if (size < *pInfoSize)
|
|
|
|
result = VK_INCOMPLETE;
|
|
|
|
}
|
|
|
|
|
|
|
|
break;
|
|
|
|
case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD:
|
|
|
|
buf = _mesa_string_buffer_create(NULL, 1024);
|
|
|
|
|
|
|
|
_mesa_string_buffer_printf(buf, "%s:\n", radv_get_shader_name(variant, stage));
|
|
|
|
_mesa_string_buffer_printf(buf, "%s\n\n", variant->disasm_string);
|
|
|
|
generate_shader_stats(device, variant, stage, buf);
|
|
|
|
|
|
|
|
/* Need to include the null terminator. */
|
|
|
|
size_t length = buf->length + 1;
|
|
|
|
|
|
|
|
if (!pInfo) {
|
|
|
|
*pInfoSize = length;
|
|
|
|
} else {
|
|
|
|
size_t size = *pInfoSize;
|
|
|
|
*pInfoSize = length;
|
|
|
|
|
|
|
|
memcpy(pInfo, buf->buf, MIN2(size, length));
|
|
|
|
|
|
|
|
if (size < length)
|
|
|
|
result = VK_INCOMPLETE;
|
|
|
|
}
|
|
|
|
|
|
|
|
_mesa_string_buffer_destroy(buf);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
/* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
|
|
|
|
result = VK_ERROR_FEATURE_NOT_PRESENT;
|
|
|
|
break;
|
2017-09-05 14:34:07 +01:00
|
|
|
}
|
|
|
|
|
2017-10-27 14:25:05 +01:00
|
|
|
return result;
|
2017-09-05 14:34:07 +01:00
|
|
|
}
|