2011-08-07 21:36:11 +01:00
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/* Copyright © 2011 Intel Corporation
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2011-05-02 17:45:40 +01:00
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "brw_vec4.h"
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2014-05-19 18:20:37 +01:00
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#include "brw_cfg.h"
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2015-11-23 02:27:42 +00:00
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#include "brw_eu.h"
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2021-04-05 18:44:41 +01:00
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#include "dev/intel_debug.h"
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2019-05-23 17:05:23 +01:00
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#include "util/mesa-sha1.h"
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2011-05-02 17:45:40 +01:00
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2015-10-22 23:35:15 +01:00
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using namespace brw;
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2011-05-02 17:45:40 +01:00
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2015-10-22 23:35:15 +01:00
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static void
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2021-03-29 23:40:04 +01:00
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generate_math1_gfx4(struct brw_codegen *p,
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2015-10-22 23:35:15 +01:00
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vec4_instruction *inst,
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struct brw_reg dst,
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struct brw_reg src)
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2011-05-02 17:45:40 +01:00
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{
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2021-03-29 23:40:04 +01:00
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gfx4_math(p,
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2014-06-07 10:12:46 +01:00
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dst,
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brw_math_function(inst->opcode),
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inst->base_mrf,
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src,
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BRW_MATH_PRECISION_FULL);
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2011-05-02 17:45:40 +01:00
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}
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2011-08-09 20:30:41 +01:00
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static void
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2021-03-29 23:40:04 +01:00
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check_gfx6_math_src_arg(struct brw_reg src)
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2011-08-09 20:30:41 +01:00
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{
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/* Source swizzles are ignored. */
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assert(!src.abs);
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assert(!src.negate);
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2015-10-23 03:41:30 +01:00
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assert(src.swizzle == BRW_SWIZZLE_XYZW);
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2011-08-09 20:30:41 +01:00
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}
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2015-10-22 23:35:15 +01:00
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static void
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2021-03-29 23:40:04 +01:00
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generate_math_gfx6(struct brw_codegen *p,
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2015-10-22 23:35:15 +01:00
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vec4_instruction *inst,
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struct brw_reg dst,
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struct brw_reg src0,
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struct brw_reg src1)
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2011-08-09 20:30:41 +01:00
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{
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/* Can't do writemask because math can't be align16. */
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2015-10-23 03:41:30 +01:00
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assert(dst.writemask == WRITEMASK_XYZW);
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2011-08-09 20:30:41 +01:00
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/* Source swizzles are ignored. */
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2021-03-29 23:40:04 +01:00
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check_gfx6_math_src_arg(src0);
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2014-06-07 10:32:40 +01:00
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if (src1.file == BRW_GENERAL_REGISTER_FILE)
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2021-03-29 23:40:04 +01:00
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check_gfx6_math_src_arg(src1);
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2011-08-09 20:30:41 +01:00
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2014-06-01 00:57:02 +01:00
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brw_set_default_access_mode(p, BRW_ALIGN_1);
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2021-03-29 23:40:04 +01:00
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gfx6_math(p, dst, brw_math_function(inst->opcode), src0, src1);
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2014-06-01 00:57:02 +01:00
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brw_set_default_access_mode(p, BRW_ALIGN_16);
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2011-08-09 20:30:41 +01:00
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}
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2015-10-22 23:35:15 +01:00
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static void
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2021-03-29 23:40:04 +01:00
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generate_math2_gfx4(struct brw_codegen *p,
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2015-10-22 23:35:15 +01:00
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vec4_instruction *inst,
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struct brw_reg dst,
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struct brw_reg src0,
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struct brw_reg src1)
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2011-08-09 20:30:41 +01:00
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{
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2011-09-29 01:37:56 +01:00
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/* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
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* "Message Payload":
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*
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* "Operand0[7]. For the INT DIV functions, this operand is the
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* denominator."
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* ...
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* "Operand1[7]. For the INT DIV functions, this operand is the
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* numerator."
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*/
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bool is_int_div = inst->opcode != SHADER_OPCODE_POW;
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struct brw_reg &op0 = is_int_div ? src1 : src0;
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struct brw_reg &op1 = is_int_div ? src0 : src1;
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2012-08-06 23:02:34 +01:00
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brw_push_insn_state(p);
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2014-06-01 00:57:02 +01:00
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brw_set_default_saturate(p, false);
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brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
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2011-09-29 01:37:56 +01:00
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brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1);
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2012-08-06 23:02:34 +01:00
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brw_pop_insn_state(p);
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2011-08-09 20:30:41 +01:00
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2021-03-29 23:40:04 +01:00
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gfx4_math(p,
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2014-06-07 10:12:46 +01:00
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dst,
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brw_math_function(inst->opcode),
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inst->base_mrf,
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op0,
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BRW_MATH_PRECISION_FULL);
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2011-08-09 20:30:41 +01:00
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}
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2015-10-22 23:35:15 +01:00
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static void
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generate_tex(struct brw_codegen *p,
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struct brw_vue_prog_data *prog_data,
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2017-01-06 09:13:24 +00:00
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gl_shader_stage stage,
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2015-10-22 23:35:15 +01:00
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vec4_instruction *inst,
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struct brw_reg dst,
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struct brw_reg src,
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2015-11-03 02:28:49 +00:00
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struct brw_reg surface_index,
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2015-10-22 23:35:15 +01:00
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struct brw_reg sampler_index)
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2011-10-26 21:53:11 +01:00
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{
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2021-04-05 21:19:39 +01:00
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const struct intel_device_info *devinfo = p->devinfo;
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2011-10-26 21:53:11 +01:00
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int msg_type = -1;
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2021-03-29 22:41:58 +01:00
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if (devinfo->ver >= 5) {
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2011-10-26 21:53:11 +01:00
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switch (inst->opcode) {
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case SHADER_OPCODE_TEX:
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case SHADER_OPCODE_TXL:
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if (inst->shadow_compare) {
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2021-03-29 23:16:59 +01:00
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msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
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2011-10-26 21:53:11 +01:00
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} else {
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2021-03-29 23:16:59 +01:00
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msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_LOD;
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2011-10-26 21:53:11 +01:00
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}
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break;
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case SHADER_OPCODE_TXD:
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2013-01-04 15:53:09 +00:00
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if (inst->shadow_compare) {
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2021-03-29 23:46:12 +01:00
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/* Gfx7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
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2021-09-22 13:06:58 +01:00
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assert(devinfo->verx10 == 75);
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2013-01-04 15:53:09 +00:00
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msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
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} else {
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2021-03-29 23:16:59 +01:00
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msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
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2013-01-04 15:53:09 +00:00
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}
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2011-10-26 21:53:11 +01:00
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break;
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case SHADER_OPCODE_TXF:
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2021-03-29 23:16:59 +01:00
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msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_LD;
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2011-10-26 21:53:11 +01:00
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break;
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2013-12-10 14:36:31 +00:00
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case SHADER_OPCODE_TXF_CMS:
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2021-03-29 22:41:58 +01:00
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if (devinfo->ver >= 7)
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2021-03-29 23:16:59 +01:00
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msg_type = GFX7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
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2013-01-24 08:35:15 +00:00
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else
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2021-03-29 23:16:59 +01:00
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msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_LD;
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2013-01-24 08:35:15 +00:00
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break;
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2013-11-29 21:32:16 +00:00
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case SHADER_OPCODE_TXF_MCS:
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2021-03-29 22:41:58 +01:00
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assert(devinfo->ver >= 7);
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2021-03-29 23:16:59 +01:00
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msg_type = GFX7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
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2013-11-29 21:32:16 +00:00
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break;
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2011-10-26 21:53:11 +01:00
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case SHADER_OPCODE_TXS:
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2021-03-29 23:16:59 +01:00
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msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
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2011-10-26 21:53:11 +01:00
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break;
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2013-03-31 09:31:12 +01:00
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case SHADER_OPCODE_TG4:
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2013-10-10 07:42:47 +01:00
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if (inst->shadow_compare) {
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2021-03-29 23:16:59 +01:00
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msg_type = GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
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2013-10-10 07:42:47 +01:00
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} else {
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2021-03-29 23:16:59 +01:00
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msg_type = GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
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2013-10-10 07:42:47 +01:00
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}
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2013-03-31 09:31:12 +01:00
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break;
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2013-10-08 09:42:10 +01:00
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case SHADER_OPCODE_TG4_OFFSET:
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2013-10-10 07:42:47 +01:00
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if (inst->shadow_compare) {
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2021-03-29 23:16:59 +01:00
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msg_type = GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
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2013-10-10 07:42:47 +01:00
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} else {
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2021-03-29 23:16:59 +01:00
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msg_type = GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
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2013-10-10 07:42:47 +01:00
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}
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2013-10-08 09:42:10 +01:00
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break;
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2015-08-12 01:37:32 +01:00
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case SHADER_OPCODE_SAMPLEINFO:
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2021-03-29 23:16:59 +01:00
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msg_type = GFX6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO;
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2015-08-12 01:37:32 +01:00
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break;
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2011-10-26 21:53:11 +01:00
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default:
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2014-06-29 22:54:01 +01:00
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unreachable("should not get here: invalid vec4 texture opcode");
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2011-10-26 21:53:11 +01:00
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}
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} else {
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switch (inst->opcode) {
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case SHADER_OPCODE_TEX:
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case SHADER_OPCODE_TXL:
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if (inst->shadow_compare) {
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msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE;
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assert(inst->mlen == 3);
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} else {
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msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD;
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assert(inst->mlen == 2);
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}
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break;
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case SHADER_OPCODE_TXD:
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/* There is no sample_d_c message; comparisons are done manually. */
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msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS;
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assert(inst->mlen == 4);
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break;
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case SHADER_OPCODE_TXF:
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msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_LD;
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assert(inst->mlen == 2);
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break;
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case SHADER_OPCODE_TXS:
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msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO;
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assert(inst->mlen == 2);
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break;
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default:
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2014-06-29 22:54:01 +01:00
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unreachable("should not get here: invalid vec4 texture opcode");
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2011-10-26 21:53:11 +01:00
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}
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}
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assert(msg_type != -1);
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2014-08-04 08:41:03 +01:00
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assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
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2011-11-12 10:21:44 +00:00
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/* Load the message header if present. If there's a texture offset, we need
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* to set it up explicitly and load the offset bitfield. Otherwise, we can
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* use an implied move from g0 to the first message register.
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*/
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2015-03-24 17:17:32 +00:00
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if (inst->header_size != 0) {
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2021-03-29 22:41:58 +01:00
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if (devinfo->ver < 6 && !inst->offset) {
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2014-01-18 22:29:19 +00:00
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/* Set up an implied move from g0 to the MRF. */
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src = brw_vec8_grf(0, 0);
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} else {
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struct brw_reg header =
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retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD);
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2014-12-10 22:59:26 +00:00
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uint32_t dw2 = 0;
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2014-01-18 22:29:19 +00:00
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/* Explicitly set up the message header by copying g0 to the MRF. */
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brw_push_insn_state(p);
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2014-06-01 00:57:02 +01:00
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brw_set_default_mask_control(p, BRW_MASK_DISABLE);
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2014-01-18 22:29:19 +00:00
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brw_MOV(p, header, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
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2014-06-01 00:57:02 +01:00
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brw_set_default_access_mode(p, BRW_ALIGN_1);
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2014-01-18 22:29:19 +00:00
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2014-12-10 22:59:26 +00:00
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if (inst->offset)
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2014-01-18 22:29:19 +00:00
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/* Set the texel offset bits in DWord 2. */
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2014-12-10 22:59:26 +00:00
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dw2 = inst->offset;
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2017-01-06 09:13:24 +00:00
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/* The VS, DS, and FS stages have the g0.2 payload delivered as 0,
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* so header0.2 is 0 when g0 is copied. The HS and GS stages do
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* not, so we must set to to 0 to avoid setting undesirable bits
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* in the message header.
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*/
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if (dw2 ||
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stage == MESA_SHADER_TESS_CTRL ||
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stage == MESA_SHADER_GEOMETRY) {
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2014-12-10 22:59:26 +00:00
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brw_MOV(p, get_element_ud(header, 2), brw_imm_ud(dw2));
|
2017-01-06 09:13:24 +00:00
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}
|
2014-01-18 22:32:49 +00:00
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2015-01-22 21:46:44 +00:00
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brw_adjust_sampler_state_pointer(p, header, sampler_index);
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2014-01-18 22:29:19 +00:00
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brw_pop_insn_state(p);
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}
|
2011-10-26 21:53:11 +01:00
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}
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uint32_t return_format;
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switch (dst.type) {
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case BRW_REGISTER_TYPE_D:
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return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
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break;
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case BRW_REGISTER_TYPE_UD:
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return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
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break;
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default:
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return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
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|
|
break;
|
|
|
|
}
|
|
|
|
|
2020-04-25 20:15:11 +01:00
|
|
|
/* Stomp the resinfo output type to UINT32. On gens 4-5, the output type
|
2021-03-29 23:40:04 +01:00
|
|
|
* is set as part of the message descriptor. On gfx4, the PRM seems to
|
2020-04-25 20:15:11 +01:00
|
|
|
* allow UINT32 and FLOAT32 (i965 PRM, Vol. 4 Section 4.8.1.1), but on
|
|
|
|
* later gens UINT32 is required. Once you hit Sandy Bridge, the bit is
|
|
|
|
* gone from the message descriptor entirely and you just get UINT32 all
|
2021-03-29 23:40:04 +01:00
|
|
|
* the time regasrdless. Since we can really only do non-UINT32 on gfx4,
|
2020-04-25 20:15:11 +01:00
|
|
|
* just stomp it to UINT32 all the time.
|
|
|
|
*/
|
|
|
|
if (inst->opcode == SHADER_OPCODE_TXS)
|
|
|
|
return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
|
|
|
|
|
2015-11-03 02:28:49 +00:00
|
|
|
if (surface_index.file == BRW_IMMEDIATE_VALUE &&
|
|
|
|
sampler_index.file == BRW_IMMEDIATE_VALUE) {
|
|
|
|
uint32_t surface = surface_index.ud;
|
2015-10-23 03:41:30 +01:00
|
|
|
uint32_t sampler = sampler_index.ud;
|
2014-08-10 00:50:16 +01:00
|
|
|
|
|
|
|
brw_SAMPLE(p,
|
|
|
|
dst,
|
|
|
|
inst->base_mrf,
|
|
|
|
src,
|
2021-12-04 04:20:30 +00:00
|
|
|
surface,
|
2014-08-10 00:50:16 +01:00
|
|
|
sampler % 16,
|
|
|
|
msg_type,
|
|
|
|
1, /* response length */
|
|
|
|
inst->mlen,
|
2015-03-24 17:17:32 +00:00
|
|
|
inst->header_size != 0,
|
2014-08-10 00:50:16 +01:00
|
|
|
BRW_SAMPLER_SIMD_MODE_SIMD4X2,
|
|
|
|
return_format);
|
|
|
|
} else {
|
2014-08-10 00:42:08 +01:00
|
|
|
/* Non-constant sampler index. */
|
|
|
|
|
|
|
|
struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
|
2015-11-03 02:28:49 +00:00
|
|
|
struct brw_reg surface_reg = vec1(retype(surface_index, BRW_REGISTER_TYPE_UD));
|
2014-08-10 00:42:08 +01:00
|
|
|
struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
|
|
|
|
|
|
|
|
brw_push_insn_state(p);
|
|
|
|
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
|
|
|
|
brw_set_default_access_mode(p, BRW_ALIGN_1);
|
|
|
|
|
2016-05-14 00:41:13 +01:00
|
|
|
if (brw_regs_equal(&surface_reg, &sampler_reg)) {
|
2015-11-03 02:28:49 +00:00
|
|
|
brw_MUL(p, addr, sampler_reg, brw_imm_uw(0x101));
|
|
|
|
} else {
|
2016-12-22 23:26:12 +00:00
|
|
|
if (sampler_reg.file == BRW_IMMEDIATE_VALUE) {
|
|
|
|
brw_OR(p, addr, surface_reg, brw_imm_ud(sampler_reg.ud << 8));
|
|
|
|
} else {
|
|
|
|
brw_SHL(p, addr, sampler_reg, brw_imm_ud(8));
|
|
|
|
brw_OR(p, addr, addr, surface_reg);
|
|
|
|
}
|
2015-11-03 02:28:49 +00:00
|
|
|
}
|
2015-05-28 15:27:31 +01:00
|
|
|
brw_AND(p, addr, addr, brw_imm_ud(0xfff));
|
2014-08-10 00:42:08 +01:00
|
|
|
|
2015-02-26 15:24:03 +00:00
|
|
|
brw_pop_insn_state(p);
|
|
|
|
|
2015-05-28 19:35:44 +01:00
|
|
|
if (inst->base_mrf != -1)
|
2021-03-29 23:40:04 +01:00
|
|
|
gfx6_resolve_implied_move(p, &src, inst->base_mrf);
|
2015-05-28 19:35:44 +01:00
|
|
|
|
i965: Factor out logic to build a send message instruction with indirect descriptor.
This is going to be useful because the Gen7+ uniform and varying pull
constant, texturing, typed and untyped surface read, write, and atomic
generation code on the vec4 and fs back-end all require the same logic
to handle conditionally indirect surface indices. In pseudocode:
| if (surface.file == BRW_IMMEDIATE_VALUE) {
| inst = brw_SEND(p, dst, payload);
| set_descriptor_control_bits(inst, surface, ...);
| } else {
| inst = brw_OR(p, addr, surface, 0);
| set_descriptor_control_bits(inst, ...);
| inst = brw_SEND(p, dst, payload);
| set_indirect_send_descriptor(inst, addr);
| }
This patch abstracts out this frequently recurring pattern so we can
now write:
| inst = brw_send_indirect_message(p, sfid, dst, payload, surface)
| set_descriptor_control_bits(inst, ...);
without worrying about handling the immediate and indirect surface
index cases explicitly.
v2: Rebase. Improve documentatation and commit message. (Topi)
Preserve UW destination type cargo-cult. (Topi, Ken, Matt)
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2015-03-19 13:44:24 +00:00
|
|
|
/* dst = send(offset, a0.0 | <descriptor>) */
|
2018-06-02 23:15:15 +01:00
|
|
|
brw_send_indirect_message(
|
|
|
|
p, BRW_SFID_SAMPLER, dst, src, addr,
|
|
|
|
brw_message_desc(devinfo, inst->mlen, 1, inst->header_size) |
|
|
|
|
brw_sampler_desc(devinfo,
|
|
|
|
0 /* surface */,
|
|
|
|
0 /* sampler */,
|
|
|
|
msg_type,
|
|
|
|
BRW_SAMPLER_SIMD_MODE_SIMD4X2,
|
2019-02-07 23:45:51 +00:00
|
|
|
return_format),
|
|
|
|
false /* EOT */);
|
2014-08-10 00:42:08 +01:00
|
|
|
|
|
|
|
/* visitor knows more than we do about the surface limit required,
|
|
|
|
* so has already done marking.
|
|
|
|
*/
|
2014-08-10 00:50:16 +01:00
|
|
|
}
|
2011-10-26 21:53:11 +01:00
|
|
|
}
|
|
|
|
|
2015-10-22 23:35:15 +01:00
|
|
|
static void
|
|
|
|
generate_vs_urb_write(struct brw_codegen *p, vec4_instruction *inst)
|
2011-05-02 17:45:40 +01:00
|
|
|
{
|
|
|
|
brw_urb_WRITE(p,
|
|
|
|
brw_null_reg(), /* dest */
|
|
|
|
inst->base_mrf, /* starting mrf reg nr */
|
|
|
|
brw_vec8_grf(0, 0), /* src */
|
2013-08-11 05:13:33 +01:00
|
|
|
inst->urb_write_flags,
|
2011-05-02 17:45:40 +01:00
|
|
|
inst->mlen,
|
|
|
|
0, /* response len */
|
|
|
|
inst->offset, /* urb destination offset */
|
|
|
|
BRW_URB_SWIZZLE_INTERLEAVE);
|
|
|
|
}
|
|
|
|
|
2015-10-22 23:35:15 +01:00
|
|
|
static void
|
|
|
|
generate_gs_urb_write(struct brw_codegen *p, vec4_instruction *inst)
|
2013-03-21 16:11:12 +00:00
|
|
|
{
|
|
|
|
struct brw_reg src = brw_message_reg(inst->base_mrf);
|
|
|
|
brw_urb_WRITE(p,
|
|
|
|
brw_null_reg(), /* dest */
|
|
|
|
inst->base_mrf, /* starting mrf reg nr */
|
|
|
|
src,
|
|
|
|
inst->urb_write_flags,
|
|
|
|
inst->mlen,
|
|
|
|
0, /* response len */
|
|
|
|
inst->offset, /* urb destination offset */
|
|
|
|
BRW_URB_SWIZZLE_INTERLEAVE);
|
|
|
|
}
|
|
|
|
|
2015-10-22 23:35:15 +01:00
|
|
|
static void
|
|
|
|
generate_gs_urb_write_allocate(struct brw_codegen *p, vec4_instruction *inst)
|
2014-07-09 15:28:30 +01:00
|
|
|
{
|
|
|
|
struct brw_reg src = brw_message_reg(inst->base_mrf);
|
|
|
|
|
|
|
|
/* We pass the temporary passed in src0 as the writeback register */
|
|
|
|
brw_urb_WRITE(p,
|
2015-11-20 05:51:37 +00:00
|
|
|
inst->src[0].as_brw_reg(), /* dest */
|
2014-07-09 15:28:30 +01:00
|
|
|
inst->base_mrf, /* starting mrf reg nr */
|
|
|
|
src,
|
|
|
|
BRW_URB_WRITE_ALLOCATE_COMPLETE,
|
|
|
|
inst->mlen,
|
|
|
|
1, /* response len */
|
|
|
|
inst->offset, /* urb destination offset */
|
|
|
|
BRW_URB_SWIZZLE_INTERLEAVE);
|
|
|
|
|
|
|
|
/* Now put allocated urb handle in dst.0 */
|
|
|
|
brw_push_insn_state(p);
|
|
|
|
brw_set_default_access_mode(p, BRW_ALIGN_1);
|
|
|
|
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
|
2015-11-20 05:51:37 +00:00
|
|
|
brw_MOV(p, get_element_ud(inst->dst.as_brw_reg(), 0),
|
|
|
|
get_element_ud(inst->src[0].as_brw_reg(), 0));
|
2014-07-09 15:28:30 +01:00
|
|
|
brw_pop_insn_state(p);
|
|
|
|
}
|
|
|
|
|
2015-10-22 23:35:15 +01:00
|
|
|
static void
|
|
|
|
generate_gs_thread_end(struct brw_codegen *p, vec4_instruction *inst)
|
2013-03-23 14:42:32 +00:00
|
|
|
{
|
|
|
|
struct brw_reg src = brw_message_reg(inst->base_mrf);
|
|
|
|
brw_urb_WRITE(p,
|
|
|
|
brw_null_reg(), /* dest */
|
|
|
|
inst->base_mrf, /* starting mrf reg nr */
|
|
|
|
src,
|
2014-07-09 14:32:57 +01:00
|
|
|
BRW_URB_WRITE_EOT | inst->urb_write_flags,
|
2015-09-25 04:58:05 +01:00
|
|
|
inst->mlen,
|
2013-03-23 14:42:32 +00:00
|
|
|
0, /* response len */
|
|
|
|
0, /* urb destination offset */
|
|
|
|
BRW_URB_SWIZZLE_INTERLEAVE);
|
|
|
|
}
|
|
|
|
|
2015-10-22 23:35:15 +01:00
|
|
|
static void
|
|
|
|
generate_gs_set_write_offset(struct brw_codegen *p,
|
|
|
|
struct brw_reg dst,
|
|
|
|
struct brw_reg src0,
|
|
|
|
struct brw_reg src1)
|
2013-03-23 14:59:13 +00:00
|
|
|
{
|
|
|
|
/* From p22 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
|
|
|
|
* Header: M0.3):
|
|
|
|
*
|
|
|
|
* Slot 0 Offset. This field, after adding to the Global Offset field
|
|
|
|
* in the message descriptor, specifies the offset (in 256-bit units)
|
|
|
|
* from the start of the URB entry, as referenced by URB Handle 0, at
|
|
|
|
* which the data will be accessed.
|
|
|
|
*
|
|
|
|
* Similar text describes DWORD M0.4, which is slot 1 offset.
|
|
|
|
*
|
|
|
|
* Therefore, we want to multiply DWORDs 0 and 4 of src0 (the x components
|
|
|
|
* of the register for geometry shader invocations 0 and 1) by the
|
|
|
|
* immediate value in src1, and store the result in DWORDs 3 and 4 of dst.
|
|
|
|
*
|
|
|
|
* We can do this with the following EU instruction:
|
|
|
|
*
|
2014-12-04 23:37:17 +00:00
|
|
|
* mul(2) dst.3<1>UD src0<8;2,4>UD src1<...>UW { Align1 WE_all }
|
2013-03-23 14:59:13 +00:00
|
|
|
*/
|
|
|
|
brw_push_insn_state(p);
|
2014-06-01 00:57:02 +01:00
|
|
|
brw_set_default_access_mode(p, BRW_ALIGN_1);
|
|
|
|
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
|
2021-03-29 22:41:58 +01:00
|
|
|
assert(p->devinfo->ver >= 7 &&
|
2014-12-04 23:37:17 +00:00
|
|
|
src1.file == BRW_IMMEDIATE_VALUE &&
|
|
|
|
src1.type == BRW_REGISTER_TYPE_UD &&
|
2015-10-23 03:41:30 +01:00
|
|
|
src1.ud <= USHRT_MAX);
|
2015-10-29 04:19:52 +00:00
|
|
|
if (src0.file == BRW_IMMEDIATE_VALUE) {
|
2015-09-25 07:47:29 +01:00
|
|
|
brw_MOV(p, suboffset(stride(dst, 2, 2, 1), 3),
|
2015-10-23 03:41:30 +01:00
|
|
|
brw_imm_ud(src0.ud * src1.ud));
|
2015-09-25 07:47:29 +01:00
|
|
|
} else {
|
2019-03-26 04:17:08 +00:00
|
|
|
if (src1.file == BRW_IMMEDIATE_VALUE) {
|
|
|
|
src1 = brw_imm_uw(src1.ud);
|
|
|
|
}
|
2015-09-25 07:47:29 +01:00
|
|
|
brw_MUL(p, suboffset(stride(dst, 2, 2, 1), 3), stride(src0, 8, 2, 4),
|
|
|
|
retype(src1, BRW_REGISTER_TYPE_UW));
|
|
|
|
}
|
2013-03-23 14:59:13 +00:00
|
|
|
brw_pop_insn_state(p);
|
|
|
|
}
|
|
|
|
|
2015-10-22 23:35:15 +01:00
|
|
|
static void
|
|
|
|
generate_gs_set_vertex_count(struct brw_codegen *p,
|
|
|
|
struct brw_reg dst,
|
|
|
|
struct brw_reg src)
|
2013-03-23 15:18:43 +00:00
|
|
|
{
|
|
|
|
brw_push_insn_state(p);
|
2014-06-01 00:57:02 +01:00
|
|
|
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
|
2013-03-23 15:18:43 +00:00
|
|
|
|
2020-09-22 21:09:56 +01:00
|
|
|
/* If we think of the src and dst registers as composed of 8 DWORDs each,
|
|
|
|
* we want to pick up the contents of DWORDs 0 and 4 from src, truncate
|
|
|
|
* them to WORDs, and then pack them into DWORD 2 of dst.
|
|
|
|
*
|
|
|
|
* It's easier to get the EU to do this if we think of the src and dst
|
|
|
|
* registers as composed of 16 WORDS each; then, we want to pick up the
|
|
|
|
* contents of WORDs 0 and 8 from src, and pack them into WORDs 4 and 5
|
|
|
|
* of dst.
|
|
|
|
*
|
|
|
|
* We can do that by the following EU instruction:
|
|
|
|
*
|
|
|
|
* mov (2) dst.4<1>:uw src<8;1,0>:uw { Align1, Q1, NoMask }
|
|
|
|
*/
|
|
|
|
brw_set_default_access_mode(p, BRW_ALIGN_1);
|
|
|
|
brw_MOV(p,
|
|
|
|
suboffset(stride(retype(dst, BRW_REGISTER_TYPE_UW), 2, 2, 1), 4),
|
|
|
|
stride(retype(src, BRW_REGISTER_TYPE_UW), 8, 1, 0));
|
|
|
|
|
2013-03-23 15:18:43 +00:00
|
|
|
brw_pop_insn_state(p);
|
|
|
|
}
|
|
|
|
|
2015-10-22 23:35:15 +01:00
|
|
|
static void
|
|
|
|
generate_gs_svb_write(struct brw_codegen *p,
|
|
|
|
vec4_instruction *inst,
|
|
|
|
struct brw_reg dst,
|
|
|
|
struct brw_reg src0,
|
|
|
|
struct brw_reg src1)
|
2014-07-18 09:36:10 +01:00
|
|
|
{
|
|
|
|
int binding = inst->sol_binding;
|
|
|
|
bool final_write = inst->sol_final_write;
|
|
|
|
|
|
|
|
brw_push_insn_state(p);
|
2015-12-03 17:27:39 +00:00
|
|
|
brw_set_default_exec_size(p, BRW_EXECUTE_4);
|
2014-07-18 09:36:10 +01:00
|
|
|
/* Copy Vertex data into M0.x */
|
|
|
|
brw_MOV(p, stride(dst, 4, 4, 1),
|
|
|
|
stride(retype(src0, BRW_REGISTER_TYPE_UD), 4, 4, 1));
|
2015-12-03 17:27:39 +00:00
|
|
|
brw_pop_insn_state(p);
|
2014-07-18 09:36:10 +01:00
|
|
|
|
2015-12-03 17:27:39 +00:00
|
|
|
brw_push_insn_state(p);
|
2014-07-18 09:36:10 +01:00
|
|
|
/* Send SVB Write */
|
|
|
|
brw_svb_write(p,
|
|
|
|
final_write ? src1 : brw_null_reg(), /* dest == src1 */
|
|
|
|
1, /* msg_reg_nr */
|
|
|
|
dst, /* src0 == previous dst */
|
2021-03-30 00:02:30 +01:00
|
|
|
BRW_GFX6_SOL_BINDING_START + binding, /* binding_table_index */
|
2014-07-18 09:36:10 +01:00
|
|
|
final_write); /* send_commit_msg */
|
|
|
|
|
|
|
|
/* Finally, wait for the write commit to occur so that we can proceed to
|
|
|
|
* other things safely.
|
|
|
|
*
|
|
|
|
* From the Sandybridge PRM, Volume 4, Part 1, Section 3.3:
|
|
|
|
*
|
|
|
|
* The write commit does not modify the destination register, but
|
|
|
|
* merely clears the dependency associated with the destination
|
|
|
|
* register. Thus, a simple “mov” instruction using the register as a
|
|
|
|
* source is sufficient to wait for the write commit to occur.
|
|
|
|
*/
|
|
|
|
if (final_write) {
|
|
|
|
brw_MOV(p, src1, src1);
|
|
|
|
}
|
|
|
|
brw_pop_insn_state(p);
|
|
|
|
}
|
|
|
|
|
2015-10-22 23:35:15 +01:00
|
|
|
static void
|
|
|
|
generate_gs_svb_set_destination_index(struct brw_codegen *p,
|
|
|
|
vec4_instruction *inst,
|
|
|
|
struct brw_reg dst,
|
|
|
|
struct brw_reg src)
|
2014-07-18 09:47:15 +01:00
|
|
|
{
|
|
|
|
int vertex = inst->sol_vertex;
|
|
|
|
brw_push_insn_state(p);
|
|
|
|
brw_set_default_access_mode(p, BRW_ALIGN_1);
|
|
|
|
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
|
|
|
|
brw_MOV(p, get_element_ud(dst, 5), get_element_ud(src, vertex));
|
|
|
|
brw_pop_insn_state(p);
|
|
|
|
}
|
|
|
|
|
2015-10-22 23:35:15 +01:00
|
|
|
static void
|
|
|
|
generate_gs_set_dword_2(struct brw_codegen *p,
|
|
|
|
struct brw_reg dst,
|
|
|
|
struct brw_reg src)
|
2013-02-19 15:31:16 +00:00
|
|
|
{
|
|
|
|
brw_push_insn_state(p);
|
2014-06-01 00:57:02 +01:00
|
|
|
brw_set_default_access_mode(p, BRW_ALIGN_1);
|
|
|
|
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
|
2014-07-17 07:54:03 +01:00
|
|
|
brw_MOV(p, suboffset(vec1(dst), 2), suboffset(vec1(src), 0));
|
2013-02-19 15:31:16 +00:00
|
|
|
brw_pop_insn_state(p);
|
|
|
|
}
|
|
|
|
|
2015-10-22 23:35:15 +01:00
|
|
|
static void
|
|
|
|
generate_gs_prepare_channel_masks(struct brw_codegen *p,
|
|
|
|
struct brw_reg dst)
|
2013-04-21 16:51:33 +01:00
|
|
|
{
|
|
|
|
/* We want to left shift just DWORD 4 (the x component belonging to the
|
|
|
|
* second geometry shader invocation) by 4 bits. So generate the
|
|
|
|
* instruction:
|
|
|
|
*
|
|
|
|
* shl(1) dst.4<1>UD dst.4<0,1,0>UD 4UD { align1 WE_all }
|
|
|
|
*/
|
|
|
|
dst = suboffset(vec1(dst), 4);
|
|
|
|
brw_push_insn_state(p);
|
2014-06-01 00:57:02 +01:00
|
|
|
brw_set_default_access_mode(p, BRW_ALIGN_1);
|
|
|
|
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
|
2013-04-21 16:51:33 +01:00
|
|
|
brw_SHL(p, dst, dst, brw_imm_ud(4));
|
|
|
|
brw_pop_insn_state(p);
|
|
|
|
}
|
|
|
|
|
2015-10-22 23:35:15 +01:00
|
|
|
static void
|
|
|
|
generate_gs_set_channel_masks(struct brw_codegen *p,
|
|
|
|
struct brw_reg dst,
|
|
|
|
struct brw_reg src)
|
2013-04-21 16:51:33 +01:00
|
|
|
{
|
|
|
|
/* From p21 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
|
|
|
|
* Header: M0.5):
|
|
|
|
*
|
|
|
|
* 15 Vertex 1 DATA [3] / Vertex 0 DATA[7] Channel Mask
|
|
|
|
*
|
|
|
|
* When Swizzle Control = URB_INTERLEAVED this bit controls Vertex 1
|
|
|
|
* DATA[3], when Swizzle Control = URB_NOSWIZZLE this bit controls
|
|
|
|
* Vertex 0 DATA[7]. This bit is ANDed with the corresponding
|
|
|
|
* channel enable to determine the final channel enable. For the
|
|
|
|
* URB_READ_OWORD & URB_READ_HWORD messages, when final channel
|
|
|
|
* enable is 1 it indicates that Vertex 1 DATA [3] will be included
|
|
|
|
* in the writeback message. For the URB_WRITE_OWORD &
|
|
|
|
* URB_WRITE_HWORD messages, when final channel enable is 1 it
|
|
|
|
* indicates that Vertex 1 DATA [3] will be written to the surface.
|
|
|
|
*
|
|
|
|
* 0: Vertex 1 DATA [3] / Vertex 0 DATA[7] channel not included
|
|
|
|
* 1: Vertex DATA [3] / Vertex 0 DATA[7] channel included
|
|
|
|
*
|
|
|
|
* 14 Vertex 1 DATA [2] Channel Mask
|
|
|
|
* 13 Vertex 1 DATA [1] Channel Mask
|
|
|
|
* 12 Vertex 1 DATA [0] Channel Mask
|
|
|
|
* 11 Vertex 0 DATA [3] Channel Mask
|
|
|
|
* 10 Vertex 0 DATA [2] Channel Mask
|
|
|
|
* 9 Vertex 0 DATA [1] Channel Mask
|
|
|
|
* 8 Vertex 0 DATA [0] Channel Mask
|
|
|
|
*
|
|
|
|
* (This is from a section of the PRM that is agnostic to the particular
|
|
|
|
* type of shader being executed, so "Vertex 0" and "Vertex 1" refer to
|
|
|
|
* geometry shader invocations 0 and 1, respectively). Since we have the
|
|
|
|
* enable flags for geometry shader invocation 0 in bits 3:0 of DWORD 0,
|
|
|
|
* and the enable flags for geometry shader invocation 1 in bits 7:0 of
|
|
|
|
* DWORD 4, we just need to OR them together and store the result in bits
|
|
|
|
* 15:8 of DWORD 5.
|
|
|
|
*
|
|
|
|
* It's easier to get the EU to do this if we think of the src and dst
|
|
|
|
* registers as composed of 32 bytes each; then, we want to pick up the
|
|
|
|
* contents of bytes 0 and 16 from src, OR them together, and store them in
|
|
|
|
* byte 21.
|
|
|
|
*
|
|
|
|
* We can do that by the following EU instruction:
|
|
|
|
*
|
|
|
|
* or(1) dst.21<1>UB src<0,1,0>UB src.16<0,1,0>UB { align1 WE_all }
|
|
|
|
*
|
|
|
|
* Note: this relies on the source register having zeros in (a) bits 7:4 of
|
|
|
|
* DWORD 0 and (b) bits 3:0 of DWORD 4. We can rely on (b) because the
|
|
|
|
* source register was prepared by GS_OPCODE_PREPARE_CHANNEL_MASKS (which
|
|
|
|
* shifts DWORD 4 left by 4 bits), and we can rely on (a) because prior to
|
|
|
|
* the execution of GS_OPCODE_PREPARE_CHANNEL_MASKS, DWORDs 0 and 4 need to
|
|
|
|
* contain valid channel mask values (which are in the range 0x0-0xf).
|
|
|
|
*/
|
|
|
|
dst = retype(dst, BRW_REGISTER_TYPE_UB);
|
|
|
|
src = retype(src, BRW_REGISTER_TYPE_UB);
|
|
|
|
brw_push_insn_state(p);
|
2014-06-01 00:57:02 +01:00
|
|
|
brw_set_default_access_mode(p, BRW_ALIGN_1);
|
|
|
|
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
|
2013-04-21 16:51:33 +01:00
|
|
|
brw_OR(p, suboffset(vec1(dst), 21), vec1(src), suboffset(vec1(src), 16));
|
|
|
|
brw_pop_insn_state(p);
|
|
|
|
}
|
|
|
|
|
2015-10-22 23:35:15 +01:00
|
|
|
static void
|
|
|
|
generate_gs_get_instance_id(struct brw_codegen *p,
|
|
|
|
struct brw_reg dst)
|
2014-01-25 20:55:24 +00:00
|
|
|
{
|
2021-03-29 23:16:59 +01:00
|
|
|
/* We want to right shift R0.0 & R0.1 by GFX7_GS_PAYLOAD_INSTANCE_ID_SHIFT
|
2014-01-25 20:55:24 +00:00
|
|
|
* and store into dst.0 & dst.4. So generate the instruction:
|
|
|
|
*
|
2021-03-29 23:16:59 +01:00
|
|
|
* shr(8) dst<1> R0<1,4,0> GFX7_GS_PAYLOAD_INSTANCE_ID_SHIFT { align1 WE_normal 1Q }
|
2014-01-25 20:55:24 +00:00
|
|
|
*/
|
|
|
|
brw_push_insn_state(p);
|
2014-06-01 00:57:02 +01:00
|
|
|
brw_set_default_access_mode(p, BRW_ALIGN_1);
|
2014-01-25 20:55:24 +00:00
|
|
|
dst = retype(dst, BRW_REGISTER_TYPE_UD);
|
|
|
|
struct brw_reg r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
|
|
|
|
brw_SHR(p, dst, stride(r0, 1, 4, 0),
|
2021-03-29 23:16:59 +01:00
|
|
|
brw_imm_ud(GFX7_GS_PAYLOAD_INSTANCE_ID_SHIFT));
|
2014-01-25 20:55:24 +00:00
|
|
|
brw_pop_insn_state(p);
|
|
|
|
}
|
|
|
|
|
2015-10-22 23:35:15 +01:00
|
|
|
static void
|
|
|
|
generate_gs_ff_sync_set_primitives(struct brw_codegen *p,
|
|
|
|
struct brw_reg dst,
|
|
|
|
struct brw_reg src0,
|
|
|
|
struct brw_reg src1,
|
|
|
|
struct brw_reg src2)
|
2014-07-23 11:56:53 +01:00
|
|
|
{
|
|
|
|
brw_push_insn_state(p);
|
|
|
|
brw_set_default_access_mode(p, BRW_ALIGN_1);
|
|
|
|
/* Save src0 data in 16:31 bits of dst.0 */
|
|
|
|
brw_AND(p, suboffset(vec1(dst), 0), suboffset(vec1(src0), 0),
|
|
|
|
brw_imm_ud(0xffffu));
|
|
|
|
brw_SHL(p, suboffset(vec1(dst), 0), suboffset(vec1(dst), 0), brw_imm_ud(16));
|
|
|
|
/* Save src1 data in 0:15 bits of dst.0 */
|
|
|
|
brw_AND(p, suboffset(vec1(src2), 0), suboffset(vec1(src1), 0),
|
|
|
|
brw_imm_ud(0xffffu));
|
|
|
|
brw_OR(p, suboffset(vec1(dst), 0),
|
|
|
|
suboffset(vec1(dst), 0),
|
|
|
|
suboffset(vec1(src2), 0));
|
|
|
|
brw_pop_insn_state(p);
|
|
|
|
}
|
|
|
|
|
2015-10-22 23:35:15 +01:00
|
|
|
static void
|
|
|
|
generate_gs_ff_sync(struct brw_codegen *p,
|
|
|
|
vec4_instruction *inst,
|
|
|
|
struct brw_reg dst,
|
|
|
|
struct brw_reg src0,
|
|
|
|
struct brw_reg src1)
|
2014-07-09 07:46:17 +01:00
|
|
|
{
|
|
|
|
/* This opcode uses an implied MRF register for:
|
|
|
|
* - the header of the ff_sync message. And as such it is expected to be
|
|
|
|
* initialized to r0 before calling here.
|
|
|
|
* - the destination where we will write the allocated URB handle.
|
|
|
|
*/
|
|
|
|
struct brw_reg header =
|
|
|
|
retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD);
|
|
|
|
|
2014-07-23 09:51:35 +01:00
|
|
|
/* Overwrite dword 0 of the header (SO vertices to write) and
|
|
|
|
* dword 1 (number of primitives written).
|
2014-07-09 07:46:17 +01:00
|
|
|
*/
|
|
|
|
brw_push_insn_state(p);
|
|
|
|
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
|
|
|
|
brw_set_default_access_mode(p, BRW_ALIGN_1);
|
2014-07-23 09:51:35 +01:00
|
|
|
brw_MOV(p, get_element_ud(header, 0), get_element_ud(src1, 0));
|
2014-07-09 07:46:17 +01:00
|
|
|
brw_MOV(p, get_element_ud(header, 1), get_element_ud(src0, 0));
|
|
|
|
brw_pop_insn_state(p);
|
|
|
|
|
|
|
|
/* Allocate URB handle in dst */
|
|
|
|
brw_ff_sync(p,
|
|
|
|
dst,
|
|
|
|
0,
|
|
|
|
header,
|
|
|
|
1, /* allocate */
|
|
|
|
1, /* response length */
|
|
|
|
0 /* eot */);
|
|
|
|
|
|
|
|
/* Now put allocated urb handle in header.0 */
|
|
|
|
brw_push_insn_state(p);
|
|
|
|
brw_set_default_access_mode(p, BRW_ALIGN_1);
|
|
|
|
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
|
|
|
|
brw_MOV(p, get_element_ud(header, 0), get_element_ud(dst, 0));
|
2014-07-23 09:51:35 +01:00
|
|
|
|
|
|
|
/* src1 is not an immediate when we use transform feedback */
|
2015-12-15 08:34:38 +00:00
|
|
|
if (src1.file != BRW_IMMEDIATE_VALUE) {
|
|
|
|
brw_set_default_exec_size(p, BRW_EXECUTE_4);
|
2014-07-23 09:51:35 +01:00
|
|
|
brw_MOV(p, brw_vec4_grf(src1.nr, 0), brw_vec4_grf(dst.nr, 1));
|
2015-12-15 08:34:38 +00:00
|
|
|
}
|
2014-07-23 09:51:35 +01:00
|
|
|
|
2014-07-09 07:46:17 +01:00
|
|
|
brw_pop_insn_state(p);
|
|
|
|
}
|
|
|
|
|
2015-10-22 23:35:15 +01:00
|
|
|
static void
|
|
|
|
generate_gs_set_primitive_id(struct brw_codegen *p, struct brw_reg dst)
|
2014-07-24 11:14:27 +01:00
|
|
|
{
|
2021-03-29 23:40:04 +01:00
|
|
|
/* In gfx6, PrimitiveID is delivered in R0.1 of the payload */
|
2014-07-24 11:14:27 +01:00
|
|
|
struct brw_reg src = brw_vec8_grf(0, 0);
|
|
|
|
brw_push_insn_state(p);
|
|
|
|
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
|
|
|
|
brw_set_default_access_mode(p, BRW_ALIGN_1);
|
|
|
|
brw_MOV(p, get_element_ud(dst, 0), get_element_ud(src, 1));
|
|
|
|
brw_pop_insn_state(p);
|
|
|
|
}
|
|
|
|
|
2015-11-17 09:07:39 +00:00
|
|
|
static void
|
|
|
|
generate_tcs_get_instance_id(struct brw_codegen *p, struct brw_reg dst)
|
|
|
|
{
|
2021-04-05 21:19:39 +01:00
|
|
|
const struct intel_device_info *devinfo = p->devinfo;
|
2021-09-22 13:06:58 +01:00
|
|
|
const bool ivb = devinfo->platform == INTEL_PLATFORM_IVB ||
|
|
|
|
devinfo->platform == INTEL_PLATFORM_BYT;
|
2015-11-26 07:27:02 +00:00
|
|
|
|
2015-11-17 09:07:39 +00:00
|
|
|
/* "Instance Count" comes as part of the payload in r0.2 bits 23:17.
|
|
|
|
*
|
|
|
|
* Since we operate in SIMD4x2 mode, we need run half as many threads
|
|
|
|
* as necessary. So we assign (2i + 1, 2i) as the thread counts. We
|
|
|
|
* shift right by one less to accomplish the multiplication by two.
|
|
|
|
*/
|
|
|
|
dst = retype(dst, BRW_REGISTER_TYPE_UD);
|
|
|
|
struct brw_reg r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
|
|
|
|
|
|
|
|
brw_push_insn_state(p);
|
|
|
|
brw_set_default_access_mode(p, BRW_ALIGN_1);
|
|
|
|
|
2015-11-26 07:27:02 +00:00
|
|
|
const int mask = ivb ? INTEL_MASK(22, 16) : INTEL_MASK(23, 17);
|
|
|
|
const int shift = ivb ? 16 : 17;
|
2015-11-17 09:07:39 +00:00
|
|
|
|
|
|
|
brw_AND(p, get_element_ud(dst, 0), get_element_ud(r0, 2), brw_imm_ud(mask));
|
|
|
|
brw_SHR(p, get_element_ud(dst, 0), get_element_ud(dst, 0),
|
|
|
|
brw_imm_ud(shift - 1));
|
|
|
|
brw_ADD(p, get_element_ud(dst, 4), get_element_ud(dst, 0), brw_imm_ud(1));
|
|
|
|
|
|
|
|
brw_pop_insn_state(p);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
generate_tcs_urb_write(struct brw_codegen *p,
|
|
|
|
vec4_instruction *inst,
|
|
|
|
struct brw_reg urb_header)
|
|
|
|
{
|
2021-04-05 21:19:39 +01:00
|
|
|
const struct intel_device_info *devinfo = p->devinfo;
|
2015-11-17 09:07:39 +00:00
|
|
|
|
|
|
|
brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
|
|
|
|
brw_set_dest(p, send, brw_null_reg());
|
|
|
|
brw_set_src0(p, send, urb_header);
|
2018-06-11 18:49:39 +01:00
|
|
|
brw_set_desc(p, send, brw_message_desc(devinfo, inst->mlen, 0, true));
|
2015-11-17 09:07:39 +00:00
|
|
|
|
2018-06-11 18:49:39 +01:00
|
|
|
brw_inst_set_sfid(devinfo, send, BRW_SFID_URB);
|
2015-11-17 09:07:39 +00:00
|
|
|
brw_inst_set_urb_opcode(devinfo, send, BRW_URB_OPCODE_WRITE_OWORD);
|
|
|
|
brw_inst_set_urb_global_offset(devinfo, send, inst->offset);
|
2015-12-24 21:09:26 +00:00
|
|
|
if (inst->urb_write_flags & BRW_URB_WRITE_EOT) {
|
|
|
|
brw_inst_set_eot(devinfo, send, 1);
|
|
|
|
} else {
|
|
|
|
brw_inst_set_urb_per_slot_offset(devinfo, send, 1);
|
|
|
|
brw_inst_set_urb_swizzle_control(devinfo, send, BRW_URB_SWIZZLE_INTERLEAVE);
|
|
|
|
}
|
2015-11-17 09:07:39 +00:00
|
|
|
|
|
|
|
/* what happens to swizzles? */
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
generate_tcs_input_urb_offsets(struct brw_codegen *p,
|
|
|
|
struct brw_reg dst,
|
|
|
|
struct brw_reg vertex,
|
|
|
|
struct brw_reg offset)
|
|
|
|
{
|
|
|
|
/* Generates an URB read/write message header for HS/DS operation.
|
|
|
|
* Inputs are a vertex index, and a byte offset from the beginning of
|
|
|
|
* the vertex. */
|
|
|
|
|
|
|
|
/* If `vertex` is not an immediate, we clobber a0.0 */
|
|
|
|
|
|
|
|
assert(vertex.file == BRW_IMMEDIATE_VALUE || vertex.file == BRW_GENERAL_REGISTER_FILE);
|
|
|
|
assert(vertex.type == BRW_REGISTER_TYPE_UD || vertex.type == BRW_REGISTER_TYPE_D);
|
|
|
|
|
|
|
|
assert(dst.file == BRW_GENERAL_REGISTER_FILE);
|
|
|
|
|
|
|
|
brw_push_insn_state(p);
|
|
|
|
brw_set_default_access_mode(p, BRW_ALIGN_1);
|
|
|
|
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
|
|
|
|
brw_MOV(p, dst, brw_imm_ud(0));
|
|
|
|
|
|
|
|
/* m0.5 bits 8-15 are channel enables */
|
|
|
|
brw_MOV(p, get_element_ud(dst, 5), brw_imm_ud(0xff00));
|
|
|
|
|
|
|
|
/* m0.0-0.1: URB handles */
|
|
|
|
if (vertex.file == BRW_IMMEDIATE_VALUE) {
|
|
|
|
uint32_t vertex_index = vertex.ud;
|
|
|
|
struct brw_reg index_reg = brw_vec1_grf(
|
|
|
|
1 + (vertex_index >> 3), vertex_index & 7);
|
|
|
|
|
|
|
|
brw_MOV(p, vec2(get_element_ud(dst, 0)),
|
|
|
|
retype(index_reg, BRW_REGISTER_TYPE_UD));
|
|
|
|
} else {
|
|
|
|
/* Use indirect addressing. ICP Handles are DWords (single channels
|
|
|
|
* of a register) and start at g1.0.
|
|
|
|
*
|
|
|
|
* In order to start our region at g1.0, we add 8 to the vertex index,
|
|
|
|
* effectively skipping over the 8 channels in g0.0. This gives us a
|
|
|
|
* DWord offset to the ICP Handle.
|
|
|
|
*
|
|
|
|
* Indirect addressing works in terms of bytes, so we then multiply
|
|
|
|
* the DWord offset by 4 (by shifting left by 2).
|
|
|
|
*/
|
|
|
|
struct brw_reg addr = brw_address_reg(0);
|
|
|
|
|
|
|
|
/* bottom half: m0.0 = g[1.0 + vertex.0]UD */
|
2016-11-20 04:04:34 +00:00
|
|
|
brw_ADD(p, addr, retype(get_element_ud(vertex, 0), BRW_REGISTER_TYPE_UW),
|
|
|
|
brw_imm_uw(0x8));
|
|
|
|
brw_SHL(p, addr, addr, brw_imm_uw(2));
|
2015-11-17 09:07:39 +00:00
|
|
|
brw_MOV(p, get_element_ud(dst, 0), deref_1ud(brw_indirect(0, 0), 0));
|
|
|
|
|
|
|
|
/* top half: m0.1 = g[1.0 + vertex.4]UD */
|
2016-11-20 04:04:34 +00:00
|
|
|
brw_ADD(p, addr, retype(get_element_ud(vertex, 4), BRW_REGISTER_TYPE_UW),
|
|
|
|
brw_imm_uw(0x8));
|
|
|
|
brw_SHL(p, addr, addr, brw_imm_uw(2));
|
2015-11-17 09:07:39 +00:00
|
|
|
brw_MOV(p, get_element_ud(dst, 1), deref_1ud(brw_indirect(0, 0), 0));
|
|
|
|
}
|
|
|
|
|
|
|
|
/* m0.3-0.4: 128bit-granular offsets into the URB from the handles */
|
|
|
|
if (offset.file != ARF)
|
|
|
|
brw_MOV(p, vec2(get_element_ud(dst, 3)), stride(offset, 4, 1, 0));
|
|
|
|
|
|
|
|
brw_pop_insn_state(p);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
generate_tcs_output_urb_offsets(struct brw_codegen *p,
|
|
|
|
struct brw_reg dst,
|
|
|
|
struct brw_reg write_mask,
|
|
|
|
struct brw_reg offset)
|
|
|
|
{
|
|
|
|
/* Generates an URB read/write message header for HS/DS operation, for the patch URB entry. */
|
|
|
|
assert(dst.file == BRW_GENERAL_REGISTER_FILE || dst.file == BRW_MESSAGE_REGISTER_FILE);
|
|
|
|
|
|
|
|
assert(write_mask.file == BRW_IMMEDIATE_VALUE);
|
|
|
|
assert(write_mask.type == BRW_REGISTER_TYPE_UD);
|
|
|
|
|
|
|
|
brw_push_insn_state(p);
|
|
|
|
|
|
|
|
brw_set_default_access_mode(p, BRW_ALIGN_1);
|
|
|
|
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
|
|
|
|
brw_MOV(p, dst, brw_imm_ud(0));
|
|
|
|
|
|
|
|
unsigned mask = write_mask.ud;
|
|
|
|
|
|
|
|
/* m0.5 bits 15:12 and 11:8 are channel enables */
|
|
|
|
brw_MOV(p, get_element_ud(dst, 5), brw_imm_ud((mask << 8) | (mask << 12)));
|
|
|
|
|
|
|
|
/* HS patch URB handle is delivered in r0.0 */
|
|
|
|
struct brw_reg urb_handle = brw_vec1_grf(0, 0);
|
|
|
|
|
|
|
|
/* m0.0-0.1: URB handles */
|
|
|
|
brw_MOV(p, vec2(get_element_ud(dst, 0)),
|
|
|
|
retype(urb_handle, BRW_REGISTER_TYPE_UD));
|
|
|
|
|
|
|
|
/* m0.3-0.4: 128bit-granular offsets into the URB from the handles */
|
|
|
|
if (offset.file != ARF)
|
|
|
|
brw_MOV(p, vec2(get_element_ud(dst, 3)), stride(offset, 4, 1, 0));
|
|
|
|
|
|
|
|
brw_pop_insn_state(p);
|
|
|
|
}
|
|
|
|
|
2015-11-17 09:30:35 +00:00
|
|
|
static void
|
|
|
|
generate_tes_create_input_read_header(struct brw_codegen *p,
|
|
|
|
struct brw_reg dst)
|
|
|
|
{
|
|
|
|
brw_push_insn_state(p);
|
|
|
|
brw_set_default_access_mode(p, BRW_ALIGN_1);
|
|
|
|
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
|
|
|
|
|
|
|
|
/* Initialize the register to 0 */
|
|
|
|
brw_MOV(p, dst, brw_imm_ud(0));
|
|
|
|
|
|
|
|
/* Enable all the channels in m0.5 bits 15:8 */
|
|
|
|
brw_MOV(p, get_element_ud(dst, 5), brw_imm_ud(0xff00));
|
|
|
|
|
|
|
|
/* Copy g1.3 (the patch URB handle) to m0.0 and m0.1. For safety,
|
|
|
|
* mask out irrelevant "Reserved" bits, as they're not marked MBZ.
|
|
|
|
*/
|
|
|
|
brw_AND(p, vec2(get_element_ud(dst, 0)),
|
|
|
|
retype(brw_vec1_grf(1, 3), BRW_REGISTER_TYPE_UD),
|
|
|
|
brw_imm_ud(0x1fff));
|
|
|
|
brw_pop_insn_state(p);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
generate_tes_add_indirect_urb_offset(struct brw_codegen *p,
|
|
|
|
struct brw_reg dst,
|
|
|
|
struct brw_reg header,
|
|
|
|
struct brw_reg offset)
|
|
|
|
{
|
|
|
|
brw_push_insn_state(p);
|
|
|
|
brw_set_default_access_mode(p, BRW_ALIGN_1);
|
|
|
|
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
|
|
|
|
|
|
|
|
brw_MOV(p, dst, header);
|
2018-06-16 03:39:56 +01:00
|
|
|
|
|
|
|
/* Uniforms will have a stride <0;4,1>, and we need to convert to <0;1,0>.
|
|
|
|
* Other values get <4;1,0>.
|
|
|
|
*/
|
|
|
|
struct brw_reg restrided_offset;
|
|
|
|
if (offset.vstride == BRW_VERTICAL_STRIDE_0 &&
|
|
|
|
offset.width == BRW_WIDTH_4 &&
|
|
|
|
offset.hstride == BRW_HORIZONTAL_STRIDE_1) {
|
|
|
|
restrided_offset = stride(offset, 0, 1, 0);
|
|
|
|
} else {
|
|
|
|
restrided_offset = stride(offset, 4, 1, 0);
|
|
|
|
}
|
|
|
|
|
2015-11-17 09:30:35 +00:00
|
|
|
/* m0.3-0.4: 128-bit-granular offsets into the URB from the handles */
|
2018-06-16 03:39:56 +01:00
|
|
|
brw_MOV(p, vec2(get_element_ud(dst, 3)), restrided_offset);
|
2015-11-17 09:30:35 +00:00
|
|
|
|
|
|
|
brw_pop_insn_state(p);
|
|
|
|
}
|
|
|
|
|
2015-11-17 09:07:39 +00:00
|
|
|
static void
|
|
|
|
generate_vec4_urb_read(struct brw_codegen *p,
|
|
|
|
vec4_instruction *inst,
|
|
|
|
struct brw_reg dst,
|
|
|
|
struct brw_reg header)
|
|
|
|
{
|
2021-04-05 21:19:39 +01:00
|
|
|
const struct intel_device_info *devinfo = p->devinfo;
|
2015-11-17 09:07:39 +00:00
|
|
|
|
|
|
|
assert(header.file == BRW_GENERAL_REGISTER_FILE);
|
|
|
|
assert(header.type == BRW_REGISTER_TYPE_UD);
|
|
|
|
|
|
|
|
brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
|
|
|
|
brw_set_dest(p, send, dst);
|
|
|
|
brw_set_src0(p, send, header);
|
|
|
|
|
2018-06-11 18:49:39 +01:00
|
|
|
brw_set_desc(p, send, brw_message_desc(devinfo, 1, 1, true));
|
|
|
|
|
|
|
|
brw_inst_set_sfid(devinfo, send, BRW_SFID_URB);
|
2015-11-17 09:07:39 +00:00
|
|
|
brw_inst_set_urb_opcode(devinfo, send, BRW_URB_OPCODE_READ_OWORD);
|
|
|
|
brw_inst_set_urb_swizzle_control(devinfo, send, BRW_URB_SWIZZLE_INTERLEAVE);
|
|
|
|
brw_inst_set_urb_per_slot_offset(devinfo, send, 1);
|
|
|
|
|
|
|
|
brw_inst_set_urb_global_offset(devinfo, send, inst->offset);
|
|
|
|
}
|
|
|
|
|
2015-11-26 01:54:22 +00:00
|
|
|
static void
|
|
|
|
generate_tcs_release_input(struct brw_codegen *p,
|
|
|
|
struct brw_reg header,
|
|
|
|
struct brw_reg vertex,
|
|
|
|
struct brw_reg is_unpaired)
|
|
|
|
{
|
2021-04-05 21:19:39 +01:00
|
|
|
const struct intel_device_info *devinfo = p->devinfo;
|
2015-11-26 01:54:22 +00:00
|
|
|
|
|
|
|
assert(vertex.file == BRW_IMMEDIATE_VALUE);
|
|
|
|
assert(vertex.type == BRW_REGISTER_TYPE_UD);
|
|
|
|
|
|
|
|
/* m0.0-0.1: URB handles */
|
|
|
|
struct brw_reg urb_handles =
|
|
|
|
retype(brw_vec2_grf(1 + (vertex.ud >> 3), vertex.ud & 7),
|
|
|
|
BRW_REGISTER_TYPE_UD);
|
|
|
|
|
|
|
|
brw_push_insn_state(p);
|
|
|
|
brw_set_default_access_mode(p, BRW_ALIGN_1);
|
|
|
|
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
|
|
|
|
brw_MOV(p, header, brw_imm_ud(0));
|
|
|
|
brw_MOV(p, vec2(get_element_ud(header, 0)), urb_handles);
|
|
|
|
brw_pop_insn_state(p);
|
|
|
|
|
|
|
|
brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
|
|
|
|
brw_set_dest(p, send, brw_null_reg());
|
|
|
|
brw_set_src0(p, send, header);
|
2018-06-11 18:49:39 +01:00
|
|
|
brw_set_desc(p, send, brw_message_desc(devinfo, 1, 0, true));
|
|
|
|
|
|
|
|
brw_inst_set_sfid(devinfo, send, BRW_SFID_URB);
|
2015-11-26 01:54:22 +00:00
|
|
|
brw_inst_set_urb_opcode(devinfo, send, BRW_URB_OPCODE_READ_OWORD);
|
|
|
|
brw_inst_set_urb_complete(devinfo, send, 1);
|
|
|
|
brw_inst_set_urb_swizzle_control(devinfo, send, is_unpaired.ud ?
|
|
|
|
BRW_URB_SWIZZLE_NONE :
|
|
|
|
BRW_URB_SWIZZLE_INTERLEAVE);
|
|
|
|
}
|
|
|
|
|
2015-12-24 21:09:26 +00:00
|
|
|
static void
|
|
|
|
generate_tcs_thread_end(struct brw_codegen *p, vec4_instruction *inst)
|
|
|
|
{
|
|
|
|
struct brw_reg header = brw_message_reg(inst->base_mrf);
|
|
|
|
|
|
|
|
brw_push_insn_state(p);
|
|
|
|
brw_set_default_access_mode(p, BRW_ALIGN_1);
|
|
|
|
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
|
|
|
|
brw_MOV(p, header, brw_imm_ud(0));
|
2016-01-05 09:53:57 +00:00
|
|
|
brw_MOV(p, get_element_ud(header, 5), brw_imm_ud(WRITEMASK_X << 8));
|
2015-12-24 21:09:26 +00:00
|
|
|
brw_MOV(p, get_element_ud(header, 0),
|
|
|
|
retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD));
|
2016-01-05 09:53:57 +00:00
|
|
|
brw_MOV(p, brw_message_reg(inst->base_mrf + 1), brw_imm_ud(0u));
|
2015-12-24 21:09:26 +00:00
|
|
|
brw_pop_insn_state(p);
|
|
|
|
|
|
|
|
brw_urb_WRITE(p,
|
|
|
|
brw_null_reg(), /* dest */
|
|
|
|
inst->base_mrf, /* starting mrf reg nr */
|
|
|
|
header,
|
2016-01-05 09:53:57 +00:00
|
|
|
BRW_URB_WRITE_EOT | BRW_URB_WRITE_OWORD |
|
|
|
|
BRW_URB_WRITE_USE_CHANNEL_MASKS,
|
2015-12-24 21:09:26 +00:00
|
|
|
inst->mlen,
|
|
|
|
0, /* response len */
|
|
|
|
0, /* urb destination offset */
|
|
|
|
0);
|
|
|
|
}
|
|
|
|
|
2015-11-17 09:30:35 +00:00
|
|
|
static void
|
|
|
|
generate_tes_get_primitive_id(struct brw_codegen *p, struct brw_reg dst)
|
|
|
|
{
|
|
|
|
brw_push_insn_state(p);
|
|
|
|
brw_set_default_access_mode(p, BRW_ALIGN_1);
|
|
|
|
brw_MOV(p, dst, retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_D));
|
|
|
|
brw_pop_insn_state(p);
|
|
|
|
}
|
|
|
|
|
2015-11-17 09:07:39 +00:00
|
|
|
static void
|
|
|
|
generate_tcs_get_primitive_id(struct brw_codegen *p, struct brw_reg dst)
|
|
|
|
{
|
|
|
|
brw_push_insn_state(p);
|
|
|
|
brw_set_default_access_mode(p, BRW_ALIGN_1);
|
|
|
|
brw_MOV(p, dst, retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD));
|
|
|
|
brw_pop_insn_state(p);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
generate_tcs_create_barrier_header(struct brw_codegen *p,
|
|
|
|
struct brw_vue_prog_data *prog_data,
|
|
|
|
struct brw_reg dst)
|
|
|
|
{
|
2021-04-05 21:19:39 +01:00
|
|
|
const struct intel_device_info *devinfo = p->devinfo;
|
2021-09-22 13:06:58 +01:00
|
|
|
const bool ivb = devinfo->platform == INTEL_PLATFORM_IVB ||
|
|
|
|
devinfo->platform == INTEL_PLATFORM_BYT;
|
2015-11-17 09:07:39 +00:00
|
|
|
struct brw_reg m0_2 = get_element_ud(dst, 2);
|
|
|
|
unsigned instances = ((struct brw_tcs_prog_data *) prog_data)->instances;
|
|
|
|
|
|
|
|
brw_push_insn_state(p);
|
|
|
|
brw_set_default_access_mode(p, BRW_ALIGN_1);
|
|
|
|
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
|
|
|
|
|
|
|
|
/* Zero the message header */
|
|
|
|
brw_MOV(p, retype(dst, BRW_REGISTER_TYPE_UD), brw_imm_ud(0u));
|
|
|
|
|
2021-03-29 23:46:12 +01:00
|
|
|
/* Copy "Barrier ID" from r0.2, bits 16:13 (Gfx7.5+) or 15:12 (Gfx7) */
|
2015-11-17 09:07:39 +00:00
|
|
|
brw_AND(p, m0_2,
|
|
|
|
retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD),
|
2015-12-24 23:26:55 +00:00
|
|
|
brw_imm_ud(ivb ? INTEL_MASK(15, 12) : INTEL_MASK(16, 13)));
|
2015-11-17 09:07:39 +00:00
|
|
|
|
2015-12-24 23:26:55 +00:00
|
|
|
/* Shift it up to bits 27:24. */
|
|
|
|
brw_SHL(p, m0_2, get_element_ud(dst, 2), brw_imm_ud(ivb ? 12 : 11));
|
2015-11-17 09:07:39 +00:00
|
|
|
|
|
|
|
/* Set the Barrier Count and the enable bit */
|
|
|
|
brw_OR(p, m0_2, m0_2, brw_imm_ud(instances << 9 | (1 << 15)));
|
|
|
|
|
|
|
|
brw_pop_insn_state(p);
|
|
|
|
}
|
|
|
|
|
2015-10-22 23:35:15 +01:00
|
|
|
static void
|
|
|
|
generate_oword_dual_block_offsets(struct brw_codegen *p,
|
|
|
|
struct brw_reg m1,
|
|
|
|
struct brw_reg index)
|
2011-08-07 21:36:11 +01:00
|
|
|
{
|
|
|
|
int second_vertex_offset;
|
|
|
|
|
2021-03-29 22:41:58 +01:00
|
|
|
if (p->devinfo->ver >= 6)
|
2011-08-07 21:36:11 +01:00
|
|
|
second_vertex_offset = 1;
|
|
|
|
else
|
|
|
|
second_vertex_offset = 16;
|
|
|
|
|
|
|
|
m1 = retype(m1, BRW_REGISTER_TYPE_D);
|
|
|
|
|
|
|
|
/* Set up M1 (message payload). Only the block offsets in M1.0 and
|
|
|
|
* M1.4 are used, and the rest are ignored.
|
|
|
|
*/
|
|
|
|
struct brw_reg m1_0 = suboffset(vec1(m1), 0);
|
|
|
|
struct brw_reg m1_4 = suboffset(vec1(m1), 4);
|
|
|
|
struct brw_reg index_0 = suboffset(vec1(index), 0);
|
|
|
|
struct brw_reg index_4 = suboffset(vec1(index), 4);
|
|
|
|
|
|
|
|
brw_push_insn_state(p);
|
2014-06-01 00:57:02 +01:00
|
|
|
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
|
|
|
|
brw_set_default_access_mode(p, BRW_ALIGN_1);
|
2011-08-07 21:36:11 +01:00
|
|
|
|
|
|
|
brw_MOV(p, m1_0, index_0);
|
|
|
|
|
|
|
|
if (index.file == BRW_IMMEDIATE_VALUE) {
|
2015-10-23 03:41:30 +01:00
|
|
|
index_4.ud += second_vertex_offset;
|
2011-08-07 21:36:11 +01:00
|
|
|
brw_MOV(p, m1_4, index_4);
|
|
|
|
} else {
|
|
|
|
brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset));
|
|
|
|
}
|
|
|
|
|
|
|
|
brw_pop_insn_state(p);
|
|
|
|
}
|
|
|
|
|
2015-10-22 23:35:15 +01:00
|
|
|
static void
|
|
|
|
generate_unpack_flags(struct brw_codegen *p,
|
|
|
|
struct brw_reg dst)
|
2013-08-07 19:31:33 +01:00
|
|
|
{
|
|
|
|
brw_push_insn_state(p);
|
2014-06-01 00:57:02 +01:00
|
|
|
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
|
|
|
|
brw_set_default_access_mode(p, BRW_ALIGN_1);
|
2013-08-07 19:31:33 +01:00
|
|
|
|
|
|
|
struct brw_reg flags = brw_flag_reg(0, 0);
|
|
|
|
struct brw_reg dst_0 = suboffset(vec1(dst), 0);
|
|
|
|
struct brw_reg dst_4 = suboffset(vec1(dst), 4);
|
|
|
|
|
|
|
|
brw_AND(p, dst_0, flags, brw_imm_ud(0x0f));
|
|
|
|
brw_AND(p, dst_4, flags, brw_imm_ud(0xf0));
|
|
|
|
brw_SHR(p, dst_4, dst_4, brw_imm_ud(4));
|
|
|
|
|
|
|
|
brw_pop_insn_state(p);
|
|
|
|
}
|
|
|
|
|
2015-10-22 23:35:15 +01:00
|
|
|
static void
|
|
|
|
generate_scratch_read(struct brw_codegen *p,
|
|
|
|
vec4_instruction *inst,
|
|
|
|
struct brw_reg dst,
|
|
|
|
struct brw_reg index)
|
2011-08-07 21:36:11 +01:00
|
|
|
{
|
2021-04-05 21:19:39 +01:00
|
|
|
const struct intel_device_info *devinfo = p->devinfo;
|
2011-08-31 00:47:43 +01:00
|
|
|
struct brw_reg header = brw_vec8_grf(0, 0);
|
|
|
|
|
2021-03-29 23:40:04 +01:00
|
|
|
gfx6_resolve_implied_move(p, &header, inst->base_mrf);
|
2011-08-07 21:36:11 +01:00
|
|
|
|
2015-10-22 23:35:15 +01:00
|
|
|
generate_oword_dual_block_offsets(p, brw_message_reg(inst->base_mrf + 1),
|
2011-08-07 21:36:11 +01:00
|
|
|
index);
|
|
|
|
|
|
|
|
uint32_t msg_type;
|
|
|
|
|
2021-03-29 22:41:58 +01:00
|
|
|
if (devinfo->ver >= 6)
|
2021-03-29 23:16:59 +01:00
|
|
|
msg_type = GFX6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
|
2021-09-22 13:06:58 +01:00
|
|
|
else if (devinfo->verx10 >= 45)
|
2011-08-07 21:36:11 +01:00
|
|
|
msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
|
|
|
|
else
|
|
|
|
msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
|
|
|
|
|
2015-04-23 12:36:16 +01:00
|
|
|
const unsigned target_cache =
|
2021-03-29 23:16:59 +01:00
|
|
|
devinfo->ver >= 7 ? GFX7_SFID_DATAPORT_DATA_CACHE :
|
|
|
|
devinfo->ver >= 6 ? GFX6_SFID_DATAPORT_RENDER_CACHE :
|
2018-06-07 18:50:20 +01:00
|
|
|
BRW_SFID_DATAPORT_READ;
|
2016-07-22 02:49:36 +01:00
|
|
|
|
2011-08-07 21:36:11 +01:00
|
|
|
/* Each of the 8 channel enables is considered for whether each
|
|
|
|
* dword is written.
|
|
|
|
*/
|
2014-06-13 22:29:25 +01:00
|
|
|
brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
|
2018-06-07 18:50:20 +01:00
|
|
|
brw_inst_set_sfid(devinfo, send, target_cache);
|
2011-08-07 21:36:11 +01:00
|
|
|
brw_set_dest(p, send, dst);
|
2011-08-31 00:47:43 +01:00
|
|
|
brw_set_src0(p, send, header);
|
2021-03-29 22:41:58 +01:00
|
|
|
if (devinfo->ver < 6)
|
2015-10-22 23:35:15 +01:00
|
|
|
brw_inst_set_cond_modifier(devinfo, send, inst->base_mrf);
|
2018-06-07 18:50:20 +01:00
|
|
|
brw_set_desc(p, send,
|
|
|
|
brw_message_desc(devinfo, 2, 1, true) |
|
|
|
|
brw_dp_read_desc(devinfo,
|
|
|
|
brw_scratch_surface_idx(p),
|
|
|
|
BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
|
|
|
|
msg_type, BRW_DATAPORT_READ_TARGET_RENDER_CACHE));
|
2011-08-07 21:36:11 +01:00
|
|
|
}
|
|
|
|
|
2015-10-22 23:35:15 +01:00
|
|
|
static void
|
|
|
|
generate_scratch_write(struct brw_codegen *p,
|
|
|
|
vec4_instruction *inst,
|
|
|
|
struct brw_reg dst,
|
|
|
|
struct brw_reg src,
|
|
|
|
struct brw_reg index)
|
2011-08-07 21:36:11 +01:00
|
|
|
{
|
2021-04-05 21:19:39 +01:00
|
|
|
const struct intel_device_info *devinfo = p->devinfo;
|
2015-04-23 12:36:16 +01:00
|
|
|
const unsigned target_cache =
|
2021-03-29 23:16:59 +01:00
|
|
|
(devinfo->ver >= 7 ? GFX7_SFID_DATAPORT_DATA_CACHE :
|
|
|
|
devinfo->ver >= 6 ? GFX6_SFID_DATAPORT_RENDER_CACHE :
|
2018-07-10 00:12:59 +01:00
|
|
|
BRW_SFID_DATAPORT_WRITE);
|
2011-08-31 00:47:43 +01:00
|
|
|
struct brw_reg header = brw_vec8_grf(0, 0);
|
2011-08-31 01:56:33 +01:00
|
|
|
bool write_commit;
|
2011-08-31 00:47:43 +01:00
|
|
|
|
2011-08-07 21:36:11 +01:00
|
|
|
/* If the instruction is predicated, we'll predicate the send, not
|
|
|
|
* the header setup.
|
|
|
|
*/
|
2018-06-07 23:32:15 +01:00
|
|
|
brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
|
2011-08-07 21:36:11 +01:00
|
|
|
|
2021-03-29 23:40:04 +01:00
|
|
|
gfx6_resolve_implied_move(p, &header, inst->base_mrf);
|
2011-08-07 21:36:11 +01:00
|
|
|
|
2015-10-22 23:35:15 +01:00
|
|
|
generate_oword_dual_block_offsets(p, brw_message_reg(inst->base_mrf + 1),
|
2011-08-07 21:36:11 +01:00
|
|
|
index);
|
|
|
|
|
|
|
|
brw_MOV(p,
|
|
|
|
retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D),
|
|
|
|
retype(src, BRW_REGISTER_TYPE_D));
|
|
|
|
|
|
|
|
uint32_t msg_type;
|
|
|
|
|
2021-03-29 22:41:58 +01:00
|
|
|
if (devinfo->ver >= 7)
|
2021-03-29 23:16:59 +01:00
|
|
|
msg_type = GFX7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE;
|
2021-03-29 22:41:58 +01:00
|
|
|
else if (devinfo->ver == 6)
|
2021-03-29 23:16:59 +01:00
|
|
|
msg_type = GFX6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
|
2011-08-07 21:36:11 +01:00
|
|
|
else
|
|
|
|
msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
|
|
|
|
|
2014-06-01 00:57:02 +01:00
|
|
|
brw_set_default_predicate_control(p, inst->predicate);
|
2011-08-07 21:36:11 +01:00
|
|
|
|
2021-03-29 23:40:04 +01:00
|
|
|
/* Pre-gfx6, we have to specify write commits to ensure ordering
|
2011-08-31 01:56:33 +01:00
|
|
|
* between reads and writes within a thread. Afterwards, that's
|
|
|
|
* guaranteed and write commits only matter for inter-thread
|
|
|
|
* synchronization.
|
|
|
|
*/
|
2021-03-29 22:41:58 +01:00
|
|
|
if (devinfo->ver >= 6) {
|
2011-08-31 01:56:33 +01:00
|
|
|
write_commit = false;
|
|
|
|
} else {
|
|
|
|
/* The visitor set up our destination register to be g0. This
|
|
|
|
* means that when the next read comes along, we will end up
|
|
|
|
* reading from g0 and causing a block on the write commit. For
|
|
|
|
* write-after-read, we are relying on the value of the previous
|
|
|
|
* read being used (and thus blocking on completion) before our
|
|
|
|
* write is executed. This means we have to be careful in
|
|
|
|
* instruction scheduling to not violate this assumption.
|
|
|
|
*/
|
|
|
|
write_commit = true;
|
|
|
|
}
|
|
|
|
|
2011-08-07 21:36:11 +01:00
|
|
|
/* Each of the 8 channel enables is considered for whether each
|
|
|
|
* dword is written.
|
|
|
|
*/
|
2014-06-13 22:29:25 +01:00
|
|
|
brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
|
2018-07-10 00:12:59 +01:00
|
|
|
brw_inst_set_sfid(p->devinfo, send, target_cache);
|
2011-08-07 21:36:11 +01:00
|
|
|
brw_set_dest(p, send, dst);
|
2011-08-31 00:47:43 +01:00
|
|
|
brw_set_src0(p, send, header);
|
2021-03-29 22:41:58 +01:00
|
|
|
if (devinfo->ver < 6)
|
2015-04-15 02:00:06 +01:00
|
|
|
brw_inst_set_cond_modifier(p->devinfo, send, inst->base_mrf);
|
2018-07-10 00:12:59 +01:00
|
|
|
brw_set_desc(p, send,
|
|
|
|
brw_message_desc(devinfo, 3, write_commit, true) |
|
|
|
|
brw_dp_write_desc(devinfo,
|
|
|
|
brw_scratch_surface_idx(p),
|
|
|
|
BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
|
|
|
|
msg_type,
|
|
|
|
write_commit));
|
2011-08-07 21:36:11 +01:00
|
|
|
}
|
|
|
|
|
2015-10-22 23:35:15 +01:00
|
|
|
static void
|
|
|
|
generate_pull_constant_load(struct brw_codegen *p,
|
|
|
|
vec4_instruction *inst,
|
|
|
|
struct brw_reg dst,
|
|
|
|
struct brw_reg index,
|
|
|
|
struct brw_reg offset)
|
2011-08-22 18:35:24 +01:00
|
|
|
{
|
2021-04-05 21:19:39 +01:00
|
|
|
const struct intel_device_info *devinfo = p->devinfo;
|
2015-04-23 12:36:16 +01:00
|
|
|
const unsigned target_cache =
|
2021-03-29 23:16:59 +01:00
|
|
|
(devinfo->ver >= 6 ? GFX6_SFID_DATAPORT_SAMPLER_CACHE :
|
2018-06-07 18:50:20 +01:00
|
|
|
BRW_SFID_DATAPORT_READ);
|
2012-06-25 22:36:28 +01:00
|
|
|
assert(index.file == BRW_IMMEDIATE_VALUE &&
|
|
|
|
index.type == BRW_REGISTER_TYPE_UD);
|
2015-10-23 03:41:30 +01:00
|
|
|
uint32_t surf_index = index.ud;
|
2012-06-25 22:36:28 +01:00
|
|
|
|
2011-08-22 18:35:24 +01:00
|
|
|
struct brw_reg header = brw_vec8_grf(0, 0);
|
|
|
|
|
2021-03-29 23:40:04 +01:00
|
|
|
gfx6_resolve_implied_move(p, &header, inst->base_mrf);
|
2011-08-22 18:35:24 +01:00
|
|
|
|
2021-03-29 22:41:58 +01:00
|
|
|
if (devinfo->ver >= 6) {
|
2015-11-24 00:01:44 +00:00
|
|
|
if (offset.file == BRW_IMMEDIATE_VALUE) {
|
|
|
|
brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1),
|
|
|
|
BRW_REGISTER_TYPE_D),
|
|
|
|
brw_imm_d(offset.ud >> 4));
|
|
|
|
} else {
|
|
|
|
brw_SHR(p, retype(brw_message_reg(inst->base_mrf + 1),
|
|
|
|
BRW_REGISTER_TYPE_D),
|
|
|
|
offset, brw_imm_d(4));
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1),
|
|
|
|
BRW_REGISTER_TYPE_D),
|
|
|
|
offset);
|
|
|
|
}
|
2011-08-22 18:35:24 +01:00
|
|
|
|
|
|
|
uint32_t msg_type;
|
|
|
|
|
2021-03-29 22:41:58 +01:00
|
|
|
if (devinfo->ver >= 6)
|
2021-03-29 23:16:59 +01:00
|
|
|
msg_type = GFX6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
|
2021-09-22 13:06:58 +01:00
|
|
|
else if (devinfo->verx10 >= 45)
|
2011-08-22 18:35:24 +01:00
|
|
|
msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
|
|
|
|
else
|
|
|
|
msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
|
|
|
|
|
|
|
|
/* Each of the 8 channel enables is considered for whether each
|
|
|
|
* dword is written.
|
|
|
|
*/
|
2014-06-13 22:29:25 +01:00
|
|
|
brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
|
2018-06-07 18:50:20 +01:00
|
|
|
brw_inst_set_sfid(devinfo, send, target_cache);
|
2011-08-22 18:35:24 +01:00
|
|
|
brw_set_dest(p, send, dst);
|
|
|
|
brw_set_src0(p, send, header);
|
2021-03-29 22:41:58 +01:00
|
|
|
if (devinfo->ver < 6)
|
2015-04-15 02:00:06 +01:00
|
|
|
brw_inst_set_cond_modifier(p->devinfo, send, inst->base_mrf);
|
2018-06-07 18:50:20 +01:00
|
|
|
brw_set_desc(p, send,
|
|
|
|
brw_message_desc(devinfo, 2, 1, true) |
|
|
|
|
brw_dp_read_desc(devinfo, surf_index,
|
|
|
|
BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
|
|
|
|
msg_type,
|
|
|
|
BRW_DATAPORT_READ_TARGET_DATA_CACHE));
|
2011-08-22 18:35:24 +01:00
|
|
|
}
|
|
|
|
|
2015-10-22 23:35:15 +01:00
|
|
|
static void
|
|
|
|
generate_get_buffer_size(struct brw_codegen *p,
|
|
|
|
vec4_instruction *inst,
|
|
|
|
struct brw_reg dst,
|
|
|
|
struct brw_reg src,
|
|
|
|
struct brw_reg surf_index)
|
2015-08-28 08:39:49 +01:00
|
|
|
{
|
2021-03-29 22:41:58 +01:00
|
|
|
assert(p->devinfo->ver >= 7);
|
2015-08-28 08:39:49 +01:00
|
|
|
assert(surf_index.type == BRW_REGISTER_TYPE_UD &&
|
|
|
|
surf_index.file == BRW_IMMEDIATE_VALUE);
|
|
|
|
|
|
|
|
brw_SAMPLE(p,
|
|
|
|
dst,
|
|
|
|
inst->base_mrf,
|
|
|
|
src,
|
2015-10-23 03:41:30 +01:00
|
|
|
surf_index.ud,
|
2015-08-28 08:39:49 +01:00
|
|
|
0,
|
2021-03-29 23:16:59 +01:00
|
|
|
GFX5_SAMPLER_MESSAGE_SAMPLE_RESINFO,
|
2015-08-28 08:39:49 +01:00
|
|
|
1, /* response length */
|
|
|
|
inst->mlen,
|
|
|
|
inst->header_size > 0,
|
|
|
|
BRW_SAMPLER_SIMD_MODE_SIMD4X2,
|
|
|
|
BRW_SAMPLER_RETURN_FORMAT_SINT32);
|
|
|
|
}
|
|
|
|
|
2015-10-22 23:35:15 +01:00
|
|
|
static void
|
2021-03-29 23:40:04 +01:00
|
|
|
generate_pull_constant_load_gfx7(struct brw_codegen *p,
|
2015-10-22 23:35:15 +01:00
|
|
|
vec4_instruction *inst,
|
|
|
|
struct brw_reg dst,
|
|
|
|
struct brw_reg surf_index,
|
|
|
|
struct brw_reg offset)
|
2013-04-04 22:10:18 +01:00
|
|
|
{
|
2021-04-05 21:19:39 +01:00
|
|
|
const struct intel_device_info *devinfo = p->devinfo;
|
2014-07-13 00:43:11 +01:00
|
|
|
assert(surf_index.type == BRW_REGISTER_TYPE_UD);
|
2013-04-04 22:10:18 +01:00
|
|
|
|
2014-07-13 00:43:11 +01:00
|
|
|
if (surf_index.file == BRW_IMMEDIATE_VALUE) {
|
i965/vs: Rework binding table size calculation.
Unlike the FS, the VS backend already computed the binding table size.
However, it did so poorly: after compilation, it looked to see if any
pull constants/textures/UBOs were in use, and set num_surfaces to the
maximum surface index for that category. If the VS only used a single
texture or UBO, this overcounted by quite a bit.
The shader time surface was also noted at state upload time (during
drawing), not at compile time, which is inefficient. I believe it also
had an off by one error.
This patch computes it accurately, while also simplifying the code.
It also renames num_surfaces to binding_table_size, since num_surfaces
wasn't actually the number of surfaces used. For example, a VS that
used one UBO and no other surfaces would have set num_surfaces to
SURF_INDEX_VS_UBO(1) == 18, rather than 1. A bit of a misnomer there.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-08-15 04:25:40 +01:00
|
|
|
|
2014-07-13 00:43:11 +01:00
|
|
|
brw_inst *insn = brw_next_insn(p, BRW_OPCODE_SEND);
|
2018-06-02 23:15:15 +01:00
|
|
|
brw_inst_set_sfid(devinfo, insn, BRW_SFID_SAMPLER);
|
2014-07-13 00:43:11 +01:00
|
|
|
brw_set_dest(p, insn, dst);
|
2015-03-24 15:52:20 +00:00
|
|
|
brw_set_src0(p, insn, offset);
|
2018-06-02 23:15:15 +01:00
|
|
|
brw_set_desc(p, insn,
|
|
|
|
brw_message_desc(devinfo, inst->mlen, 1, inst->header_size) |
|
|
|
|
brw_sampler_desc(devinfo, surf_index.ud,
|
|
|
|
0, /* LD message ignores sampler unit */
|
2021-03-29 23:16:59 +01:00
|
|
|
GFX5_SAMPLER_MESSAGE_SAMPLE_LD,
|
2018-06-02 23:15:15 +01:00
|
|
|
BRW_SAMPLER_SIMD_MODE_SIMD4X2, 0));
|
2014-07-13 00:43:11 +01:00
|
|
|
} else {
|
|
|
|
|
|
|
|
struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
|
|
|
|
|
|
|
|
brw_push_insn_state(p);
|
|
|
|
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
|
|
|
|
brw_set_default_access_mode(p, BRW_ALIGN_1);
|
|
|
|
|
|
|
|
/* a0.0 = surf_index & 0xff */
|
|
|
|
brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
|
2018-06-02 23:15:15 +01:00
|
|
|
brw_inst_set_exec_size(devinfo, insn_and, BRW_EXECUTE_1);
|
2014-07-13 00:43:11 +01:00
|
|
|
brw_set_dest(p, insn_and, addr);
|
|
|
|
brw_set_src0(p, insn_and, vec1(retype(surf_index, BRW_REGISTER_TYPE_UD)));
|
|
|
|
brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
|
|
|
|
|
2015-02-26 15:24:03 +00:00
|
|
|
brw_pop_insn_state(p);
|
|
|
|
|
i965: Factor out logic to build a send message instruction with indirect descriptor.
This is going to be useful because the Gen7+ uniform and varying pull
constant, texturing, typed and untyped surface read, write, and atomic
generation code on the vec4 and fs back-end all require the same logic
to handle conditionally indirect surface indices. In pseudocode:
| if (surface.file == BRW_IMMEDIATE_VALUE) {
| inst = brw_SEND(p, dst, payload);
| set_descriptor_control_bits(inst, surface, ...);
| } else {
| inst = brw_OR(p, addr, surface, 0);
| set_descriptor_control_bits(inst, ...);
| inst = brw_SEND(p, dst, payload);
| set_indirect_send_descriptor(inst, addr);
| }
This patch abstracts out this frequently recurring pattern so we can
now write:
| inst = brw_send_indirect_message(p, sfid, dst, payload, surface)
| set_descriptor_control_bits(inst, ...);
without worrying about handling the immediate and indirect surface
index cases explicitly.
v2: Rebase. Improve documentatation and commit message. (Topi)
Preserve UW destination type cargo-cult. (Topi, Ken, Matt)
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2015-03-19 13:44:24 +00:00
|
|
|
/* dst = send(offset, a0.0 | <descriptor>) */
|
2018-06-02 23:15:15 +01:00
|
|
|
brw_send_indirect_message(
|
|
|
|
p, BRW_SFID_SAMPLER, dst, offset, addr,
|
|
|
|
brw_message_desc(devinfo, inst->mlen, 1, inst->header_size) |
|
|
|
|
brw_sampler_desc(devinfo,
|
|
|
|
0 /* surface */,
|
|
|
|
0 /* sampler */,
|
2021-03-29 23:16:59 +01:00
|
|
|
GFX5_SAMPLER_MESSAGE_SAMPLE_LD,
|
2018-06-02 23:15:15 +01:00
|
|
|
BRW_SAMPLER_SIMD_MODE_SIMD4X2,
|
2019-02-07 23:45:51 +00:00
|
|
|
0),
|
|
|
|
false /* EOT */);
|
2014-07-13 00:43:11 +01:00
|
|
|
}
|
2013-04-04 22:10:18 +01:00
|
|
|
}
|
|
|
|
|
2015-11-24 05:39:15 +00:00
|
|
|
static void
|
|
|
|
generate_mov_indirect(struct brw_codegen *p,
|
intel/compiler: Silence unused parameter warnings in generate_foo methods
Since all of the fs_generator::generate_foo methods take a fs_inst * as
the first parameter, just remove the name to quiet the compiler.
src/intel/compiler/brw_fs_generator.cpp: In member function ‘void fs_generator::generate_barrier(fs_inst*, brw_reg)’:
src/intel/compiler/brw_fs_generator.cpp:743:41: warning: unused parameter ‘inst’ [-Wunused-parameter]
fs_generator::generate_barrier(fs_inst *inst, struct brw_reg src)
^~~~
src/intel/compiler/brw_fs_generator.cpp: In member function ‘void fs_generator::generate_discard_jump(fs_inst*)’:
src/intel/compiler/brw_fs_generator.cpp:1326:46: warning: unused parameter ‘inst’ [-Wunused-parameter]
fs_generator::generate_discard_jump(fs_inst *inst)
^~~~
src/intel/compiler/brw_fs_generator.cpp: In member function ‘void fs_generator::generate_pack_half_2x16_split(fs_inst*, brw_reg, brw_reg, brw_reg)’:
src/intel/compiler/brw_fs_generator.cpp:1675:54: warning: unused parameter ‘inst’ [-Wunused-parameter]
fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
^~~~
src/intel/compiler/brw_fs_generator.cpp: In member function ‘void fs_generator::generate_shader_time_add(fs_inst*, brw_reg, brw_reg, brw_reg)’:
src/intel/compiler/brw_fs_generator.cpp:1743:49: warning: unused parameter ‘inst’ [-Wunused-parameter]
fs_generator::generate_shader_time_add(fs_inst *inst,
^~~~
src/intel/compiler/brw_vec4_generator.cpp: In function ‘void generate_set_simd4x2_header_gen9(brw_codegen*, brw::vec4_instruction*, brw_reg)’:
src/intel/compiler/brw_vec4_generator.cpp:1412:52: warning: unused parameter ‘inst’ [-Wunused-parameter]
vec4_instruction *inst,
^~~~
src/intel/compiler/brw_vec4_generator.cpp: In function ‘void generate_mov_indirect(brw_codegen*, brw::vec4_instruction*, brw_reg, brw_reg, brw_reg, brw_reg)’:
src/intel/compiler/brw_vec4_generator.cpp:1430:41: warning: unused parameter ‘inst’ [-Wunused-parameter]
vec4_instruction *inst,
^~~~
src/intel/compiler/brw_vec4_generator.cpp:1432:63: warning: unused parameter ‘length’ [-Wunused-parameter]
struct brw_reg indirect, struct brw_reg length)
^~~~~~
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-03-29 00:29:45 +01:00
|
|
|
vec4_instruction *,
|
2015-11-24 05:39:15 +00:00
|
|
|
struct brw_reg dst, struct brw_reg reg,
|
intel/compiler: Silence unused parameter warnings in generate_foo methods
Since all of the fs_generator::generate_foo methods take a fs_inst * as
the first parameter, just remove the name to quiet the compiler.
src/intel/compiler/brw_fs_generator.cpp: In member function ‘void fs_generator::generate_barrier(fs_inst*, brw_reg)’:
src/intel/compiler/brw_fs_generator.cpp:743:41: warning: unused parameter ‘inst’ [-Wunused-parameter]
fs_generator::generate_barrier(fs_inst *inst, struct brw_reg src)
^~~~
src/intel/compiler/brw_fs_generator.cpp: In member function ‘void fs_generator::generate_discard_jump(fs_inst*)’:
src/intel/compiler/brw_fs_generator.cpp:1326:46: warning: unused parameter ‘inst’ [-Wunused-parameter]
fs_generator::generate_discard_jump(fs_inst *inst)
^~~~
src/intel/compiler/brw_fs_generator.cpp: In member function ‘void fs_generator::generate_pack_half_2x16_split(fs_inst*, brw_reg, brw_reg, brw_reg)’:
src/intel/compiler/brw_fs_generator.cpp:1675:54: warning: unused parameter ‘inst’ [-Wunused-parameter]
fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
^~~~
src/intel/compiler/brw_fs_generator.cpp: In member function ‘void fs_generator::generate_shader_time_add(fs_inst*, brw_reg, brw_reg, brw_reg)’:
src/intel/compiler/brw_fs_generator.cpp:1743:49: warning: unused parameter ‘inst’ [-Wunused-parameter]
fs_generator::generate_shader_time_add(fs_inst *inst,
^~~~
src/intel/compiler/brw_vec4_generator.cpp: In function ‘void generate_set_simd4x2_header_gen9(brw_codegen*, brw::vec4_instruction*, brw_reg)’:
src/intel/compiler/brw_vec4_generator.cpp:1412:52: warning: unused parameter ‘inst’ [-Wunused-parameter]
vec4_instruction *inst,
^~~~
src/intel/compiler/brw_vec4_generator.cpp: In function ‘void generate_mov_indirect(brw_codegen*, brw::vec4_instruction*, brw_reg, brw_reg, brw_reg, brw_reg)’:
src/intel/compiler/brw_vec4_generator.cpp:1430:41: warning: unused parameter ‘inst’ [-Wunused-parameter]
vec4_instruction *inst,
^~~~
src/intel/compiler/brw_vec4_generator.cpp:1432:63: warning: unused parameter ‘length’ [-Wunused-parameter]
struct brw_reg indirect, struct brw_reg length)
^~~~~~
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-03-29 00:29:45 +01:00
|
|
|
struct brw_reg indirect)
|
2015-11-24 05:39:15 +00:00
|
|
|
{
|
|
|
|
assert(indirect.type == BRW_REGISTER_TYPE_UD);
|
2021-03-29 22:41:58 +01:00
|
|
|
assert(p->devinfo->ver >= 6);
|
2015-11-24 05:39:15 +00:00
|
|
|
|
|
|
|
unsigned imm_byte_offset = reg.nr * REG_SIZE + reg.subnr * (REG_SIZE / 2);
|
|
|
|
|
|
|
|
/* This instruction acts in align1 mode */
|
|
|
|
assert(dst.writemask == WRITEMASK_XYZW);
|
|
|
|
|
|
|
|
if (indirect.file == BRW_IMMEDIATE_VALUE) {
|
|
|
|
imm_byte_offset += indirect.ud;
|
|
|
|
|
|
|
|
reg.nr = imm_byte_offset / REG_SIZE;
|
|
|
|
reg.subnr = (imm_byte_offset / (REG_SIZE / 2)) % 2;
|
|
|
|
unsigned shift = (imm_byte_offset / 4) % 4;
|
|
|
|
reg.swizzle += BRW_SWIZZLE4(shift, shift, shift, shift);
|
|
|
|
|
|
|
|
brw_MOV(p, dst, reg);
|
|
|
|
} else {
|
|
|
|
brw_push_insn_state(p);
|
|
|
|
brw_set_default_access_mode(p, BRW_ALIGN_1);
|
|
|
|
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
|
|
|
|
|
|
|
|
struct brw_reg addr = vec8(brw_address_reg(0));
|
|
|
|
|
|
|
|
/* We need to move the indirect value into the address register. In
|
|
|
|
* order to make things make some sense, we want to respect at least the
|
|
|
|
* X component of the swizzle. In order to do that, we need to convert
|
|
|
|
* the subnr (probably 0) to an align1 subnr and add in the swizzle.
|
|
|
|
*/
|
|
|
|
assert(brw_is_single_value_swizzle(indirect.swizzle));
|
|
|
|
indirect.subnr = (indirect.subnr * 4 + BRW_GET_SWZ(indirect.swizzle, 0));
|
|
|
|
|
|
|
|
/* We then use a region of <8,4,0>:uw to pick off the first 2 bytes of
|
|
|
|
* the indirect and splat it out to all four channels of the given half
|
|
|
|
* of a0.
|
|
|
|
*/
|
|
|
|
indirect.subnr *= 2;
|
|
|
|
indirect = stride(retype(indirect, BRW_REGISTER_TYPE_UW), 8, 4, 0);
|
|
|
|
brw_ADD(p, addr, indirect, brw_imm_uw(imm_byte_offset));
|
|
|
|
|
|
|
|
/* Now we need to incorporate the swizzle from the source register */
|
|
|
|
if (reg.swizzle != BRW_SWIZZLE_XXXX) {
|
|
|
|
uint32_t uv_swiz = BRW_GET_SWZ(reg.swizzle, 0) << 2 |
|
|
|
|
BRW_GET_SWZ(reg.swizzle, 1) << 6 |
|
|
|
|
BRW_GET_SWZ(reg.swizzle, 2) << 10 |
|
|
|
|
BRW_GET_SWZ(reg.swizzle, 3) << 14;
|
|
|
|
uv_swiz |= uv_swiz << 16;
|
|
|
|
|
|
|
|
brw_ADD(p, addr, addr, brw_imm_uv(uv_swiz));
|
|
|
|
}
|
|
|
|
|
|
|
|
brw_MOV(p, dst, retype(brw_VxH_indirect(0, 0), reg.type));
|
|
|
|
|
|
|
|
brw_pop_insn_state(p);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-05-02 19:54:01 +01:00
|
|
|
static void
|
|
|
|
generate_zero_oob_push_regs(struct brw_codegen *p,
|
|
|
|
struct brw_stage_prog_data *prog_data,
|
|
|
|
struct brw_reg scratch,
|
|
|
|
struct brw_reg bit_mask_in)
|
|
|
|
{
|
|
|
|
const uint64_t want_zero = prog_data->zero_push_reg;
|
|
|
|
assert(want_zero);
|
|
|
|
|
|
|
|
assert(bit_mask_in.file == BRW_GENERAL_REGISTER_FILE);
|
|
|
|
assert(BRW_GET_SWZ(bit_mask_in.swizzle, 1) ==
|
|
|
|
BRW_GET_SWZ(bit_mask_in.swizzle, 0) + 1);
|
|
|
|
bit_mask_in.subnr += BRW_GET_SWZ(bit_mask_in.swizzle, 0) * 4;
|
|
|
|
bit_mask_in.type = BRW_REGISTER_TYPE_W;
|
|
|
|
|
|
|
|
/* Scratch should be 3 registers in the GRF */
|
|
|
|
assert(scratch.file == BRW_GENERAL_REGISTER_FILE);
|
|
|
|
scratch = vec8(scratch);
|
|
|
|
struct brw_reg mask_w16 = retype(scratch, BRW_REGISTER_TYPE_W);
|
|
|
|
struct brw_reg mask_d16 = retype(byte_offset(scratch, REG_SIZE),
|
|
|
|
BRW_REGISTER_TYPE_D);
|
|
|
|
|
|
|
|
brw_push_insn_state(p);
|
|
|
|
brw_set_default_access_mode(p, BRW_ALIGN_1);
|
|
|
|
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
|
|
|
|
|
|
|
|
for (unsigned i = 0; i < 64; i++) {
|
|
|
|
if (i % 16 == 0 && (want_zero & BITFIELD64_RANGE(i, 16))) {
|
|
|
|
brw_set_default_exec_size(p, BRW_EXECUTE_8);
|
|
|
|
brw_SHL(p, suboffset(mask_w16, 8),
|
|
|
|
vec1(byte_offset(bit_mask_in, i / 8)),
|
|
|
|
brw_imm_v(0x01234567));
|
|
|
|
brw_SHL(p, mask_w16, suboffset(mask_w16, 8), brw_imm_w(8));
|
|
|
|
|
|
|
|
brw_set_default_exec_size(p, BRW_EXECUTE_16);
|
|
|
|
brw_ASR(p, mask_d16, mask_w16, brw_imm_w(15));
|
|
|
|
}
|
|
|
|
|
|
|
|
if (want_zero & BITFIELD64_BIT(i)) {
|
|
|
|
unsigned push_start = prog_data->dispatch_grf_start_reg;
|
|
|
|
struct brw_reg push_reg =
|
|
|
|
retype(brw_vec8_grf(push_start + i, 0), BRW_REGISTER_TYPE_D);
|
|
|
|
|
|
|
|
brw_set_default_exec_size(p, BRW_EXECUTE_8);
|
|
|
|
brw_AND(p, push_reg, push_reg, vec1(suboffset(mask_d16, i)));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
brw_pop_insn_state(p);
|
|
|
|
}
|
|
|
|
|
2015-10-22 23:35:15 +01:00
|
|
|
static void
|
|
|
|
generate_code(struct brw_codegen *p,
|
|
|
|
const struct brw_compiler *compiler,
|
|
|
|
void *log_data,
|
|
|
|
const nir_shader *nir,
|
|
|
|
struct brw_vue_prog_data *prog_data,
|
2019-04-24 05:19:56 +01:00
|
|
|
const struct cfg_t *cfg,
|
2020-03-26 23:27:32 +00:00
|
|
|
const performance &perf,
|
2021-03-23 18:25:42 +00:00
|
|
|
struct brw_compile_stats *stats,
|
|
|
|
bool debug_enabled)
|
2011-05-02 17:45:40 +01:00
|
|
|
{
|
2021-04-05 21:19:39 +01:00
|
|
|
const struct intel_device_info *devinfo = p->devinfo;
|
2017-09-15 03:52:38 +01:00
|
|
|
const char *stage_abbrev = _mesa_shader_stage_to_abbrev(nir->info.stage);
|
2022-06-29 22:13:31 +01:00
|
|
|
struct disasm_info *disasm_info = disasm_initialize(p->isa, cfg);
|
2019-10-29 19:18:16 +00:00
|
|
|
|
|
|
|
/* `send_count` explicitly does not include spills or fills, as we'd
|
|
|
|
* like to use it as a metric for intentional memory access or other
|
|
|
|
* shared function use. Otherwise, subtle changes to scheduling or
|
|
|
|
* register allocation could cause it to fluctuate wildly - and that
|
|
|
|
* effect is already counted in spill/fill counts.
|
|
|
|
*/
|
2016-08-12 19:44:26 +01:00
|
|
|
int spill_count = 0, fill_count = 0;
|
2019-10-29 19:18:16 +00:00
|
|
|
int loop_count = 0, send_count = 0;
|
2013-06-13 19:23:08 +01:00
|
|
|
|
2014-08-29 17:07:08 +01:00
|
|
|
foreach_block_and_inst (block, vec4_instruction, inst, cfg) {
|
|
|
|
struct brw_reg src[3], dst;
|
2013-06-13 19:23:08 +01:00
|
|
|
|
2021-03-23 18:25:42 +00:00
|
|
|
if (unlikely(debug_enabled))
|
2017-11-16 01:08:42 +00:00
|
|
|
disasm_annotate(disasm_info, inst, p->next_insn_offset);
|
2013-06-13 19:23:08 +01:00
|
|
|
|
2014-08-29 17:07:08 +01:00
|
|
|
for (unsigned int i = 0; i < 3; i++) {
|
2015-11-20 05:51:37 +00:00
|
|
|
src[i] = inst->src[i].as_brw_reg();
|
2014-08-29 17:07:08 +01:00
|
|
|
}
|
2015-11-20 05:51:37 +00:00
|
|
|
dst = inst->dst.as_brw_reg();
|
2013-06-13 19:23:08 +01:00
|
|
|
|
2014-08-29 17:07:08 +01:00
|
|
|
brw_set_default_predicate_control(p, inst->predicate);
|
|
|
|
brw_set_default_predicate_inverse(p, inst->predicate_inverse);
|
2017-12-12 20:05:02 +00:00
|
|
|
brw_set_default_flag_reg(p, inst->flag_subreg / 2, inst->flag_subreg % 2);
|
2014-08-29 17:07:08 +01:00
|
|
|
brw_set_default_saturate(p, inst->saturate);
|
|
|
|
brw_set_default_mask_control(p, inst->force_writemask_all);
|
|
|
|
brw_set_default_acc_write_control(p, inst->writes_accumulator);
|
2013-06-13 19:23:08 +01:00
|
|
|
|
2016-06-17 07:49:44 +01:00
|
|
|
assert(inst->group % inst->exec_size == 0);
|
2017-04-13 00:54:49 +01:00
|
|
|
assert(inst->group % 4 == 0);
|
2016-08-29 09:10:30 +01:00
|
|
|
|
i965/vec4: Fix exec size for MOVs {SET,PICK}_{HIGH,LOW}_32BIT.
Otherwise for a pack_double_2x32_split opcode, we emit:
vec1 64 ssa_135 = pack_double_2x32_split ssa_133, ssa_134
mov(8) g5<1>UD g5<4>.xUD { align16 1Q compacted };
mov(8) g7<2>UD g5<4,4,1>UD { align1 1Q };
ERROR: When the destination spans two registers, the source must span two registers
(exceptions for scalar source and packed-word to packed-dword expansion)
mov(8) g8<2>UD g5.4<4,4,1>UD { align1 2N };
ERROR: The offset from the two source registers must be the same
mov(8) g5<1>UD g6<4>.xUD { align16 1Q compacted };
mov(8) g7.1<2>UD g5<4,4,1>UD { align1 1Q };
ERROR: When the destination spans two registers, the source must span two registers
(exceptions for scalar source and packed-word to packed-dword expansion)
mov(8) g8.1<2>UD g5.4<4,4,1>UD { align1 2N };
ERROR: The offset from the two source registers must be the same
The intention was to emit mov(4)s for the instructions that have ERROR
annotations.
See tests/spec/arb_gpu_shader_fp64/execution/vs-isinf-dvec.shader_test
for example.
v2 (Samuel):
- Instead of setting the exec size to a fixed value, don't double it
(Curro).
- Add PICK_{HIGH,LOW}_32BIT to the condition.
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
[ Francisco Jerez: Trivial rebase changes. ]
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2017-01-20 21:35:32 +00:00
|
|
|
/* There are some instructions where the destination is 64-bit
|
|
|
|
* but we retype it to a smaller type. In that case, we cannot
|
|
|
|
* double the exec_size.
|
|
|
|
*/
|
|
|
|
const bool is_df = (get_exec_type_size(inst) == 8 ||
|
|
|
|
inst->dst.type == BRW_REGISTER_TYPE_DF) &&
|
|
|
|
inst->opcode != VEC4_OPCODE_PICK_LOW_32BIT &&
|
|
|
|
inst->opcode != VEC4_OPCODE_PICK_HIGH_32BIT &&
|
|
|
|
inst->opcode != VEC4_OPCODE_SET_LOW_32BIT &&
|
|
|
|
inst->opcode != VEC4_OPCODE_SET_HIGH_32BIT;
|
|
|
|
|
2016-08-29 09:10:30 +01:00
|
|
|
unsigned exec_size = inst->exec_size;
|
2021-05-14 17:04:46 +01:00
|
|
|
if (devinfo->verx10 == 70 && is_df)
|
2016-08-29 09:10:30 +01:00
|
|
|
exec_size *= 2;
|
|
|
|
|
|
|
|
brw_set_default_exec_size(p, cvt(exec_size) - 1);
|
|
|
|
|
2016-06-17 07:49:44 +01:00
|
|
|
if (!inst->force_writemask_all)
|
|
|
|
brw_set_default_group(p, inst->group);
|
|
|
|
|
2021-03-29 22:41:58 +01:00
|
|
|
assert(inst->base_mrf + inst->mlen <= BRW_MAX_MRF(devinfo->ver));
|
2015-09-18 07:15:52 +01:00
|
|
|
assert(inst->mlen <= BRW_MAX_MSG_LENGTH);
|
|
|
|
|
2014-08-29 17:07:08 +01:00
|
|
|
unsigned pre_emit_nr_insn = p->nr_insn;
|
2013-06-13 19:23:08 +01:00
|
|
|
|
2014-08-29 17:07:08 +01:00
|
|
|
switch (inst->opcode) {
|
2014-10-24 07:22:09 +01:00
|
|
|
case VEC4_OPCODE_UNPACK_UNIFORM:
|
2014-08-29 17:07:08 +01:00
|
|
|
case BRW_OPCODE_MOV:
|
2021-05-04 21:30:27 +01:00
|
|
|
case VEC4_OPCODE_MOV_FOR_SCRATCH:
|
2014-08-29 17:07:08 +01:00
|
|
|
brw_MOV(p, dst, src[0]);
|
|
|
|
break;
|
|
|
|
case BRW_OPCODE_ADD:
|
|
|
|
brw_ADD(p, dst, src[0], src[1]);
|
|
|
|
break;
|
|
|
|
case BRW_OPCODE_MUL:
|
|
|
|
brw_MUL(p, dst, src[0], src[1]);
|
|
|
|
break;
|
|
|
|
case BRW_OPCODE_MACH:
|
|
|
|
brw_MACH(p, dst, src[0], src[1]);
|
|
|
|
break;
|
2013-06-13 19:23:08 +01:00
|
|
|
|
2014-08-29 17:07:08 +01:00
|
|
|
case BRW_OPCODE_MAD:
|
2021-03-29 22:41:58 +01:00
|
|
|
assert(devinfo->ver >= 6);
|
2014-08-29 17:07:08 +01:00
|
|
|
brw_MAD(p, dst, src[0], src[1], src[2]);
|
|
|
|
break;
|
2013-06-13 19:23:08 +01:00
|
|
|
|
2014-08-29 17:07:08 +01:00
|
|
|
case BRW_OPCODE_FRC:
|
|
|
|
brw_FRC(p, dst, src[0]);
|
|
|
|
break;
|
|
|
|
case BRW_OPCODE_RNDD:
|
|
|
|
brw_RNDD(p, dst, src[0]);
|
|
|
|
break;
|
|
|
|
case BRW_OPCODE_RNDE:
|
|
|
|
brw_RNDE(p, dst, src[0]);
|
|
|
|
break;
|
|
|
|
case BRW_OPCODE_RNDZ:
|
|
|
|
brw_RNDZ(p, dst, src[0]);
|
|
|
|
break;
|
2013-06-13 19:23:08 +01:00
|
|
|
|
2014-08-29 17:07:08 +01:00
|
|
|
case BRW_OPCODE_AND:
|
|
|
|
brw_AND(p, dst, src[0], src[1]);
|
|
|
|
break;
|
|
|
|
case BRW_OPCODE_OR:
|
|
|
|
brw_OR(p, dst, src[0], src[1]);
|
|
|
|
break;
|
|
|
|
case BRW_OPCODE_XOR:
|
|
|
|
brw_XOR(p, dst, src[0], src[1]);
|
|
|
|
break;
|
|
|
|
case BRW_OPCODE_NOT:
|
|
|
|
brw_NOT(p, dst, src[0]);
|
|
|
|
break;
|
|
|
|
case BRW_OPCODE_ASR:
|
|
|
|
brw_ASR(p, dst, src[0], src[1]);
|
|
|
|
break;
|
|
|
|
case BRW_OPCODE_SHR:
|
|
|
|
brw_SHR(p, dst, src[0], src[1]);
|
|
|
|
break;
|
|
|
|
case BRW_OPCODE_SHL:
|
|
|
|
brw_SHL(p, dst, src[0], src[1]);
|
|
|
|
break;
|
2013-06-13 19:23:08 +01:00
|
|
|
|
2014-08-29 17:07:08 +01:00
|
|
|
case BRW_OPCODE_CMP:
|
|
|
|
brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
|
|
|
|
break;
|
2021-02-13 22:11:30 +00:00
|
|
|
case BRW_OPCODE_CMPN:
|
|
|
|
brw_CMPN(p, dst, inst->conditional_mod, src[0], src[1]);
|
|
|
|
break;
|
2014-08-29 17:07:08 +01:00
|
|
|
case BRW_OPCODE_SEL:
|
|
|
|
brw_SEL(p, dst, src[0], src[1]);
|
|
|
|
break;
|
2013-06-13 19:23:08 +01:00
|
|
|
|
2014-08-29 17:07:08 +01:00
|
|
|
case BRW_OPCODE_DPH:
|
|
|
|
brw_DPH(p, dst, src[0], src[1]);
|
|
|
|
break;
|
2013-06-13 19:23:08 +01:00
|
|
|
|
2014-08-29 17:07:08 +01:00
|
|
|
case BRW_OPCODE_DP4:
|
|
|
|
brw_DP4(p, dst, src[0], src[1]);
|
|
|
|
break;
|
2013-06-13 19:23:08 +01:00
|
|
|
|
2014-08-29 17:07:08 +01:00
|
|
|
case BRW_OPCODE_DP3:
|
|
|
|
brw_DP3(p, dst, src[0], src[1]);
|
|
|
|
break;
|
2013-06-13 19:23:08 +01:00
|
|
|
|
2014-08-29 17:07:08 +01:00
|
|
|
case BRW_OPCODE_DP2:
|
|
|
|
brw_DP2(p, dst, src[0], src[1]);
|
|
|
|
break;
|
2013-06-13 19:23:08 +01:00
|
|
|
|
2014-08-29 17:07:08 +01:00
|
|
|
case BRW_OPCODE_F32TO16:
|
2021-03-29 22:41:58 +01:00
|
|
|
assert(devinfo->ver >= 7);
|
2014-08-29 17:07:08 +01:00
|
|
|
brw_F32TO16(p, dst, src[0]);
|
|
|
|
break;
|
2013-06-13 19:23:08 +01:00
|
|
|
|
2014-08-29 17:07:08 +01:00
|
|
|
case BRW_OPCODE_F16TO32:
|
2021-03-29 22:41:58 +01:00
|
|
|
assert(devinfo->ver >= 7);
|
2014-08-29 17:07:08 +01:00
|
|
|
brw_F16TO32(p, dst, src[0]);
|
|
|
|
break;
|
2013-06-13 19:23:08 +01:00
|
|
|
|
2014-08-29 17:07:08 +01:00
|
|
|
case BRW_OPCODE_LRP:
|
2021-03-29 22:41:58 +01:00
|
|
|
assert(devinfo->ver >= 6);
|
2014-08-29 17:07:08 +01:00
|
|
|
brw_LRP(p, dst, src[0], src[1], src[2]);
|
|
|
|
break;
|
2013-06-13 19:23:08 +01:00
|
|
|
|
2014-08-29 17:07:08 +01:00
|
|
|
case BRW_OPCODE_BFREV:
|
2021-03-29 22:41:58 +01:00
|
|
|
assert(devinfo->ver >= 7);
|
2014-08-29 17:07:08 +01:00
|
|
|
brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
|
|
|
|
retype(src[0], BRW_REGISTER_TYPE_UD));
|
|
|
|
break;
|
|
|
|
case BRW_OPCODE_FBH:
|
2021-03-29 22:41:58 +01:00
|
|
|
assert(devinfo->ver >= 7);
|
2017-06-30 23:10:17 +01:00
|
|
|
brw_FBH(p, retype(dst, src[0].type), src[0]);
|
2014-08-29 17:07:08 +01:00
|
|
|
break;
|
|
|
|
case BRW_OPCODE_FBL:
|
2021-03-29 22:41:58 +01:00
|
|
|
assert(devinfo->ver >= 7);
|
2017-06-30 23:10:17 +01:00
|
|
|
brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD),
|
|
|
|
retype(src[0], BRW_REGISTER_TYPE_UD));
|
2014-08-29 17:07:08 +01:00
|
|
|
break;
|
2016-06-21 23:14:03 +01:00
|
|
|
case BRW_OPCODE_LZD:
|
|
|
|
brw_LZD(p, dst, src[0]);
|
|
|
|
break;
|
2014-08-29 17:07:08 +01:00
|
|
|
case BRW_OPCODE_CBIT:
|
2021-03-29 22:41:58 +01:00
|
|
|
assert(devinfo->ver >= 7);
|
2017-06-30 23:10:17 +01:00
|
|
|
brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD),
|
|
|
|
retype(src[0], BRW_REGISTER_TYPE_UD));
|
2014-08-29 17:07:08 +01:00
|
|
|
break;
|
|
|
|
case BRW_OPCODE_ADDC:
|
2021-03-29 22:41:58 +01:00
|
|
|
assert(devinfo->ver >= 7);
|
2014-08-29 17:07:08 +01:00
|
|
|
brw_ADDC(p, dst, src[0], src[1]);
|
|
|
|
break;
|
|
|
|
case BRW_OPCODE_SUBB:
|
2021-03-29 22:41:58 +01:00
|
|
|
assert(devinfo->ver >= 7);
|
2014-08-29 17:07:08 +01:00
|
|
|
brw_SUBB(p, dst, src[0], src[1]);
|
|
|
|
break;
|
|
|
|
case BRW_OPCODE_MAC:
|
|
|
|
brw_MAC(p, dst, src[0], src[1]);
|
|
|
|
break;
|
2013-06-13 19:23:08 +01:00
|
|
|
|
2014-08-29 17:07:08 +01:00
|
|
|
case BRW_OPCODE_BFE:
|
2021-03-29 22:41:58 +01:00
|
|
|
assert(devinfo->ver >= 7);
|
2014-08-29 17:07:08 +01:00
|
|
|
brw_BFE(p, dst, src[0], src[1], src[2]);
|
|
|
|
break;
|
2011-05-02 17:45:40 +01:00
|
|
|
|
2014-08-29 17:07:08 +01:00
|
|
|
case BRW_OPCODE_BFI1:
|
2021-03-29 22:41:58 +01:00
|
|
|
assert(devinfo->ver >= 7);
|
2014-08-29 17:07:08 +01:00
|
|
|
brw_BFI1(p, dst, src[0], src[1]);
|
|
|
|
break;
|
|
|
|
case BRW_OPCODE_BFI2:
|
2021-03-29 22:41:58 +01:00
|
|
|
assert(devinfo->ver >= 7);
|
2014-08-29 17:07:08 +01:00
|
|
|
brw_BFI2(p, dst, src[0], src[1], src[2]);
|
|
|
|
break;
|
2011-05-02 17:45:40 +01:00
|
|
|
|
2014-08-29 17:07:08 +01:00
|
|
|
case BRW_OPCODE_IF:
|
2015-10-24 23:29:03 +01:00
|
|
|
if (!inst->src[0].is_null()) {
|
2021-03-29 23:40:04 +01:00
|
|
|
/* The instruction has an embedded compare (only allowed on gfx6) */
|
2021-03-29 22:41:58 +01:00
|
|
|
assert(devinfo->ver == 6);
|
2021-03-29 23:40:04 +01:00
|
|
|
gfx6_IF(p, inst->conditional_mod, src[0], src[1]);
|
2014-08-29 17:07:08 +01:00
|
|
|
} else {
|
|
|
|
brw_inst *if_inst = brw_IF(p, BRW_EXECUTE_8);
|
2015-04-15 02:00:06 +01:00
|
|
|
brw_inst_set_pred_control(p->devinfo, if_inst, inst->predicate);
|
2014-08-29 17:07:08 +01:00
|
|
|
}
|
|
|
|
break;
|
2011-10-26 21:53:11 +01:00
|
|
|
|
2014-08-29 17:07:08 +01:00
|
|
|
case BRW_OPCODE_ELSE:
|
|
|
|
brw_ELSE(p);
|
|
|
|
break;
|
|
|
|
case BRW_OPCODE_ENDIF:
|
|
|
|
brw_ENDIF(p);
|
|
|
|
break;
|
2011-05-02 17:45:40 +01:00
|
|
|
|
2014-08-29 17:07:08 +01:00
|
|
|
case BRW_OPCODE_DO:
|
|
|
|
brw_DO(p, BRW_EXECUTE_8);
|
|
|
|
break;
|
2011-08-07 21:36:11 +01:00
|
|
|
|
2014-08-29 17:07:08 +01:00
|
|
|
case BRW_OPCODE_BREAK:
|
|
|
|
brw_BREAK(p);
|
|
|
|
brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
|
|
|
|
break;
|
|
|
|
case BRW_OPCODE_CONTINUE:
|
|
|
|
brw_CONT(p);
|
|
|
|
brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
|
|
|
|
break;
|
2011-08-07 21:36:11 +01:00
|
|
|
|
2014-08-29 17:07:08 +01:00
|
|
|
case BRW_OPCODE_WHILE:
|
|
|
|
brw_WHILE(p);
|
2014-08-06 09:27:58 +01:00
|
|
|
loop_count++;
|
2014-08-29 17:07:08 +01:00
|
|
|
break;
|
2011-08-22 18:35:24 +01:00
|
|
|
|
2014-08-29 17:07:08 +01:00
|
|
|
case SHADER_OPCODE_RCP:
|
|
|
|
case SHADER_OPCODE_RSQ:
|
|
|
|
case SHADER_OPCODE_SQRT:
|
|
|
|
case SHADER_OPCODE_EXP2:
|
|
|
|
case SHADER_OPCODE_LOG2:
|
|
|
|
case SHADER_OPCODE_SIN:
|
|
|
|
case SHADER_OPCODE_COS:
|
2014-11-21 20:34:22 +00:00
|
|
|
assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
|
2021-03-29 22:41:58 +01:00
|
|
|
if (devinfo->ver >= 7) {
|
2021-03-29 23:40:04 +01:00
|
|
|
gfx6_math(p, dst, brw_math_function(inst->opcode), src[0],
|
2014-08-29 17:07:08 +01:00
|
|
|
brw_null_reg());
|
2021-03-29 22:41:58 +01:00
|
|
|
} else if (devinfo->ver == 6) {
|
2021-03-29 23:40:04 +01:00
|
|
|
generate_math_gfx6(p, inst, dst, src[0], brw_null_reg());
|
2014-08-29 17:07:08 +01:00
|
|
|
} else {
|
2021-03-29 23:40:04 +01:00
|
|
|
generate_math1_gfx4(p, inst, dst, src[0]);
|
2019-10-29 19:18:16 +00:00
|
|
|
send_count++;
|
2014-08-29 17:07:08 +01:00
|
|
|
}
|
|
|
|
break;
|
2013-04-04 22:10:18 +01:00
|
|
|
|
2014-08-29 17:07:08 +01:00
|
|
|
case SHADER_OPCODE_POW:
|
|
|
|
case SHADER_OPCODE_INT_QUOTIENT:
|
|
|
|
case SHADER_OPCODE_INT_REMAINDER:
|
2014-11-21 20:34:22 +00:00
|
|
|
assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
|
2021-03-29 22:41:58 +01:00
|
|
|
if (devinfo->ver >= 7) {
|
2021-03-29 23:40:04 +01:00
|
|
|
gfx6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
|
2021-03-29 22:41:58 +01:00
|
|
|
} else if (devinfo->ver == 6) {
|
2021-03-29 23:40:04 +01:00
|
|
|
generate_math_gfx6(p, inst, dst, src[0], src[1]);
|
2014-08-29 17:07:08 +01:00
|
|
|
} else {
|
2021-03-29 23:40:04 +01:00
|
|
|
generate_math2_gfx4(p, inst, dst, src[0], src[1]);
|
2019-10-29 19:18:16 +00:00
|
|
|
send_count++;
|
2014-08-29 17:07:08 +01:00
|
|
|
}
|
|
|
|
break;
|
2013-03-21 16:11:12 +00:00
|
|
|
|
2014-08-29 17:07:08 +01:00
|
|
|
case SHADER_OPCODE_TEX:
|
|
|
|
case SHADER_OPCODE_TXD:
|
|
|
|
case SHADER_OPCODE_TXF:
|
|
|
|
case SHADER_OPCODE_TXF_CMS:
|
2015-09-09 15:59:36 +01:00
|
|
|
case SHADER_OPCODE_TXF_CMS_W:
|
2014-08-29 17:07:08 +01:00
|
|
|
case SHADER_OPCODE_TXF_MCS:
|
|
|
|
case SHADER_OPCODE_TXL:
|
|
|
|
case SHADER_OPCODE_TXS:
|
|
|
|
case SHADER_OPCODE_TG4:
|
|
|
|
case SHADER_OPCODE_TG4_OFFSET:
|
2015-08-12 01:37:32 +01:00
|
|
|
case SHADER_OPCODE_SAMPLEINFO:
|
2017-09-15 03:52:38 +01:00
|
|
|
generate_tex(p, prog_data, nir->info.stage,
|
2017-01-06 09:13:24 +00:00
|
|
|
inst, dst, src[0], src[1], src[2]);
|
2019-10-29 19:18:16 +00:00
|
|
|
send_count++;
|
2014-08-29 17:07:08 +01:00
|
|
|
break;
|
2013-03-23 14:42:32 +00:00
|
|
|
|
2017-12-11 01:03:32 +00:00
|
|
|
case SHADER_OPCODE_GET_BUFFER_SIZE:
|
intel/vec4: Silence unused paramter warnings in brw_vec4_generator.cpp
src/intel/compiler/brw_vec4_generator.cpp: In function ‘void generate_gs_svb_write(brw_codegen*, brw_vue_prog_data*, brw::vec4_instruction*, brw_reg, brw_reg, brw_reg)’:
src/intel/compiler/brw_vec4_generator.cpp:488:49: warning: unused parameter ‘prog_data’ [-Wunused-parameter]
488 | struct brw_vue_prog_data *prog_data,
| ~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~
src/intel/compiler/brw_vec4_generator.cpp: In function ‘void generate_pull_constant_load(brw_codegen*, brw_vue_prog_data*, brw::vec4_instruction*, brw_reg, brw_reg, brw_reg)’:
src/intel/compiler/brw_vec4_generator.cpp:1269:55: warning: unused parameter ‘prog_data’ [-Wunused-parameter]
1269 | struct brw_vue_prog_data *prog_data,
| ~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~
src/intel/compiler/brw_vec4_generator.cpp: In function ‘void generate_get_buffer_size(brw_codegen*, brw_vue_prog_data*, brw::vec4_instruction*, brw_reg, brw_reg, brw_reg)’:
src/intel/compiler/brw_vec4_generator.cpp:1331:52: warning: unused parameter ‘prog_data’ [-Wunused-parameter]
1331 | struct brw_vue_prog_data *prog_data,
| ~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~
src/intel/compiler/brw_vec4_generator.cpp: In function ‘void generate_pull_constant_load_gen7(brw_codegen*, brw_vue_prog_data*, brw::vec4_instruction*, brw_reg, brw_reg, brw_reg)’:
src/intel/compiler/brw_vec4_generator.cpp:1357:60: warning: unused parameter ‘prog_data’ [-Wunused-parameter]
1357 | struct brw_vue_prog_data *prog_data,
| ~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6826>
2020-09-22 21:53:25 +01:00
|
|
|
generate_get_buffer_size(p, inst, dst, src[0], src[1]);
|
2019-10-29 19:18:16 +00:00
|
|
|
send_count++;
|
2017-12-11 01:03:32 +00:00
|
|
|
break;
|
|
|
|
|
2022-07-05 18:03:07 +01:00
|
|
|
case VEC4_VS_OPCODE_URB_WRITE:
|
2015-10-22 23:35:15 +01:00
|
|
|
generate_vs_urb_write(p, inst);
|
2019-10-29 19:18:16 +00:00
|
|
|
send_count++;
|
2014-08-29 17:07:08 +01:00
|
|
|
break;
|
2013-03-23 14:59:13 +00:00
|
|
|
|
2021-03-30 00:02:30 +01:00
|
|
|
case SHADER_OPCODE_GFX4_SCRATCH_READ:
|
2015-10-22 23:35:15 +01:00
|
|
|
generate_scratch_read(p, inst, dst, src[0]);
|
2016-08-12 19:44:26 +01:00
|
|
|
fill_count++;
|
2014-08-29 17:07:08 +01:00
|
|
|
break;
|
2013-03-23 15:18:43 +00:00
|
|
|
|
2021-03-30 00:02:30 +01:00
|
|
|
case SHADER_OPCODE_GFX4_SCRATCH_WRITE:
|
2015-10-22 23:35:15 +01:00
|
|
|
generate_scratch_write(p, inst, dst, src[0], src[1]);
|
2016-08-12 19:44:26 +01:00
|
|
|
spill_count++;
|
2014-08-29 17:07:08 +01:00
|
|
|
break;
|
2013-02-19 15:31:16 +00:00
|
|
|
|
2014-08-29 17:07:08 +01:00
|
|
|
case VS_OPCODE_PULL_CONSTANT_LOAD:
|
intel/vec4: Silence unused paramter warnings in brw_vec4_generator.cpp
src/intel/compiler/brw_vec4_generator.cpp: In function ‘void generate_gs_svb_write(brw_codegen*, brw_vue_prog_data*, brw::vec4_instruction*, brw_reg, brw_reg, brw_reg)’:
src/intel/compiler/brw_vec4_generator.cpp:488:49: warning: unused parameter ‘prog_data’ [-Wunused-parameter]
488 | struct brw_vue_prog_data *prog_data,
| ~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~
src/intel/compiler/brw_vec4_generator.cpp: In function ‘void generate_pull_constant_load(brw_codegen*, brw_vue_prog_data*, brw::vec4_instruction*, brw_reg, brw_reg, brw_reg)’:
src/intel/compiler/brw_vec4_generator.cpp:1269:55: warning: unused parameter ‘prog_data’ [-Wunused-parameter]
1269 | struct brw_vue_prog_data *prog_data,
| ~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~
src/intel/compiler/brw_vec4_generator.cpp: In function ‘void generate_get_buffer_size(brw_codegen*, brw_vue_prog_data*, brw::vec4_instruction*, brw_reg, brw_reg, brw_reg)’:
src/intel/compiler/brw_vec4_generator.cpp:1331:52: warning: unused parameter ‘prog_data’ [-Wunused-parameter]
1331 | struct brw_vue_prog_data *prog_data,
| ~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~
src/intel/compiler/brw_vec4_generator.cpp: In function ‘void generate_pull_constant_load_gen7(brw_codegen*, brw_vue_prog_data*, brw::vec4_instruction*, brw_reg, brw_reg, brw_reg)’:
src/intel/compiler/brw_vec4_generator.cpp:1357:60: warning: unused parameter ‘prog_data’ [-Wunused-parameter]
1357 | struct brw_vue_prog_data *prog_data,
| ~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6826>
2020-09-22 21:53:25 +01:00
|
|
|
generate_pull_constant_load(p, inst, dst, src[0], src[1]);
|
2019-10-29 19:18:16 +00:00
|
|
|
send_count++;
|
2014-08-29 17:07:08 +01:00
|
|
|
break;
|
2013-04-21 16:51:33 +01:00
|
|
|
|
2021-03-30 00:02:30 +01:00
|
|
|
case VS_OPCODE_PULL_CONSTANT_LOAD_GFX7:
|
2021-03-29 23:40:04 +01:00
|
|
|
generate_pull_constant_load_gfx7(p, inst, dst, src[0], src[1]);
|
2019-10-29 19:18:16 +00:00
|
|
|
send_count++;
|
2014-08-29 17:07:08 +01:00
|
|
|
break;
|
2013-04-21 16:51:33 +01:00
|
|
|
|
2022-07-05 18:03:07 +01:00
|
|
|
case VEC4_GS_OPCODE_URB_WRITE:
|
2015-10-22 23:35:15 +01:00
|
|
|
generate_gs_urb_write(p, inst);
|
2019-10-29 19:18:16 +00:00
|
|
|
send_count++;
|
2014-08-29 17:07:08 +01:00
|
|
|
break;
|
2014-01-25 20:55:24 +00:00
|
|
|
|
2022-07-05 18:03:07 +01:00
|
|
|
case VEC4_GS_OPCODE_URB_WRITE_ALLOCATE:
|
2015-10-22 23:35:15 +01:00
|
|
|
generate_gs_urb_write_allocate(p, inst);
|
2019-10-29 19:18:16 +00:00
|
|
|
send_count++;
|
2014-07-09 15:28:30 +01:00
|
|
|
break;
|
|
|
|
|
2014-07-18 09:36:10 +01:00
|
|
|
case GS_OPCODE_SVB_WRITE:
|
intel/vec4: Silence unused paramter warnings in brw_vec4_generator.cpp
src/intel/compiler/brw_vec4_generator.cpp: In function ‘void generate_gs_svb_write(brw_codegen*, brw_vue_prog_data*, brw::vec4_instruction*, brw_reg, brw_reg, brw_reg)’:
src/intel/compiler/brw_vec4_generator.cpp:488:49: warning: unused parameter ‘prog_data’ [-Wunused-parameter]
488 | struct brw_vue_prog_data *prog_data,
| ~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~
src/intel/compiler/brw_vec4_generator.cpp: In function ‘void generate_pull_constant_load(brw_codegen*, brw_vue_prog_data*, brw::vec4_instruction*, brw_reg, brw_reg, brw_reg)’:
src/intel/compiler/brw_vec4_generator.cpp:1269:55: warning: unused parameter ‘prog_data’ [-Wunused-parameter]
1269 | struct brw_vue_prog_data *prog_data,
| ~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~
src/intel/compiler/brw_vec4_generator.cpp: In function ‘void generate_get_buffer_size(brw_codegen*, brw_vue_prog_data*, brw::vec4_instruction*, brw_reg, brw_reg, brw_reg)’:
src/intel/compiler/brw_vec4_generator.cpp:1331:52: warning: unused parameter ‘prog_data’ [-Wunused-parameter]
1331 | struct brw_vue_prog_data *prog_data,
| ~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~
src/intel/compiler/brw_vec4_generator.cpp: In function ‘void generate_pull_constant_load_gen7(brw_codegen*, brw_vue_prog_data*, brw::vec4_instruction*, brw_reg, brw_reg, brw_reg)’:
src/intel/compiler/brw_vec4_generator.cpp:1357:60: warning: unused parameter ‘prog_data’ [-Wunused-parameter]
1357 | struct brw_vue_prog_data *prog_data,
| ~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6826>
2020-09-22 21:53:25 +01:00
|
|
|
generate_gs_svb_write(p, inst, dst, src[0], src[1]);
|
2019-10-29 19:18:16 +00:00
|
|
|
send_count++;
|
2014-07-18 09:36:10 +01:00
|
|
|
break;
|
|
|
|
|
2014-07-18 09:47:15 +01:00
|
|
|
case GS_OPCODE_SVB_SET_DST_INDEX:
|
2015-10-22 23:35:15 +01:00
|
|
|
generate_gs_svb_set_destination_index(p, inst, dst, src[0]);
|
2014-07-18 09:47:15 +01:00
|
|
|
break;
|
|
|
|
|
2014-08-29 17:07:08 +01:00
|
|
|
case GS_OPCODE_THREAD_END:
|
2015-10-22 23:35:15 +01:00
|
|
|
generate_gs_thread_end(p, inst);
|
2019-10-29 19:18:16 +00:00
|
|
|
send_count++;
|
2014-08-29 17:07:08 +01:00
|
|
|
break;
|
2012-11-27 22:10:52 +00:00
|
|
|
|
2014-08-29 17:07:08 +01:00
|
|
|
case GS_OPCODE_SET_WRITE_OFFSET:
|
2015-10-22 23:35:15 +01:00
|
|
|
generate_gs_set_write_offset(p, dst, src[0], src[1]);
|
2014-08-29 17:07:08 +01:00
|
|
|
break;
|
2013-09-11 22:01:50 +01:00
|
|
|
|
2014-08-29 17:07:08 +01:00
|
|
|
case GS_OPCODE_SET_VERTEX_COUNT:
|
2015-10-22 23:35:15 +01:00
|
|
|
generate_gs_set_vertex_count(p, dst, src[0]);
|
2014-08-29 17:07:08 +01:00
|
|
|
break;
|
2013-09-11 22:03:13 +01:00
|
|
|
|
2014-07-09 07:46:17 +01:00
|
|
|
case GS_OPCODE_FF_SYNC:
|
2015-10-22 23:35:15 +01:00
|
|
|
generate_gs_ff_sync(p, inst, dst, src[0], src[1]);
|
2019-10-29 19:18:16 +00:00
|
|
|
send_count++;
|
2014-07-09 07:46:17 +01:00
|
|
|
break;
|
|
|
|
|
2014-07-23 11:56:53 +01:00
|
|
|
case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
|
2015-10-22 23:35:15 +01:00
|
|
|
generate_gs_ff_sync_set_primitives(p, dst, src[0], src[1], src[2]);
|
2014-07-23 11:56:53 +01:00
|
|
|
break;
|
|
|
|
|
2014-07-24 11:14:27 +01:00
|
|
|
case GS_OPCODE_SET_PRIMITIVE_ID:
|
2015-10-22 23:35:15 +01:00
|
|
|
generate_gs_set_primitive_id(p, dst);
|
2014-07-24 11:14:27 +01:00
|
|
|
break;
|
|
|
|
|
2014-07-17 07:54:03 +01:00
|
|
|
case GS_OPCODE_SET_DWORD_2:
|
2015-10-22 23:35:15 +01:00
|
|
|
generate_gs_set_dword_2(p, dst, src[0]);
|
2014-08-29 17:07:08 +01:00
|
|
|
break;
|
2013-08-07 19:31:33 +01:00
|
|
|
|
2014-08-29 17:07:08 +01:00
|
|
|
case GS_OPCODE_PREPARE_CHANNEL_MASKS:
|
2015-10-22 23:35:15 +01:00
|
|
|
generate_gs_prepare_channel_masks(p, dst);
|
2014-08-29 17:07:08 +01:00
|
|
|
break;
|
2011-05-02 17:45:40 +01:00
|
|
|
|
2014-08-29 17:07:08 +01:00
|
|
|
case GS_OPCODE_SET_CHANNEL_MASKS:
|
2015-10-22 23:35:15 +01:00
|
|
|
generate_gs_set_channel_masks(p, dst, src[0]);
|
2014-08-29 17:07:08 +01:00
|
|
|
break;
|
2014-05-25 18:42:32 +01:00
|
|
|
|
2014-08-29 17:07:08 +01:00
|
|
|
case GS_OPCODE_GET_INSTANCE_ID:
|
2015-10-22 23:35:15 +01:00
|
|
|
generate_gs_get_instance_id(p, dst);
|
2014-08-29 17:07:08 +01:00
|
|
|
break;
|
2011-05-02 17:45:40 +01:00
|
|
|
|
2019-02-21 16:41:59 +00:00
|
|
|
case VEC4_OPCODE_UNTYPED_ATOMIC:
|
2015-07-20 15:38:15 +01:00
|
|
|
assert(src[2].file == BRW_IMMEDIATE_VALUE);
|
2015-10-23 03:41:30 +01:00
|
|
|
brw_untyped_atomic(p, dst, src[0], src[1], src[2].ud, inst->mlen,
|
2017-12-12 20:05:03 +00:00
|
|
|
!inst->dst.is_null(), inst->header_size);
|
2019-10-29 19:18:16 +00:00
|
|
|
send_count++;
|
2014-08-29 17:07:08 +01:00
|
|
|
break;
|
2011-05-02 17:45:40 +01:00
|
|
|
|
2019-02-21 16:41:59 +00:00
|
|
|
case VEC4_OPCODE_UNTYPED_SURFACE_READ:
|
2017-12-12 20:05:03 +00:00
|
|
|
assert(!inst->header_size);
|
2015-07-20 15:38:15 +01:00
|
|
|
assert(src[2].file == BRW_IMMEDIATE_VALUE);
|
2015-03-19 13:11:28 +00:00
|
|
|
brw_untyped_surface_read(p, dst, src[0], src[1], inst->mlen,
|
2015-10-23 03:41:30 +01:00
|
|
|
src[2].ud);
|
2019-10-29 19:18:16 +00:00
|
|
|
send_count++;
|
2014-08-29 17:07:08 +01:00
|
|
|
break;
|
2011-05-02 17:45:40 +01:00
|
|
|
|
2019-02-21 16:41:59 +00:00
|
|
|
case VEC4_OPCODE_UNTYPED_SURFACE_WRITE:
|
2015-04-23 12:24:14 +01:00
|
|
|
assert(src[2].file == BRW_IMMEDIATE_VALUE);
|
|
|
|
brw_untyped_surface_write(p, src[0], src[1], inst->mlen,
|
2017-12-12 20:05:03 +00:00
|
|
|
src[2].ud, inst->header_size);
|
2019-10-29 19:18:16 +00:00
|
|
|
send_count++;
|
2015-04-23 12:24:14 +01:00
|
|
|
break;
|
|
|
|
|
intel/fs,vec4: Pull stall logic for memory fences up into the IR
Instead of emitting the stall MOV "inside" the
SHADER_OPCODE_MEMORY_FENCE generation, use the scheduling fences when
creating the IR.
For IvyBridge, every (data cache) fence is accompained by a render
cache fence, that now is explicit in the IR, two
SHADER_OPCODE_MEMORY_FENCEs are emitted (with different SFIDs).
Because Begin and End interlock intrinsics are effectively memory
barriers, move its handling alongside the other memory barrier
intrinsics. The SHADER_OPCODE_INTERLOCK is still used to distinguish
if we are going to use a SENDC (for Begin) or regular SEND (for End).
This change is a preparation to allow emitting both SENDs in Gen11+
before we can stall on them.
Shader-db results for IVB (i965):
total instructions in shared programs: 11971190 -> 11971200 (<.01%)
instructions in affected programs: 11482 -> 11492 (0.09%)
helped: 0
HURT: 8
HURT stats (abs) min: 1 max: 3 x̄: 1.25 x̃: 1
HURT stats (rel) min: 0.03% max: 0.50% x̄: 0.14% x̃: 0.10%
95% mean confidence interval for instructions value: 0.66 1.84
95% mean confidence interval for instructions %-change: 0.01% 0.27%
Instructions are HURT.
Unlike the previous code, that used the `mov g1 g2` trick to force
both `g1` and `g2` to stall, the scheduling fence will generate `mov
null g1` and `mov null g2`. During review it was decided it was not
worth keeping the special codepath for the small effect will have.
Shader-db results for HSW (i965), BDW and SKL don't have a change
on instruction count, but do report changes in cycles count, showing
SKL results below
total cycles in shared programs: 341738444 -> 341710570 (<.01%)
cycles in affected programs: 7240002 -> 7212128 (-0.38%)
helped: 46
HURT: 5
helped stats (abs) min: 14 max: 1940 x̄: 676.22 x̃: 154
helped stats (rel) min: <.01% max: 2.62% x̄: 1.28% x̃: 0.95%
HURT stats (abs) min: 2 max: 1768 x̄: 646.40 x̃: 362
HURT stats (rel) min: <.01% max: 0.83% x̄: 0.28% x̃: 0.08%
95% mean confidence interval for cycles value: -777.71 -315.38
95% mean confidence interval for cycles %-change: -1.42% -0.83%
Cycles are helped.
This seems to be the effect of allocating two registers separatedly
instead of a single one with size 2, which causes different register
allocation, affecting the cycle estimates.
while ICL also has not change on instruction count but report changes
negative changes in cycles
total cycles in shared programs: 352665369 -> 352707484 (0.01%)
cycles in affected programs: 9608288 -> 9650403 (0.44%)
helped: 4
HURT: 104
helped stats (abs) min: 24 max: 128 x̄: 88.50 x̃: 101
helped stats (rel) min: <.01% max: 0.85% x̄: 0.46% x̃: 0.49%
HURT stats (abs) min: 2 max: 2016 x̄: 408.36 x̃: 48
HURT stats (rel) min: <.01% max: 3.31% x̄: 0.88% x̃: 0.45%
95% mean confidence interval for cycles value: 256.67 523.24
95% mean confidence interval for cycles %-change: 0.63% 1.03%
Cycles are HURT.
AFAICT this is the result of the case above.
Shader-db results for TGL have similar cycles result as ICL, but also
affect instructions
total instructions in shared programs: 17690586 -> 17690597 (<.01%)
instructions in affected programs: 64617 -> 64628 (0.02%)
helped: 55
HURT: 32
helped stats (abs) min: 1 max: 16 x̄: 4.13 x̃: 3
helped stats (rel) min: 0.05% max: 2.78% x̄: 0.86% x̃: 0.74%
HURT stats (abs) min: 1 max: 65 x̄: 7.44 x̃: 2
HURT stats (rel) min: 0.05% max: 4.58% x̄: 1.13% x̃: 0.69%
95% mean confidence interval for instructions value: -2.03 2.28
95% mean confidence interval for instructions %-change: -0.41% 0.15%
Inconclusive result (value mean confidence interval includes 0).
Now that more is done in the IR, more dependencies are visible and
more SWSB annotations are emitted. Mixed with different register
allocation decisions like above, some shaders will see more `sync
nops` while others able to avoid them.
Most of the new `sync nops` are also redundant and could be dropped,
which will be fixed in a separate change.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3278>
2020-01-17 23:07:44 +00:00
|
|
|
case SHADER_OPCODE_MEMORY_FENCE:
|
|
|
|
brw_memory_fence(p, dst, src[0], BRW_OPCODE_SEND,
|
|
|
|
brw_message_target(inst->sfid),
|
2021-10-27 22:11:27 +01:00
|
|
|
inst->desc,
|
intel/fs,vec4: Pull stall logic for memory fences up into the IR
Instead of emitting the stall MOV "inside" the
SHADER_OPCODE_MEMORY_FENCE generation, use the scheduling fences when
creating the IR.
For IvyBridge, every (data cache) fence is accompained by a render
cache fence, that now is explicit in the IR, two
SHADER_OPCODE_MEMORY_FENCEs are emitted (with different SFIDs).
Because Begin and End interlock intrinsics are effectively memory
barriers, move its handling alongside the other memory barrier
intrinsics. The SHADER_OPCODE_INTERLOCK is still used to distinguish
if we are going to use a SENDC (for Begin) or regular SEND (for End).
This change is a preparation to allow emitting both SENDs in Gen11+
before we can stall on them.
Shader-db results for IVB (i965):
total instructions in shared programs: 11971190 -> 11971200 (<.01%)
instructions in affected programs: 11482 -> 11492 (0.09%)
helped: 0
HURT: 8
HURT stats (abs) min: 1 max: 3 x̄: 1.25 x̃: 1
HURT stats (rel) min: 0.03% max: 0.50% x̄: 0.14% x̃: 0.10%
95% mean confidence interval for instructions value: 0.66 1.84
95% mean confidence interval for instructions %-change: 0.01% 0.27%
Instructions are HURT.
Unlike the previous code, that used the `mov g1 g2` trick to force
both `g1` and `g2` to stall, the scheduling fence will generate `mov
null g1` and `mov null g2`. During review it was decided it was not
worth keeping the special codepath for the small effect will have.
Shader-db results for HSW (i965), BDW and SKL don't have a change
on instruction count, but do report changes in cycles count, showing
SKL results below
total cycles in shared programs: 341738444 -> 341710570 (<.01%)
cycles in affected programs: 7240002 -> 7212128 (-0.38%)
helped: 46
HURT: 5
helped stats (abs) min: 14 max: 1940 x̄: 676.22 x̃: 154
helped stats (rel) min: <.01% max: 2.62% x̄: 1.28% x̃: 0.95%
HURT stats (abs) min: 2 max: 1768 x̄: 646.40 x̃: 362
HURT stats (rel) min: <.01% max: 0.83% x̄: 0.28% x̃: 0.08%
95% mean confidence interval for cycles value: -777.71 -315.38
95% mean confidence interval for cycles %-change: -1.42% -0.83%
Cycles are helped.
This seems to be the effect of allocating two registers separatedly
instead of a single one with size 2, which causes different register
allocation, affecting the cycle estimates.
while ICL also has not change on instruction count but report changes
negative changes in cycles
total cycles in shared programs: 352665369 -> 352707484 (0.01%)
cycles in affected programs: 9608288 -> 9650403 (0.44%)
helped: 4
HURT: 104
helped stats (abs) min: 24 max: 128 x̄: 88.50 x̃: 101
helped stats (rel) min: <.01% max: 0.85% x̄: 0.46% x̃: 0.49%
HURT stats (abs) min: 2 max: 2016 x̄: 408.36 x̃: 48
HURT stats (rel) min: <.01% max: 3.31% x̄: 0.88% x̃: 0.45%
95% mean confidence interval for cycles value: 256.67 523.24
95% mean confidence interval for cycles %-change: 0.63% 1.03%
Cycles are HURT.
AFAICT this is the result of the case above.
Shader-db results for TGL have similar cycles result as ICL, but also
affect instructions
total instructions in shared programs: 17690586 -> 17690597 (<.01%)
instructions in affected programs: 64617 -> 64628 (0.02%)
helped: 55
HURT: 32
helped stats (abs) min: 1 max: 16 x̄: 4.13 x̃: 3
helped stats (rel) min: 0.05% max: 2.78% x̄: 0.86% x̃: 0.74%
HURT stats (abs) min: 1 max: 65 x̄: 7.44 x̃: 2
HURT stats (rel) min: 0.05% max: 4.58% x̄: 1.13% x̃: 0.69%
95% mean confidence interval for instructions value: -2.03 2.28
95% mean confidence interval for instructions %-change: -0.41% 0.15%
Inconclusive result (value mean confidence interval includes 0).
Now that more is done in the IR, more dependencies are visible and
more SWSB annotations are emitted. Mixed with different register
allocation decisions like above, some shaders will see more `sync
nops` while others able to avoid them.
Most of the new `sync nops` are also redundant and could be dropped,
which will be fixed in a separate change.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3278>
2020-01-17 23:07:44 +00:00
|
|
|
/* commit_enable */ false,
|
|
|
|
/* bti */ 0);
|
|
|
|
send_count++;
|
2015-04-23 12:30:28 +01:00
|
|
|
break;
|
|
|
|
|
2016-09-16 01:24:10 +01:00
|
|
|
case SHADER_OPCODE_FIND_LIVE_CHANNEL: {
|
|
|
|
const struct brw_reg mask =
|
2017-09-15 03:52:38 +01:00
|
|
|
brw_stage_has_packed_dispatch(devinfo, nir->info.stage,
|
2016-09-16 01:24:10 +01:00
|
|
|
&prog_data->base) ? brw_imm_ud(~0u) :
|
|
|
|
brw_dmask_reg();
|
2022-03-17 07:46:21 +00:00
|
|
|
brw_find_live_channel(p, dst, mask, false);
|
2015-04-23 12:42:53 +01:00
|
|
|
break;
|
2016-09-16 01:24:10 +01:00
|
|
|
}
|
2015-04-23 12:42:53 +01:00
|
|
|
|
2015-02-20 18:14:24 +00:00
|
|
|
case SHADER_OPCODE_BROADCAST:
|
2016-05-19 08:10:03 +01:00
|
|
|
assert(inst->force_writemask_all);
|
2015-02-20 18:14:24 +00:00
|
|
|
brw_broadcast(p, dst, src[0], src[1]);
|
|
|
|
break;
|
|
|
|
|
2014-08-29 17:07:08 +01:00
|
|
|
case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
|
2015-10-22 23:35:15 +01:00
|
|
|
generate_unpack_flags(p, dst);
|
2014-08-29 17:07:08 +01:00
|
|
|
break;
|
2012-12-01 02:29:34 +00:00
|
|
|
|
2015-02-12 01:42:43 +00:00
|
|
|
case VEC4_OPCODE_MOV_BYTES: {
|
|
|
|
/* Moves the low byte from each channel, using an Align1 access mode
|
|
|
|
* and a <4,1,0> source region.
|
|
|
|
*/
|
|
|
|
assert(src[0].type == BRW_REGISTER_TYPE_UB ||
|
|
|
|
src[0].type == BRW_REGISTER_TYPE_B);
|
|
|
|
|
|
|
|
brw_set_default_access_mode(p, BRW_ALIGN_1);
|
|
|
|
src[0].vstride = BRW_VERTICAL_STRIDE_4;
|
|
|
|
src[0].width = BRW_WIDTH_1;
|
|
|
|
src[0].hstride = BRW_HORIZONTAL_STRIDE_0;
|
|
|
|
brw_MOV(p, dst, src[0]);
|
|
|
|
brw_set_default_access_mode(p, BRW_ALIGN_16);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2017-03-24 07:46:13 +00:00
|
|
|
case VEC4_OPCODE_DOUBLE_TO_F32:
|
|
|
|
case VEC4_OPCODE_DOUBLE_TO_D32:
|
|
|
|
case VEC4_OPCODE_DOUBLE_TO_U32: {
|
2016-02-17 09:32:05 +00:00
|
|
|
assert(type_sz(src[0].type) == 8);
|
2017-03-24 07:46:13 +00:00
|
|
|
assert(type_sz(dst.type) == 8);
|
|
|
|
|
|
|
|
brw_reg_type dst_type;
|
|
|
|
|
|
|
|
switch (inst->opcode) {
|
|
|
|
case VEC4_OPCODE_DOUBLE_TO_F32:
|
|
|
|
dst_type = BRW_REGISTER_TYPE_F;
|
|
|
|
break;
|
|
|
|
case VEC4_OPCODE_DOUBLE_TO_D32:
|
|
|
|
dst_type = BRW_REGISTER_TYPE_D;
|
|
|
|
break;
|
|
|
|
case VEC4_OPCODE_DOUBLE_TO_U32:
|
|
|
|
dst_type = BRW_REGISTER_TYPE_UD;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
unreachable("Not supported conversion");
|
|
|
|
}
|
|
|
|
dst = retype(dst, dst_type);
|
2015-08-13 23:36:05 +01:00
|
|
|
|
|
|
|
brw_set_default_access_mode(p, BRW_ALIGN_1);
|
|
|
|
|
2016-09-23 10:57:43 +01:00
|
|
|
/* When converting from DF->F, we set destination's stride as 2 as an
|
2022-06-22 17:31:08 +01:00
|
|
|
* alignment requirement. But in IVB/BYT, each DF implicitly writes
|
2016-09-23 10:57:43 +01:00
|
|
|
* two floats, being the first one the converted value. So we don't
|
|
|
|
* need to explicitly set stride 2, but 1.
|
|
|
|
*/
|
|
|
|
struct brw_reg spread_dst;
|
2021-05-14 17:04:46 +01:00
|
|
|
if (devinfo->verx10 == 70)
|
2016-09-23 10:57:43 +01:00
|
|
|
spread_dst = stride(dst, 8, 4, 1);
|
|
|
|
else
|
|
|
|
spread_dst = stride(dst, 8, 4, 2);
|
|
|
|
|
|
|
|
brw_MOV(p, spread_dst, src[0]);
|
|
|
|
|
2015-08-13 23:36:05 +01:00
|
|
|
brw_set_default_access_mode(p, BRW_ALIGN_16);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2016-02-17 09:32:05 +00:00
|
|
|
case VEC4_OPCODE_TO_DOUBLE: {
|
|
|
|
assert(type_sz(src[0].type) == 4);
|
|
|
|
assert(type_sz(dst.type) == 8);
|
2015-08-13 23:36:05 +01:00
|
|
|
|
|
|
|
brw_set_default_access_mode(p, BRW_ALIGN_1);
|
|
|
|
|
2017-01-13 02:05:58 +00:00
|
|
|
brw_MOV(p, dst, src[0]);
|
2015-08-13 23:36:05 +01:00
|
|
|
|
|
|
|
brw_set_default_access_mode(p, BRW_ALIGN_16);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2016-05-31 09:17:37 +01:00
|
|
|
case VEC4_OPCODE_PICK_LOW_32BIT:
|
|
|
|
case VEC4_OPCODE_PICK_HIGH_32BIT: {
|
|
|
|
/* Stores the low/high 32-bit of each 64-bit element in src[0] into
|
|
|
|
* dst using ALIGN1 mode and a <8,4,2>:UD region on the source.
|
|
|
|
*/
|
|
|
|
assert(type_sz(src[0].type) == 8);
|
|
|
|
assert(type_sz(dst.type) == 4);
|
|
|
|
|
|
|
|
brw_set_default_access_mode(p, BRW_ALIGN_1);
|
|
|
|
|
|
|
|
dst = retype(dst, BRW_REGISTER_TYPE_UD);
|
|
|
|
dst.hstride = BRW_HORIZONTAL_STRIDE_1;
|
|
|
|
|
|
|
|
src[0] = retype(src[0], BRW_REGISTER_TYPE_UD);
|
|
|
|
if (inst->opcode == VEC4_OPCODE_PICK_HIGH_32BIT)
|
|
|
|
src[0] = suboffset(src[0], 1);
|
2017-04-25 11:28:18 +01:00
|
|
|
src[0] = spread(src[0], 2);
|
2016-05-31 09:17:37 +01:00
|
|
|
brw_MOV(p, dst, src[0]);
|
|
|
|
|
|
|
|
brw_set_default_access_mode(p, BRW_ALIGN_16);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2016-06-17 11:19:35 +01:00
|
|
|
case VEC4_OPCODE_SET_LOW_32BIT:
|
|
|
|
case VEC4_OPCODE_SET_HIGH_32BIT: {
|
|
|
|
/* Reads consecutive 32-bit elements from src[0] and writes
|
|
|
|
* them to the low/high 32-bit of each 64-bit element in dst.
|
|
|
|
*/
|
|
|
|
assert(type_sz(src[0].type) == 4);
|
|
|
|
assert(type_sz(dst.type) == 8);
|
|
|
|
|
|
|
|
brw_set_default_access_mode(p, BRW_ALIGN_1);
|
|
|
|
|
|
|
|
dst = retype(dst, BRW_REGISTER_TYPE_UD);
|
|
|
|
if (inst->opcode == VEC4_OPCODE_SET_HIGH_32BIT)
|
|
|
|
dst = suboffset(dst, 1);
|
|
|
|
dst.hstride = BRW_HORIZONTAL_STRIDE_2;
|
|
|
|
|
|
|
|
src[0] = retype(src[0], BRW_REGISTER_TYPE_UD);
|
|
|
|
brw_MOV(p, dst, src[0]);
|
|
|
|
|
|
|
|
brw_set_default_access_mode(p, BRW_ALIGN_16);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2014-03-10 20:26:30 +00:00
|
|
|
case VEC4_OPCODE_PACK_BYTES: {
|
|
|
|
/* Is effectively:
|
|
|
|
*
|
|
|
|
* mov(8) dst<16,4,1>:UB src<4,1,0>:UB
|
|
|
|
*
|
|
|
|
* but destinations' only regioning is horizontal stride, so instead we
|
|
|
|
* have to use two instructions:
|
|
|
|
*
|
|
|
|
* mov(4) dst<1>:UB src<4,1,0>:UB
|
|
|
|
* mov(4) dst.16<1>:UB src.16<4,1,0>:UB
|
|
|
|
*
|
|
|
|
* where they pack the four bytes from the low and high four DW.
|
|
|
|
*/
|
2018-09-06 19:36:19 +01:00
|
|
|
assert(util_is_power_of_two_nonzero(dst.writemask));
|
2015-10-23 03:41:30 +01:00
|
|
|
unsigned offset = __builtin_ctz(dst.writemask);
|
2014-08-15 23:03:44 +01:00
|
|
|
|
2014-03-10 20:26:30 +00:00
|
|
|
dst.type = BRW_REGISTER_TYPE_UB;
|
|
|
|
|
|
|
|
brw_set_default_access_mode(p, BRW_ALIGN_1);
|
|
|
|
|
|
|
|
src[0].type = BRW_REGISTER_TYPE_UB;
|
|
|
|
src[0].vstride = BRW_VERTICAL_STRIDE_4;
|
|
|
|
src[0].width = BRW_WIDTH_1;
|
|
|
|
src[0].hstride = BRW_HORIZONTAL_STRIDE_0;
|
2014-08-15 23:03:44 +01:00
|
|
|
dst.subnr = offset * 4;
|
2014-03-10 20:26:30 +00:00
|
|
|
struct brw_inst *insn = brw_MOV(p, dst, src[0]);
|
2015-04-15 02:00:06 +01:00
|
|
|
brw_inst_set_exec_size(p->devinfo, insn, BRW_EXECUTE_4);
|
|
|
|
brw_inst_set_no_dd_clear(p->devinfo, insn, true);
|
|
|
|
brw_inst_set_no_dd_check(p->devinfo, insn, inst->no_dd_check);
|
2014-03-10 20:26:30 +00:00
|
|
|
|
|
|
|
src[0].subnr = 16;
|
2014-08-15 23:03:44 +01:00
|
|
|
dst.subnr = 16 + offset * 4;
|
2014-03-10 20:26:30 +00:00
|
|
|
insn = brw_MOV(p, dst, src[0]);
|
2015-04-15 02:00:06 +01:00
|
|
|
brw_inst_set_exec_size(p->devinfo, insn, BRW_EXECUTE_4);
|
|
|
|
brw_inst_set_no_dd_clear(p->devinfo, insn, inst->no_dd_clear);
|
|
|
|
brw_inst_set_no_dd_check(p->devinfo, insn, true);
|
2014-03-10 20:26:30 +00:00
|
|
|
|
|
|
|
brw_set_default_access_mode(p, BRW_ALIGN_16);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2021-05-02 19:54:01 +01:00
|
|
|
case VEC4_OPCODE_ZERO_OOB_PUSH_REGS:
|
|
|
|
generate_zero_oob_push_regs(p, &prog_data->base, dst, src[0]);
|
2021-06-13 06:50:32 +01:00
|
|
|
break;
|
2021-05-02 19:54:01 +01:00
|
|
|
|
2022-07-05 18:03:07 +01:00
|
|
|
case VEC4_TCS_OPCODE_URB_WRITE:
|
2015-11-17 09:07:39 +00:00
|
|
|
generate_tcs_urb_write(p, inst, src[0]);
|
2019-10-29 19:18:16 +00:00
|
|
|
send_count++;
|
2015-11-17 09:07:39 +00:00
|
|
|
break;
|
|
|
|
|
|
|
|
case VEC4_OPCODE_URB_READ:
|
|
|
|
generate_vec4_urb_read(p, inst, dst, src[0]);
|
2019-10-29 19:18:16 +00:00
|
|
|
send_count++;
|
2015-11-17 09:07:39 +00:00
|
|
|
break;
|
|
|
|
|
2022-07-05 18:03:07 +01:00
|
|
|
case VEC4_TCS_OPCODE_SET_INPUT_URB_OFFSETS:
|
2015-11-17 09:07:39 +00:00
|
|
|
generate_tcs_input_urb_offsets(p, dst, src[0], src[1]);
|
|
|
|
break;
|
|
|
|
|
2022-07-05 18:03:07 +01:00
|
|
|
case VEC4_TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
|
2015-11-17 09:07:39 +00:00
|
|
|
generate_tcs_output_urb_offsets(p, dst, src[0], src[1]);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case TCS_OPCODE_GET_INSTANCE_ID:
|
|
|
|
generate_tcs_get_instance_id(p, dst);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case TCS_OPCODE_GET_PRIMITIVE_ID:
|
|
|
|
generate_tcs_get_primitive_id(p, dst);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case TCS_OPCODE_CREATE_BARRIER_HEADER:
|
|
|
|
generate_tcs_create_barrier_header(p, prog_data, dst);
|
|
|
|
break;
|
|
|
|
|
2015-11-17 09:30:35 +00:00
|
|
|
case TES_OPCODE_CREATE_INPUT_READ_HEADER:
|
|
|
|
generate_tes_create_input_read_header(p, dst);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
|
|
|
|
generate_tes_add_indirect_urb_offset(p, dst, src[0], src[1]);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case TES_OPCODE_GET_PRIMITIVE_ID:
|
|
|
|
generate_tes_get_primitive_id(p, dst);
|
|
|
|
break;
|
|
|
|
|
2015-11-26 01:54:22 +00:00
|
|
|
case TCS_OPCODE_SRC0_010_IS_ZERO:
|
|
|
|
/* If src_reg had stride like fs_reg, we wouldn't need this. */
|
|
|
|
brw_MOV(p, brw_null_reg(), stride(src[0], 0, 1, 0));
|
|
|
|
break;
|
|
|
|
|
|
|
|
case TCS_OPCODE_RELEASE_INPUT:
|
|
|
|
generate_tcs_release_input(p, dst, src[0], src[1]);
|
2019-10-29 19:18:16 +00:00
|
|
|
send_count++;
|
2015-11-26 01:54:22 +00:00
|
|
|
break;
|
|
|
|
|
2015-12-24 21:09:26 +00:00
|
|
|
case TCS_OPCODE_THREAD_END:
|
|
|
|
generate_tcs_thread_end(p, inst);
|
2019-10-29 19:18:16 +00:00
|
|
|
send_count++;
|
2015-12-24 21:09:26 +00:00
|
|
|
break;
|
|
|
|
|
2015-11-17 09:07:39 +00:00
|
|
|
case SHADER_OPCODE_BARRIER:
|
|
|
|
brw_barrier(p, src[0]);
|
|
|
|
brw_WAIT(p);
|
2019-10-29 19:18:16 +00:00
|
|
|
send_count++;
|
2015-11-17 09:07:39 +00:00
|
|
|
break;
|
|
|
|
|
2015-11-24 05:39:15 +00:00
|
|
|
case SHADER_OPCODE_MOV_INDIRECT:
|
intel/compiler: Silence unused parameter warnings in generate_foo methods
Since all of the fs_generator::generate_foo methods take a fs_inst * as
the first parameter, just remove the name to quiet the compiler.
src/intel/compiler/brw_fs_generator.cpp: In member function ‘void fs_generator::generate_barrier(fs_inst*, brw_reg)’:
src/intel/compiler/brw_fs_generator.cpp:743:41: warning: unused parameter ‘inst’ [-Wunused-parameter]
fs_generator::generate_barrier(fs_inst *inst, struct brw_reg src)
^~~~
src/intel/compiler/brw_fs_generator.cpp: In member function ‘void fs_generator::generate_discard_jump(fs_inst*)’:
src/intel/compiler/brw_fs_generator.cpp:1326:46: warning: unused parameter ‘inst’ [-Wunused-parameter]
fs_generator::generate_discard_jump(fs_inst *inst)
^~~~
src/intel/compiler/brw_fs_generator.cpp: In member function ‘void fs_generator::generate_pack_half_2x16_split(fs_inst*, brw_reg, brw_reg, brw_reg)’:
src/intel/compiler/brw_fs_generator.cpp:1675:54: warning: unused parameter ‘inst’ [-Wunused-parameter]
fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
^~~~
src/intel/compiler/brw_fs_generator.cpp: In member function ‘void fs_generator::generate_shader_time_add(fs_inst*, brw_reg, brw_reg, brw_reg)’:
src/intel/compiler/brw_fs_generator.cpp:1743:49: warning: unused parameter ‘inst’ [-Wunused-parameter]
fs_generator::generate_shader_time_add(fs_inst *inst,
^~~~
src/intel/compiler/brw_vec4_generator.cpp: In function ‘void generate_set_simd4x2_header_gen9(brw_codegen*, brw::vec4_instruction*, brw_reg)’:
src/intel/compiler/brw_vec4_generator.cpp:1412:52: warning: unused parameter ‘inst’ [-Wunused-parameter]
vec4_instruction *inst,
^~~~
src/intel/compiler/brw_vec4_generator.cpp: In function ‘void generate_mov_indirect(brw_codegen*, brw::vec4_instruction*, brw_reg, brw_reg, brw_reg, brw_reg)’:
src/intel/compiler/brw_vec4_generator.cpp:1430:41: warning: unused parameter ‘inst’ [-Wunused-parameter]
vec4_instruction *inst,
^~~~
src/intel/compiler/brw_vec4_generator.cpp:1432:63: warning: unused parameter ‘length’ [-Wunused-parameter]
struct brw_reg indirect, struct brw_reg length)
^~~~~~
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-03-29 00:29:45 +01:00
|
|
|
generate_mov_indirect(p, inst, dst, src[0], src[1]);
|
2015-11-24 05:39:15 +00:00
|
|
|
break;
|
|
|
|
|
2016-07-07 07:38:22 +01:00
|
|
|
case BRW_OPCODE_DIM:
|
2021-09-22 13:06:58 +01:00
|
|
|
assert(devinfo->verx10 == 75);
|
2016-07-07 07:38:22 +01:00
|
|
|
assert(src[0].type == BRW_REGISTER_TYPE_DF);
|
|
|
|
assert(dst.type == BRW_REGISTER_TYPE_DF);
|
|
|
|
brw_DIM(p, dst, retype(src[0], BRW_REGISTER_TYPE_F));
|
|
|
|
break;
|
|
|
|
|
2014-08-29 17:07:08 +01:00
|
|
|
default:
|
2015-04-16 18:30:05 +01:00
|
|
|
unreachable("Unsupported opcode");
|
2014-08-29 17:07:08 +01:00
|
|
|
}
|
2011-05-02 17:45:40 +01:00
|
|
|
|
2014-08-15 23:03:44 +01:00
|
|
|
if (inst->opcode == VEC4_OPCODE_PACK_BYTES) {
|
|
|
|
/* Handled dependency hints in the generator. */
|
|
|
|
|
|
|
|
assert(!inst->conditional_mod);
|
|
|
|
} else if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
|
2012-12-01 02:29:34 +00:00
|
|
|
assert(p->nr_insn == pre_emit_nr_insn + 1 ||
|
2014-05-31 00:41:32 +01:00
|
|
|
!"conditional_mod, no_dd_check, or no_dd_clear set for IR "
|
|
|
|
"emitting more than 1 instruction");
|
2012-12-01 02:29:34 +00:00
|
|
|
|
2014-06-13 22:29:25 +01:00
|
|
|
brw_inst *last = &p->store[pre_emit_nr_insn];
|
2012-12-01 02:29:34 +00:00
|
|
|
|
2014-11-21 20:20:53 +00:00
|
|
|
if (inst->conditional_mod)
|
2015-04-15 02:00:06 +01:00
|
|
|
brw_inst_set_cond_modifier(p->devinfo, last, inst->conditional_mod);
|
|
|
|
brw_inst_set_no_dd_clear(p->devinfo, last, inst->no_dd_clear);
|
|
|
|
brw_inst_set_no_dd_check(p->devinfo, last, inst->no_dd_check);
|
2012-12-01 02:29:34 +00:00
|
|
|
}
|
2011-05-02 17:45:40 +01:00
|
|
|
}
|
|
|
|
|
2016-08-29 23:57:41 +01:00
|
|
|
brw_set_uip_jip(p, 0);
|
2017-11-16 01:08:42 +00:00
|
|
|
|
|
|
|
/* end of program sentinel */
|
|
|
|
disasm_new_inst_group(disasm_info, p->next_insn_offset);
|
2011-05-02 17:45:40 +01:00
|
|
|
|
2015-06-29 22:08:51 +01:00
|
|
|
#ifndef NDEBUG
|
2017-11-16 21:35:01 +00:00
|
|
|
bool validated =
|
2015-06-29 22:08:51 +01:00
|
|
|
#else
|
2021-03-25 18:36:58 +00:00
|
|
|
if (unlikely(debug_enabled))
|
2017-11-16 21:35:01 +00:00
|
|
|
#endif
|
2022-06-29 22:13:31 +01:00
|
|
|
brw_validate_instructions(&compiler->isa, p->store,
|
2017-04-29 01:05:44 +01:00
|
|
|
0, p->next_insn_offset,
|
2017-11-16 01:08:42 +00:00
|
|
|
disasm_info);
|
2015-06-29 22:08:51 +01:00
|
|
|
|
2014-05-25 22:56:41 +01:00
|
|
|
int before_size = p->next_insn_offset;
|
2017-11-16 01:08:42 +00:00
|
|
|
brw_compact_instructions(p, 0, disasm_info);
|
2014-05-25 22:56:41 +01:00
|
|
|
int after_size = p->next_insn_offset;
|
2014-05-19 18:20:37 +01:00
|
|
|
|
2021-03-23 18:25:42 +00:00
|
|
|
if (unlikely(debug_enabled)) {
|
2019-05-23 17:05:23 +01:00
|
|
|
unsigned char sha1[21];
|
|
|
|
char sha1buf[41];
|
2015-10-06 01:41:46 +01:00
|
|
|
|
2019-05-23 17:05:23 +01:00
|
|
|
_mesa_sha1_compute(p->store, p->next_insn_offset, sha1);
|
|
|
|
_mesa_sha1_format(sha1buf, sha1);
|
|
|
|
|
|
|
|
fprintf(stderr, "Native code for %s %s shader %s (sha1 %s):\n",
|
|
|
|
nir->info.label ? nir->info.label : "unnamed",
|
|
|
|
_mesa_shader_stage_to_string(nir->info.stage), nir->info.name,
|
|
|
|
sha1buf);
|
2014-05-25 18:46:55 +01:00
|
|
|
|
2019-05-23 17:05:23 +01:00
|
|
|
fprintf(stderr, "%s vec4 shader: %d instructions. %d loops. %u cycles. %d:%d "
|
2019-10-29 19:18:16 +00:00
|
|
|
"spills:fills, %u sends. Compacted %d to %d bytes (%.0f%%)\n",
|
2020-03-26 23:27:32 +00:00
|
|
|
stage_abbrev, before_size / 16, loop_count, perf.latency,
|
2019-10-29 19:18:16 +00:00
|
|
|
spill_count, fill_count, send_count, before_size, after_size,
|
2019-05-23 17:05:23 +01:00
|
|
|
100.0f * (before_size - after_size) / before_size);
|
|
|
|
|
|
|
|
/* overriding the shader makes disasm_info invalid */
|
|
|
|
if (!brw_try_override_assembly(p, 0, sha1buf)) {
|
2019-06-03 12:55:23 +01:00
|
|
|
dump_assembly(p->store, 0, p->next_insn_offset,
|
|
|
|
disasm_info, perf.block_latency);
|
2019-05-23 17:05:23 +01:00
|
|
|
} else {
|
|
|
|
fprintf(stderr, "Successfully overrode shader with sha1 %s\n\n", sha1buf);
|
|
|
|
}
|
2014-05-19 18:20:37 +01:00
|
|
|
}
|
2017-11-20 08:57:17 +00:00
|
|
|
ralloc_free(disasm_info);
|
2015-06-29 22:08:51 +01:00
|
|
|
assert(validated);
|
2014-11-14 20:46:44 +00:00
|
|
|
|
2021-07-29 22:13:27 +01:00
|
|
|
brw_shader_debug_log(compiler, log_data,
|
|
|
|
"%s vec4 shader: %d inst, %d loops, %u cycles, "
|
|
|
|
"%d:%d spills:fills, %u sends, "
|
2021-10-03 13:58:36 +01:00
|
|
|
"compacted %d to %d bytes.\n",
|
2021-07-29 22:13:27 +01:00
|
|
|
stage_abbrev, before_size / 16,
|
|
|
|
loop_count, perf.latency, spill_count,
|
|
|
|
fill_count, send_count, before_size, after_size);
|
2019-04-24 05:19:56 +01:00
|
|
|
if (stats) {
|
|
|
|
stats->dispatch_width = 0;
|
|
|
|
stats->instructions = before_size / 16;
|
2020-04-03 19:09:41 +01:00
|
|
|
stats->sends = send_count;
|
2019-04-24 05:19:56 +01:00
|
|
|
stats->loops = loop_count;
|
2020-03-26 23:27:32 +00:00
|
|
|
stats->cycles = perf.latency;
|
2019-04-24 05:19:56 +01:00
|
|
|
stats->spills = spill_count;
|
|
|
|
stats->fills = fill_count;
|
|
|
|
}
|
2014-05-25 18:42:32 +01:00
|
|
|
}
|
|
|
|
|
2015-10-22 23:01:27 +01:00
|
|
|
extern "C" const unsigned *
|
|
|
|
brw_vec4_generate_assembly(const struct brw_compiler *compiler,
|
|
|
|
void *log_data,
|
|
|
|
void *mem_ctx,
|
|
|
|
const nir_shader *nir,
|
|
|
|
struct brw_vue_prog_data *prog_data,
|
2019-04-24 05:19:56 +01:00
|
|
|
const struct cfg_t *cfg,
|
2020-03-26 23:27:32 +00:00
|
|
|
const performance &perf,
|
2021-03-23 18:25:42 +00:00
|
|
|
struct brw_compile_stats *stats,
|
|
|
|
bool debug_enabled)
|
2015-10-22 23:01:27 +01:00
|
|
|
{
|
2015-10-22 23:35:15 +01:00
|
|
|
struct brw_codegen *p = rzalloc(mem_ctx, struct brw_codegen);
|
2022-06-29 22:13:31 +01:00
|
|
|
brw_init_codegen(&compiler->isa, p, mem_ctx);
|
2015-10-22 23:35:15 +01:00
|
|
|
brw_set_default_access_mode(p, BRW_ALIGN_16);
|
2015-10-22 23:01:27 +01:00
|
|
|
|
2021-03-23 18:25:42 +00:00
|
|
|
generate_code(p, compiler, log_data, nir, prog_data, cfg, perf, stats,
|
|
|
|
debug_enabled);
|
2015-10-22 23:01:27 +01:00
|
|
|
|
2020-08-08 04:26:07 +01:00
|
|
|
assert(prog_data->base.const_data_size == 0);
|
|
|
|
if (nir->constant_data_size > 0) {
|
|
|
|
prog_data->base.const_data_size = nir->constant_data_size;
|
|
|
|
prog_data->base.const_data_offset =
|
|
|
|
brw_append_data(p, nir->constant_data, nir->constant_data_size, 32);
|
|
|
|
}
|
|
|
|
|
2018-02-27 00:34:55 +00:00
|
|
|
return brw_get_program(p, &prog_data->base.program_size);
|
2015-10-22 23:35:15 +01:00
|
|
|
}
|