i965/vec4: Refactor sampler message setup.
The next patch adds an additional case where the message header is necessary. So we want to do the g0 copy if inst->header_present is set, rather than inst->texture_offset. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
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@ -367,23 +367,28 @@ vec4_generator::generate_tex(vec4_instruction *inst,
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* to set it up explicitly and load the offset bitfield. Otherwise, we can
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* use an implied move from g0 to the first message register.
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*/
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if (inst->texture_offset) {
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/* Explicitly set up the message header by copying g0 to the MRF. */
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brw_push_insn_state(p);
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brw_set_mask_control(p, BRW_MASK_DISABLE);
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brw_MOV(p, retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD),
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retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
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if (inst->header_present) {
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if (brw->gen < 6 && !inst->texture_offset) {
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/* Set up an implied move from g0 to the MRF. */
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src = brw_vec8_grf(0, 0);
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} else {
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struct brw_reg header =
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retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD);
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/* Then set the offset bits in DWord 2. */
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brw_set_access_mode(p, BRW_ALIGN_1);
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brw_MOV(p,
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retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, inst->base_mrf, 2),
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BRW_REGISTER_TYPE_UD),
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brw_imm_ud(inst->texture_offset));
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brw_pop_insn_state(p);
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} else if (inst->header_present) {
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/* Set up an implied move from g0 to the MRF. */
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src = brw_vec8_grf(0, 0);
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/* Explicitly set up the message header by copying g0 to the MRF. */
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brw_push_insn_state(p);
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brw_set_mask_control(p, BRW_MASK_DISABLE);
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brw_MOV(p, header, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
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brw_set_access_mode(p, BRW_ALIGN_1);
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if (inst->texture_offset) {
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/* Set the texel offset bits in DWord 2. */
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brw_MOV(p, get_element_ud(header, 2),
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brw_imm_ud(inst->texture_offset));
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}
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brw_pop_insn_state(p);
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}
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}
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uint32_t return_format;
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