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intel/compiler: Rename vec4 state URB opcodes to have VEC4_ prefix 

An argument could be made that all stage-specific opcodes for vec4
stages should be prefixed with VEC4_ like the stage-agnostic opcodes.
I'll leave those additional sed jobs for another day.

    egrep -lr '(VS|GS|TCS)_OPCODE_URB_WRITE' src |\
    while read f; do
        sed --in-place 's/\(VS\|GS\|TCS\)_OPCODE_URB_WRITE/VEC4_\1_OPCODE_URB_WRITE/g' $f
    done

    egrep -lr 'T.S_OPCODE[_A-Z]*URB_OFFSETS' src |\
    while read f; do
        sed --in-place 's/\(T.S_OPCODE[_A-Z]*URB_OFFSETS\)/VEC4_\1/g' $f
    done

Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17379>
This commit is contained in:
Ian Romanick 2022-07-05 10:03:07 -07:00 committed by Marge Bot
parent f7c741c058
commit b909ac350f
11 changed files with 50 additions and 50 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
src/intel/compiler/brw_eu_defines.h
View File

@ -580,7 +580,7 @@ enum opcode {
FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET,
FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET,
VS_OPCODE_URB_WRITE,
VEC4_VS_OPCODE_URB_WRITE,
VS_OPCODE_PULL_CONSTANT_LOAD,
VS_OPCODE_PULL_CONSTANT_LOAD_GFX7,
@ -589,11 +589,11 @@ enum opcode {
/**
* Write geometry shader output data to the URB.
*
* Unlike VS_OPCODE_URB_WRITE, this opcode doesn't do an implied move from
* Unlike VEC4_VS_OPCODE_URB_WRITE, this opcode doesn't do an implied move from
* R0 to the first MRF. This allows the geometry shader to override the
* "Slot {0,1} Offset" fields in the message header.
*/
GS_OPCODE_URB_WRITE,
VEC4_GS_OPCODE_URB_WRITE,
/**
* Write geometry shader output data to the URB and request a new URB
@ -601,7 +601,7 @@ enum opcode {
*
* This opcode doesn't do an implied move from R0 to the first MRF.
*/
GS_OPCODE_URB_WRITE_ALLOCATE,
VEC4_GS_OPCODE_URB_WRITE_ALLOCATE,
/**
* Terminate the geometry shader thread by doing an empty URB write.
@ -775,9 +775,9 @@ enum opcode {
VEC4_OPCODE_URB_READ,
TCS_OPCODE_GET_INSTANCE_ID,
TCS_OPCODE_URB_WRITE,
TCS_OPCODE_SET_INPUT_URB_OFFSETS,
TCS_OPCODE_SET_OUTPUT_URB_OFFSETS,
VEC4_TCS_OPCODE_URB_WRITE,
VEC4_TCS_OPCODE_SET_INPUT_URB_OFFSETS,
VEC4_TCS_OPCODE_SET_OUTPUT_URB_OFFSETS,
TCS_OPCODE_GET_PRIMITIVE_ID,
TCS_OPCODE_CREATE_BARRIER_HEADER,
TCS_OPCODE_SRC0_010_IS_ZERO,

12
src/intel/compiler/brw_ir_performance.cpp
View File

@ -842,8 +842,8 @@ namespace {
case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
case TCS_OPCODE_GET_INSTANCE_ID:
case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
case VEC4_TCS_OPCODE_SET_INPUT_URB_OFFSETS:
case VEC4_TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
case TES_OPCODE_CREATE_INPUT_READ_HEADER:
if (devinfo->ver >= 8)
return calculate_desc(info, EU_UNIT_FPU, 22 /* XXX */, 0, 0,
@ -929,12 +929,12 @@ namespace {
case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
case VEC4_OPCODE_URB_READ:
case VS_OPCODE_URB_WRITE:
case GS_OPCODE_URB_WRITE:
case GS_OPCODE_URB_WRITE_ALLOCATE:
case VEC4_VS_OPCODE_URB_WRITE:
case VEC4_GS_OPCODE_URB_WRITE:
case VEC4_GS_OPCODE_URB_WRITE_ALLOCATE:
case GS_OPCODE_THREAD_END:
case GS_OPCODE_FF_SYNC:
case TCS_OPCODE_URB_WRITE:
case VEC4_TCS_OPCODE_URB_WRITE:
case TCS_OPCODE_RELEASE_INPUT:
case TCS_OPCODE_THREAD_END:
return calculate_desc(info, EU_UNIT_URB, 2, 0, 0, 0, 6 /* XXX */,

14
src/intel/compiler/brw_shader.cpp
View File

@ -474,7 +474,7 @@ brw_instruction_name(const struct brw_isa_info *isa, enum opcode op)
case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
return "interp_per_slot_offset";
case VS_OPCODE_URB_WRITE:
case VEC4_VS_OPCODE_URB_WRITE:
return "vs_urb_write";
case VS_OPCODE_PULL_CONSTANT_LOAD:
return "pull_constant_load";
@ -484,9 +484,9 @@ brw_instruction_name(const struct brw_isa_info *isa, enum opcode op)
case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
return "unpack_flags_simd4x2";
case GS_OPCODE_URB_WRITE:
case VEC4_GS_OPCODE_URB_WRITE:
return "gs_urb_write";
case GS_OPCODE_URB_WRITE_ALLOCATE:
case VEC4_GS_OPCODE_URB_WRITE_ALLOCATE:
return "gs_urb_write_allocate";
case GS_OPCODE_THREAD_END:
return "gs_thread_end";
@ -531,11 +531,11 @@ brw_instruction_name(const struct brw_isa_info *isa, enum opcode op)
return "urb_read";
case TCS_OPCODE_GET_INSTANCE_ID:
return "tcs_get_instance_id";
case TCS_OPCODE_URB_WRITE:
case VEC4_TCS_OPCODE_URB_WRITE:
return "tcs_urb_write";
case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
case VEC4_TCS_OPCODE_SET_INPUT_URB_OFFSETS:
return "tcs_set_input_urb_offsets";
case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
case VEC4_TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
return "tcs_set_output_urb_offsets";
case TCS_OPCODE_GET_PRIMITIVE_ID:
return "tcs_get_primitive_id";
@ -1143,7 +1143,7 @@ backend_instruction::has_side_effects() const
case FS_OPCODE_FB_WRITE_LOGICAL:
case FS_OPCODE_REP_FB_WRITE:
case SHADER_OPCODE_BARRIER:
case TCS_OPCODE_URB_WRITE:
case VEC4_TCS_OPCODE_URB_WRITE:
case TCS_OPCODE_RELEASE_INPUT:
case SHADER_OPCODE_RND_MODE:
case SHADER_OPCODE_FLOAT_CONTROL_MODE:

20
src/intel/compiler/brw_vec4.cpp
View File

@ -155,7 +155,7 @@ vec4_instruction::is_send_from_grf() const
case VEC4_OPCODE_UNTYPED_SURFACE_READ:
case VEC4_OPCODE_UNTYPED_SURFACE_WRITE:
case VEC4_OPCODE_URB_READ:
case TCS_OPCODE_URB_WRITE:
case VEC4_TCS_OPCODE_URB_WRITE:
case TCS_OPCODE_RELEASE_INPUT:
case SHADER_OPCODE_BARRIER:
return true;
@ -187,8 +187,8 @@ bool
vec4_instruction::has_source_and_destination_hazard() const
{
switch (opcode) {
case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
case VEC4_TCS_OPCODE_SET_INPUT_URB_OFFSETS:
case VEC4_TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
return true;
default:
@ -209,7 +209,7 @@ vec4_instruction::size_read(unsigned arg) const
case VEC4_OPCODE_UNTYPED_ATOMIC:
case VEC4_OPCODE_UNTYPED_SURFACE_READ:
case VEC4_OPCODE_UNTYPED_SURFACE_WRITE:
case TCS_OPCODE_URB_WRITE:
case VEC4_TCS_OPCODE_URB_WRITE:
if (arg == 0)
return mlen * REG_SIZE;
break;
@ -283,8 +283,8 @@ vec4_instruction::can_do_writemask(const struct intel_device_info *devinfo)
case VEC4_OPCODE_SET_HIGH_32BIT:
case VS_OPCODE_PULL_CONSTANT_LOAD:
case VS_OPCODE_PULL_CONSTANT_LOAD_GFX7:
case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
case VEC4_TCS_OPCODE_SET_INPUT_URB_OFFSETS:
case VEC4_TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
case TES_OPCODE_CREATE_INPUT_READ_HEADER:
case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
case VEC4_OPCODE_URB_READ:
@ -343,7 +343,7 @@ vec4_instruction::implied_mrf_writes() const
case SHADER_OPCODE_POW:
case TCS_OPCODE_THREAD_END:
return 2;
case VS_OPCODE_URB_WRITE:
case VEC4_VS_OPCODE_URB_WRITE:
return 1;
case VS_OPCODE_PULL_CONSTANT_LOAD:
return 2;
@ -351,13 +351,13 @@ vec4_instruction::implied_mrf_writes() const
return 2;
case SHADER_OPCODE_GFX4_SCRATCH_WRITE:
return 3;
case GS_OPCODE_URB_WRITE:
case GS_OPCODE_URB_WRITE_ALLOCATE:
case VEC4_GS_OPCODE_URB_WRITE:
case VEC4_GS_OPCODE_URB_WRITE_ALLOCATE:
case GS_OPCODE_THREAD_END:
return 0;
case GS_OPCODE_FF_SYNC:
return 1;
case TCS_OPCODE_URB_WRITE:
case VEC4_TCS_OPCODE_URB_WRITE:
return 0;
case SHADER_OPCODE_TEX:
case SHADER_OPCODE_TXL:

4
src/intel/compiler/brw_vec4_cse.cpp
View File

@ -75,8 +75,8 @@ is_expression(const vec4_instruction *const inst)
case VEC4_OPCODE_UNPACK_UNIFORM:
case SHADER_OPCODE_FIND_LIVE_CHANNEL:
case SHADER_OPCODE_BROADCAST:
case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
case VEC4_TCS_OPCODE_SET_INPUT_URB_OFFSETS:
case VEC4_TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
return true;
case SHADER_OPCODE_RCP:
case SHADER_OPCODE_RSQ:

12
src/intel/compiler/brw_vec4_generator.cpp
View File

@ -1815,7 +1815,7 @@ generate_code(struct brw_codegen *p,
send_count++;
break;
case VS_OPCODE_URB_WRITE:
case VEC4_VS_OPCODE_URB_WRITE:
generate_vs_urb_write(p, inst);
send_count++;
break;
@ -1840,12 +1840,12 @@ generate_code(struct brw_codegen *p,
send_count++;
break;
case GS_OPCODE_URB_WRITE:
case VEC4_GS_OPCODE_URB_WRITE:
generate_gs_urb_write(p, inst);
send_count++;
break;
case GS_OPCODE_URB_WRITE_ALLOCATE:
case VEC4_GS_OPCODE_URB_WRITE_ALLOCATE:
generate_gs_urb_write_allocate(p, inst);
send_count++;
break;
@ -2110,7 +2110,7 @@ generate_code(struct brw_codegen *p,
generate_zero_oob_push_regs(p, &prog_data->base, dst, src[0]);
break;
case TCS_OPCODE_URB_WRITE:
case VEC4_TCS_OPCODE_URB_WRITE:
generate_tcs_urb_write(p, inst, src[0]);
send_count++;
break;
@ -2120,11 +2120,11 @@ generate_code(struct brw_codegen *p,
send_count++;
break;
case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
case VEC4_TCS_OPCODE_SET_INPUT_URB_OFFSETS:
generate_tcs_input_urb_offsets(p, dst, src[0], src[1]);
break;
case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
case VEC4_TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
generate_tcs_output_urb_offsets(p, dst, src[0], src[1]);
break;

4
src/intel/compiler/brw_vec4_gs_visitor.cpp
View File

@ -257,7 +257,7 @@ vec4_gs_visitor::emit_urb_write_opcode(bool complete)
*/
(void) complete;
vec4_instruction *inst = emit(GS_OPCODE_URB_WRITE);
vec4_instruction *inst = emit(VEC4_GS_OPCODE_URB_WRITE);
inst->offset = gs_prog_data->control_data_header_size_hwords;
inst->urb_write_flags = BRW_URB_WRITE_PER_SLOT_OFFSET;
@ -371,7 +371,7 @@ vec4_gs_visitor::emit_control_data_bits()
dst_reg mrf_reg2(MRF, base_mrf + 1);
inst = emit(MOV(mrf_reg2, this->control_data_bits));
inst->force_writemask_all = true;
inst = emit(GS_OPCODE_URB_WRITE);
inst = emit(VEC4_GS_OPCODE_URB_WRITE);
inst->urb_write_flags = urb_write_flags;
inst->base_mrf = base_mrf;
inst->mlen = 2;

8
src/intel/compiler/brw_vec4_tcs.cpp
View File

@ -161,7 +161,7 @@ vec4_tcs_visitor::emit_input_urb_read(const dst_reg &dst,
/* Set up the message header to reference the proper parts of the URB */
dst_reg header = dst_reg(this, glsl_type::uvec4_type);
inst = emit(TCS_OPCODE_SET_INPUT_URB_OFFSETS, header, vertex_index,
inst = emit(VEC4_TCS_OPCODE_SET_INPUT_URB_OFFSETS, header, vertex_index,
indirect_offset);
inst->force_writemask_all = true;
@ -194,7 +194,7 @@ vec4_tcs_visitor::emit_output_urb_read(const dst_reg &dst,
/* Set up the message header to reference the proper parts of the URB */
dst_reg header = dst_reg(this, glsl_type::uvec4_type);
inst = emit(TCS_OPCODE_SET_OUTPUT_URB_OFFSETS, header,
inst = emit(VEC4_TCS_OPCODE_SET_OUTPUT_URB_OFFSETS, header,
brw_imm_ud(dst.writemask << first_component), indirect_offset);
inst->force_writemask_all = true;
@ -223,14 +223,14 @@ vec4_tcs_visitor::emit_urb_write(const src_reg &value,
src_reg message(this, glsl_type::uvec4_type, 2);
vec4_instruction *inst;
inst = emit(TCS_OPCODE_SET_OUTPUT_URB_OFFSETS, dst_reg(message),
inst = emit(VEC4_TCS_OPCODE_SET_OUTPUT_URB_OFFSETS, dst_reg(message),
brw_imm_ud(writemask), indirect_offset);
inst->force_writemask_all = true;
inst = emit(MOV(byte_offset(dst_reg(retype(message, value.type)), REG_SIZE),
value));
inst->force_writemask_all = true;
inst = emit(TCS_OPCODE_URB_WRITE, dst_null_f(), message);
inst = emit(VEC4_TCS_OPCODE_URB_WRITE, dst_null_f(), message);
inst->offset = base_offset;
inst->mlen = 2;
inst->base_mrf = -1;

4
src/intel/compiler/brw_vec4_tes.cpp
View File

@ -94,7 +94,7 @@ void
vec4_tes_visitor::emit_urb_write_header(int mrf)
{
/* No need to do anything for DS; an implied write to this MRF will be
* performed by VS_OPCODE_URB_WRITE.
* performed by VEC4_VS_OPCODE_URB_WRITE.
*/
(void) mrf;
}
@ -103,7 +103,7 @@ vec4_tes_visitor::emit_urb_write_header(int mrf)
vec4_instruction *
vec4_tes_visitor::emit_urb_write_opcode(bool complete)
{
vec4_instruction *inst = emit(VS_OPCODE_URB_WRITE);
vec4_instruction *inst = emit(VEC4_VS_OPCODE_URB_WRITE);
inst->urb_write_flags = complete ?
BRW_URB_WRITE_EOT_COMPLETE : BRW_URB_WRITE_NO_FLAGS;

4
src/intel/compiler/brw_vec4_vs_visitor.cpp
View File

@ -37,7 +37,7 @@ void
vec4_vs_visitor::emit_urb_write_header(int mrf)
{
/* No need to do anything for VS; an implied write to this MRF will be
* performed by VS_OPCODE_URB_WRITE.
* performed by VEC4_VS_OPCODE_URB_WRITE.
*/
(void) mrf;
}
@ -46,7 +46,7 @@ vec4_vs_visitor::emit_urb_write_header(int mrf)
vec4_instruction *
vec4_vs_visitor::emit_urb_write_opcode(bool complete)
{
vec4_instruction *inst = emit(VS_OPCODE_URB_WRITE);
vec4_instruction *inst = emit(VEC4_VS_OPCODE_URB_WRITE);
inst->urb_write_flags = complete ?
BRW_URB_WRITE_EOT_COMPLETE : BRW_URB_WRITE_NO_FLAGS;

4
src/intel/compiler/gfx6_gs_visitor.cpp
View File

@ -293,7 +293,7 @@ gfx6_gs_visitor::emit_snb_gs_urb_write_opcode(bool complete, int base_mrf,
if (!complete) {
/* If the vertex is not complete we don't have to do anything special */
inst = emit(GS_OPCODE_URB_WRITE);
inst = emit(VEC4_GS_OPCODE_URB_WRITE);
inst->urb_write_flags = BRW_URB_WRITE_NO_FLAGS;
} else {
/* Otherwise we always request to allocate a new VUE handle. If this is
@ -304,7 +304,7 @@ gfx6_gs_visitor::emit_snb_gs_urb_write_opcode(bool complete, int base_mrf,
* which would require to end the program with an IF/ELSE/ENDIF block,
* something we do not want.
*/
inst = emit(GS_OPCODE_URB_WRITE_ALLOCATE);
inst = emit(VEC4_GS_OPCODE_URB_WRITE_ALLOCATE);
inst->urb_write_flags = BRW_URB_WRITE_COMPLETE;
inst->dst = dst_reg(MRF, base_mrf);
inst->src[0] = this->temp;